hybrid sc-i b t l -v h efficiency switched … buck and boost converter topologies due to their...

HYBRID SC-INDUCTIVE BASED TOPOLOGIES FOR LOW-VOLUME HIGH-

EFFICIENCY SWITCHED-MODE POWER SUPPLIES

by

Seyed-Behzad Mahdavikhah-Mehrabad

A thesis submitted in conformity with the requirements

for the degree of Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering

University of Toronto

© Copyright by Behzad Mahdavikhah 2014

ii

Hybrid SC-Inductive Based Topologies for Low-Volume High-

Efficiency Switched-Mode Power Supplies

Seyed-Behzad Mahdavikhah-Mehrabad

Doctor of Philosophy

Graduate Department of Electrical and Computer Engineering

University of Toronto

2014

Abstract

Switched-mode power supplies (SMPS) are widely used as the voltage or current regulators for

electronic devices. The most commonly used SMPS are inductive converters based on

conventional buck and boost converter topologies due to their simplicity and relatively high

power density and efficiency. However, in applications with large voltage difference between

their inputs and outputs, these converters suffer from excessive losses and increased volume due

to more demanding filtering and also cooling requirements. Therefore strong and ever increasing

demands for developing smaller and more efficient SMPS with high conversion ratios exist.

In this work two new converter topologies suitable for applications with large input-to-output

voltage difference are introduced for both input voltage step-down and step-up in two different

types of applications, i.e. for dc-dc converters and rectifiers with power factor correction. These

converters are developed based on the concept of merging Switched-capacitor (SC) and

inductive based converter stages by means of newly emerged digital controllers, improving

iii

efficiency and reducing the overall volume of the converter. Hence, the benefits of high power

density SC-based converters are exploited and at the same time the input-to-output voltage ratio

for the inductive stage is reduced improving its power density and efficiency. Compared to two-

stage solutions, by merging SC and inductive based stages, switches between two stages are

shared, reducing conduction losses, intermediate/flying capacitors are eliminated and controllers

are unified.

The buck-based, voltage step-down solution combines a capacitive divider and an interleaved

buck to reduce the volume of multi-phase step-down converters. Experimental results obtained

with a 7V-to-1V, 10A, 1 MHz prototype demonstrate that the merged capacitor converter has

15% smaller inductor, 13% smaller output capacitor, up to 35% lower power losses and 15%

shorter settling time after transients.

In the boost-based voltage step-up solution, the improvements are achieved by replacing the

output capacitor of the boost converter with a non-symmetric active capacitive divider, with a

2:1 division ratio, effectively providing four-level converter behavior. Experimental results

obtained with a 350 W, 200 kHz, universal input voltage (85Vrms - 265Vrms) PFC prototype

demonstrate 66% reduction of boost converter inductor and up to 10% improvement of

efficiency.

iv

Acknowledgements

I wish to express my deepest appreciation to my advisor, Professor Aleksandar Prodić, for

accepting me into the power electronics group and his invaluable advice, support and

encouragement throughout my PhD studies. Professor Prodić's knowledge, vision and passion for

research along with his dedication and unique personality provided me a mentorship truly

beyond my expectations. I have thoroughly enjoyed working in the Laboratory for Power

Management and Integrated SMPS under his supervision.

I would also like to thank my dissertation committee members, Dr. Óscar García, Dr. Reza

Iravani, Dr. Peter Lehn and Dr. Zeb Tate for their insight and their valuable and thoughtful

feedbacks.

Grateful regards to all my friends and colleagues in the Laboratory for Power Management and

Integrated SMPS, Amir Parayandeh, SM Ahsanuzzaman, Aleksandar Radić, Zdravko Lukić,

Conny Huerta Oliviares, Massimo Tarulli, Mahmoud Shousha, Adrian Straka, Parth Jane, Tim

Mcrae, Amr Amin and Nenad Vukadinovic who made this journey an enjoyable one through

their friendship and also collaborations and discussions on numerous projects.

My deepest gratitude to my parents, my grandmother and my sister for their invaluable support

in many significant ways that can never be matched with anything. I will always be grateful for

their support.

v

Finally I would like to acknowledge the support of Department of Electrical and Computer

Engineering at the University of Toronto. Financial support from the Energy System Department

is gratefully acknowledged.

vi

Contents

Chapter 1 Introduction...............................................................................................................1

1.1 Motivation ............................................................................................................................1

1.2 Thesis Objectives .................................................................................................................5

1.3 Thesis Organization and Contributions ...............................................................................6

1.4 Thesis Outline ......................................................................................................................8

References .................................................................................................................................10

Chapter 2 Background and Previous Art .................................................................................11

2.1 Topology Limits.................................................................................................................12

2.2 Reactive Components Volume ..........................................................................................13

2.2.1 Inductor Volume ....................................................................................................13

2.2.2 Output Capacitor Volume ......................................................................................14

2.3 Converter Losses ................................................................................................................15

vii

2.4 Volume reduction techniques ............................................................................................16

2.4.1 Increasing Switching Frequency ............................................................................16

2.4.2 Interleaving techniques ..........................................................................................18

2.4.3 Non-linear Controllers ...........................................................................................18

2.4.4 Ripple Cancellation ................................................................................................19

2.5 Switched Capacitor Converters..........................................................................................19

2.6 Two-Stage Converter topologies .......................................................................................22

2.7 Topologies Merging Inductive-based Solutions and Capacitive Attenuator .....................24

2.8 References ..........................................................................................................................26

Chapter 3 Digitally Controlled Multi-Phase Buck-Converter with Merged Capacitive

Attenuator ..................................................................................................................................32

3.1 Introduction ........................................................................................................................33

3.2 Principle of Operation and System Description.................................................................35

3.2.1 Steady-state operation and elimination of the output capacitor of the SC stage ...37

3.2.2 Transient and low-input mode ...............................................................................42

3.3 Practical Implementation ...................................................................................................44

3.3.1 Output filter reduction............................................................................................44

3.3.2 Component voltage ratings and start up transient ..................................................45

3.3.3 Conduction losses and switch selection .................................................................49

3.4 Experimental system and results ........................................................................................50

3.5 Conclusions ........................................................................................................................57

3.6 References ..........................................................................................................................57

Chapter 4 Low-Volume PFC Rectifier Based On Non-Symmetric Multi-Level Boost

Converter ...................................................................................................................................60

4.1 Introduction ........................................................................................................................61

viii

4.2 Principle of Operation of The Non-Symmetric Multi-Level Boost-Based (NSMB)

Front end PFC Stage ..........................................................................................................65

4.2.1 Non-symmetric active capacitive divider ..............................................................68

4.2.2 Centre tap voltage balancing and isolated downstream stages ..............................78

4.3 Practical Controller Implementation ..................................................................................80

4.3.1 Input current and bus voltage regulator .................................................................80

4.3.2 Mode selector and sampling sequence generator...................................................83

4.3.3 Centre-tap voltage regulator ..................................................................................88

4.3.4 Design Tradeoffs ....................................................................................................91

4.3.5 Extension to Higher Power Levels ........................................................................92

4.4 Experimental System and Results ......................................................................................93

4.5 Conclusions ......................................................................................................................107

4.6 References ........................................................................................................................108

Chapter 5 ....................................................................................................................................112

Conclusions and Future Work .....................................................................................................112

5 113

5.1 Digitally Controlled Multi-Phase Buck-Converter with Merged Capacitive Attenuator 113

5.1.1 Conclusions ..........................................................................................................113

5.1.2 Future Work .........................................................................................................114

5.2 Low-Volume PFC Rectifier Based On Non-Symmetric Multi-Level Boost Converter ..115

5.2.1 Conclusions ..........................................................................................................115

5.2.2 Future Work .........................................................................................................117

5.3 References ........................................................................................................................118

Appendix A Analysis of Conduction losses for optimized design of switching

components .............................................................................................................................119

ix

A.1 Analytical comparison of Conduction losses ...................................................................120

A.2 References ........................................................................................................................122

x

List of Tables

Table 3.1. MSCB converter component voltage ratings (assuming small ac ripple). .................. 46

Table 3.2. MSCB and multi-phase buck filter components parameters. ...................................... 51

Table 4.1: Comparison of NSMB Converter Parameters with Boost and 3-level PFC ................ 93

Thesis.doc#_Toc392157094

xi

List of Figures

Figure 1.1. Comparison of overall area occupied by power supplies (shown in red boxes) to the

overall PCB area for, a) a battery operated Google Galaxy Nexus 7 Tablet [4]; b) an ac powered

Panasonic VIERA TX-P50VT30E plasma TV [5]. ........................................................................ 3

Figure 1.2. Block diagram of a 2-phase merged switch capacitor buck (MSCB) converter and its

digital controller. ............................................................................................................................. 6

Figure 1.3. Block diagram of the non-symmetric multi-level buck (NSMB) based PFC rectifier

and its controller. ............................................................................................................................ 7

Figure 2.1. Most common non-isolated inductive-based converter topologies. a. buck converter.

b. boost converter .......................................................................................................................... 12

Figure 2.2. A 3-to-1 ratio down-step ladder network switched capacitor converter, Φi represents

phase of operation of switches. ..................................................................................................... 20

Figure 2.3. Capacitive energy transfer modeling with a virtual resistor [47] ............................... 21

Figure 2.4. SMPS volume reduction using two inductive converter stages ................................. 23

Figure 2.5. SMPS volume reduction using two-stage approach utilizing a SC voltage attenuator

....................................................................................................................................................... 23

Figure 2.6. Single-phase buck converter with merged capacitive attenuator [55]........................ 24

Figure 2.7. A four-level boost-derived flying capacitor multi-level converter [58]. .................... 25

xii

Figure 2.8. The three-level boot converter [57]. ........................................................................... 26


digital controller. ........................................................................................................................... 34

Figure 3.2. Operating modes of the capacitive attenuator; top: mode A; bottom: mode B. ......... 37

Figure 3.3. Key waveforms of the MSCB converter. ................................................................... 38

Figure 3.4. Approximate dc equivalent circuit of the converter. .................................................. 40

Figure 3.5. Converter configuration during a light-to-heavy load transient and low input voltage

range Vbatt<2Vout. ........................................................................................................................... 43

Figure 3.6. Converter configuration at start-up ............................................................................ 47

Figure 3.7. start-up transient of LC undamped input filter ........................................................... 49

Figure 3.8. Equivalent circuits of the top and bottom phase of the downstream buck for the both

portions of a switching interval..................................................................................................... 50

Figure 3.9. SC stage waveforms and gating signals during steady state operation; top to bottom:

Ch.3 (top): input current, iin(t) (200mA/div); Ch.4 (upper middle): resonance capacitor voltage,

vcr(t) (200 mV/div); Ch.2 (lower middle): bottom input capacitor voltage, vc2(t) (0.5V/div); Ch.4

(bottom): top input capacitor voltage, vc1(t) (0.5V/div); digital channels 1 to 9 are gating signal

G1 to G9. Time scale is 200 ns/div. Operating conditions: vin= 7 V, Vout = 1 V, Pout ~ 2.5 W. ... 52

Figure 3.10. Transient response for buck converter; top to bottom: Ch.4 (top): output voltage,

vout(t) (50mV/div); Ch.2 (upper middle): switching node voltage for top phase, vx1(t) (10V/div);

xiii

Ch.1 (lower middle): top phase inductor current, iL1(t) (2A/div); Ch.3 (bottom): bottom phase

inductor current, iL2(t) (2A/div); Time scale is 2 us/div. Operating conditions: vin= 7 V, Vout = 1

V, load current step of 2A to 8A. .................................................................................................. 53

Figure 3.11. Transient response for MSCB converter: Ch.4 (top): output voltage, vout(t)

(50mV/div); Ch.2 (upper middle): switching node voltage for top phase, vx1(t) (10V/div); Ch.1

(lower middle): top phase inductor current, iL1(t) (2A/div); Ch.3 (bottom): bottom phase inductor

current, iL2(t) (2A/div); Time scale is 2 us/div. Operating conditions: vin= 7 V, Vout = 1 V, load

current step of 2A to 8A................................................................................................................ 54

Figure 3.12. Start-up transient of MSCB converter: Ch.4 (top): output voltage, vout(t) (1V/div);

Ch.3 (upper middle): resonance capacitor voltage, vcr(t) (2V/div); Ch.2 (lower middle): top input

capacitor voltage, vc1(t) (2V/div); Ch.4 (bottom): bottom input capacitor voltage, vc2(t) (2V/div);

Time scale is 5 ms/div. Operating conditions: start up from zero state to vin= 7 V, Vout = 1 V, Pout

~ 2.5 W. ......................................................................................................................................... 55

Figure 3.13. Efficiency and loss comparison of buck and MSCB converters for 7V-to-1V

operating condition. ...................................................................................................................... 56

Figure 4.1: Non-symmetric multi-level boost (NSMB) based PFC rectifier and its downstream

stage. ............................................................................................................................................. 63

Figure 4.2: Equivalent circuit for the analysis of the inductor voltage swing and the voltage

waveforms of (a) a general boost-based converter and (b) the conventional boost. ..................... 66

xiv

Figure 4.3: Mode 1 of operation of the non-symmetric multi-level boost front-end stage: a) input

voltage range for mode 1; b) equivalent circuit of the converter during inductor charging phase;

c) equivalent circuit during the discharging.................................................................................. 69

Figure 4.4: Mode 2 of operation of the NSMB front-end stage: a) input voltage range for mode 2;

b) equivalent circuit of the converter during inductor charging phase; c) equivalent circuit during

the discharging. ............................................................................................................................. 70



the discharging. ............................................................................................................................. 71

Figure 4.6. Waveforms of the output capacitor voltage of an ideal PFC circuit; instantaneous

input power, voltage and current waveforms (a); decomposition of input power components (b);

and output capacitor voltage ripple (c) ......................................................................................... 74

Figure 4.7: The input filter and parasitic capacitances of the boost PFC circuit (top) and NSMB

PFC (bottom) circuits. ................................................................................................................... 77

Figure 4.8: Block diagram of the centre-tap voltage balancing system based on the downstream

converter current steering. ............................................................................................................ 80

Figure 4.9: Block diagram of the input current and bus voltage regulator. .................................. 81

Figure 4.10: Block diagram of the mode selector and sampling sequence generator................... 83

Figure 4.11: State flow diagram of the mode selector logic. ........................................................ 85

xv

Figure 4.12: Waveforms of the sampling sequence generator. ..................................................... 86

Figure 4.13: Problem of utilizing bypass diode in the NSMB topology. ..................................... 87

Figure 4.14: Centre tap voltage controller regulating operation of a forward based downstream

stage. ............................................................................................................................................. 89

Figure 4.15: Key waveforms of the centre-tap voltage regulator (from top to bottom): cd(t) –

pulse width modulated signal of the downstream stage controller; cd1(t) – control signal for Qd1;

cd2(t) – control signal for Qd2; i1(t) – discharging current of the top capacitor of the NSMB; i2(t) –

discharging current of the bottom capacitor of the NSMB. .......................................................... 90

Figure 4.16: Bridgeless NSMB converter topology. .................................................................... 92

Figure 4.17: Key waveforms of the conventional boost-based PFC rectifier; top to bottom: Ch.1

(top): attenuated output voltage, Hvbus(t) (2 V/div); Ch.2 (upper middle): switching node voltage,

vx(t) (200 V/div); Ch.3 (lower middle): input line current, iL(t) (0.5A/div); Ch.4 (bottom): input

line voltage, vin(t) (200 V/div). Time scale is 1 ms/div. Operating conditions: vline = 220 Vrms,

Vbus = 400 V, Pout = 100 W, C = 100 F , L = 680 H. ................................................................ 94

Figure 4.18: Key waveforms of the NSM-based PFC rectifier; top to bottom: Ch.1 (top):

attenuated output voltage, Hvbus(t) (2 V/div); Ch.2 (upper middle): switching node voltage, vx(t)

(200 V/div); Ch.3 (lower middle): input line current, iL(t) (0.5A/div); Ch.4 (bottom): input line

voltage, vin(t) (200 V/div). Time scale is 1 ms/div. Operating conditions vline = 220 Vrms, Vbus =

400 V, Pout = 100 W, Ctop = 150 F, Cbottom= 300 F , L = 680 H. ............................................ 95

xvi




line voltage, vin(t) (200 V/div). Time scale is 1 ms/div. Operating conditions: vline = 90 Vrms, Vbus

= 400 V, Pout = 100 W, C = 100 F , L = 680 H. ....................................................................... 96





= 400 V, Pout = 100 W, C = 100 F , L = 680 H. ....................................................................... 97

Figure 4.21: Transitions from mode 1 to mode 2 (top) and from mode 2 to mode 3 (bottom);

Ch.m1(top): input line voltage, vin(t) (200 V/div); Ch.2 (upper middle): switching node voltage,

vx(t) (200V/div); Ch.4 (middle): gating signal of SW1, c1(t) (20 V/div); Ch.1 (lower middle):

gating signal of SW2, c2(t) (20 V/div); Ch.3 (bottom): input line current, iL(t), (0.5 A/div); digital

input: mode control signal (0 = mode 1, 1 = mode 2, 2 = mode 3). Time scale is 5 s/div.

Operating conditions vline = 220 Vrms, Vbus = 400 V, Pout = 100 W, Ctop = 150 F, Cbottom = 300

F, L = 230 H. ........................................................................................................................... 98

Figure 4.22: Capacitor taps voltage regulation with the downstream stage currents; top to bottom:

Ch.1 (top): top capacitor voltage, vupper(t) (100 V/div); Ch.2 (upper middle): bottom capacitor

voltage, vbottom(t) (100V/div); Ch.4 (lower middle): discharging current of bottom capacitor, i2(t)

( 1 A/div); Ch.3 (bottom): discharging current of top capacitor, i1(t), (1 A/div);. Time scale is 2

xvii

s/div. Operating conditions vline = 220 Vrms, Vbus = 400 V, Pout = 70 W, Ctop = 150 F, Cbottom =

300 F, L = 230 H. ..................................................................................................................... 99

Figure 4.23: Amplitudes of harmonics (multiples of 50 Hz) around line frequency and the

switching frequency for the NSMB-based PFC prototype (top) and the conventional boost based

prototype (bottom). ..................................................................................................................... 101

Figure 4.24: Efficiency comparison of the conventional boost, three level boost and NSMB PFC

converters for the line input of 265 Vrms. .................................................................................... 102


converters for the line input of 85 Vrms ....................................................................................... 102

Figure 4.26: Loss break down analysis for the conventional boost, three level boost and NSMB

PFC converters for 85Vrms and 265 Vrms input voltages at the light load operating condition

(50W). Length of each bar is normalized based on the losses of the boost at 90Vrms which is

9.8W. ........................................................................................................................................... 104



(350W for 85Vrms and 400W for 265Vrms). Length of each bar is normalized based on the losses

of the boost at 90Vrms , which are 50.5W. ................................................................................... 105

Figure 4.28: Normalized volume distributions of conventional boost-based PFC and three other

solution. In case of the latter three cases, a volume break down in case of implementation with

optimal switches, i.e. lower voltage/current rated switches in single package, is also shown. .. 106

xviii

List of Acronyms

DPWM Digital Pulse Width Modulator SMPM

AC Alternating Current

ADC Analog-to-Digital Converter

CCM Continuous Conduction Mode

CM Common Mode

CPM Current Program Mode

CPU Central Processing Unit

DAC Digital-to-Analog Converter

DC Direct Current

DCM Discontinuous Conduction Mode

DCR DC resistance

DM Differential Mode

EMI Electro-magnetic Interference

ESR Equivalent Series Resistance

FSM Finite State Machine

xix

IC Integrated Circuit

LCD Liquid Crystal Display

LUT Look-up Table

MAC Multiplier Accumulator

MSCB Multi-phase Switched-capacitor Buck

NSMB Non-Symmetric Multi-level Boost

PCB Printed Circuit Board

PI Proportional Integrator

PID Proportional Integral Derivative

PWM Pulse Width Modulation

SC Switched-Capacitor

SMPS Switch-Mode Power Supply

1

Chapter 1

Introduction

1.1 Motivation

In the past few decades, electronic devices have progressively become more prevalent in many

different application areas, as diverse as communication, healthcare, transportation,

entertainment and consumer electronics, making them an essential part of today’s modern life.

2

In almost all of these applications the electric energy source, the ac line from utility network or a

set of battery cells, supplies the device by providing a variable and/or unregulated voltage,

whereas the functional blocks of the device require well-regulated dc voltages at a different

levels.

Switched mode power supplies (SMPS) are widely used to serve the purpose of regulating the

voltage supplied by the electric energy source and delivering power to the electronic loads, i.e.

functional blocks. That is mainly due to their significantly higher power density, power

processing efficiency and their capability to cope with larger input voltage range compared to

other existing solutions such as analog linear regulators [1], [2].

Still, the volume miniaturization of switched mode power supplies has not kept up with the pace

of reduction in size of the electronic loads they supply. This is especially prominent in portable

applications and consumer electronic products such as cell phones, tablets, personal computers,

liquid crystal display (LCD) monitors and TV sets.

In fact, in modern electronic devices switched mode power supplies often occupy up to 25% of

the overall volume of the device. In these systems the reactive components of power supplies,

i.e. inductors and capacitors, take most of the volume and are among the largest contributors to

the overall device weight [3]. In order to visually demonstrate a typical scenario, the portion of

the PCB area occupied by the switched mode power supplies in a Google Nexus 7 tablet and a

Panasonic Plasma TV is compared to the overall area of their electronic circuits in Fig. 1.1.

Another important feature of SMPS converters that shall not be undermined while focusing on

volume reduction of a power supply is their power processing efficiency. In battery operated

3

a) b)

Figure 1.1. Comparison of overall area occupied by power supplies (shown in red boxes) to the

overall PCB area for, a) a battery operated Google Galaxy Nexus 7 Tablet [4]; b) an ac powered

Panasonic VIERA TX-P50VT30E plasma TV [5].

electronic devices, high power conversion efficiency is crucial in order to increase the often

insufficient battery life of the device, attributed to the limited energy storage capacity of their

batteries. Furthermore, the high converter efficiency translates into savings on energy costs,

which is an imperative factor in higher power applications. Moreover, operation of the converter

with reduced volume at same or lower efficiency is not practical, since it results in a higher heat

density, requiring addition of heat sinks, and reduced reliability of the device. Therefore, in a

feasible solution for converter miniaturization, the converter volume reduction has to be

accompanied by proportional increase of its power processing efficiency.

In most of these applications buck or boost converters, or their simple derivations such as

forward or flyback converters, are conventionally used, due to their controller simplicity.

However, as it will be shown in this thesis, these topologies are not the optimized solutions, from

the size and weight point of view, for many applications and often result in overdesign of the

power stage components and, hence, increased volume and cost.

4

In these converters, the size of reactive components is mainly determined by the difference

between input and output voltages and converter switching frequency; the higher conversion

ratios and lower switching frequencies result in larger size of passive elements.

Although reduction of converter volume can be accomplished through an increase in switching

frequency, it results in more switching losses and efficiency degradation. Hence, operation in

higher switching frequency does not provide a viable solution to converter volume reduction.

In many applications of switched mode power supplies (SMPS), there is a relatively large

voltage difference between the converter input and output voltages under some operating

conditions, which has a large impact on the overall volume. For example, this can be noticed in

battery operated dc-dc converters due to large variation of the battery voltage and low voltage

requirement of digital loads. Also, in laptop computers, the power supply has to provide voltage

step-down conversion ratios up to 19:1 [6]. Other examples are ac-dc converters, where a similar

situation exists due to input voltage swing during one line cycle, e.g. 0V to 374V, while

delivering constant output voltage of around 380V or higher. Those large input-to-output voltage

differences result in increased overall volume and cost of the conventionally used buck or boost

converters due to their more demanding filtering requirements [6]-[10]. The difference also

increases switching losses, due to switching higher voltages across semiconductor switches and,

therefore, limits the maximum operating frequency of the converter besides reducing the

converter efficiency.

The newly emerged digital controllers allow for control of switching actions for new and more

complex converter topologies than the traditional analog controlled solutions. Therefore they

provide opportunities for minimizing overall converter volume and losses. The prior work [6]-

5

[10] with regards to this approach suggest that a combination of high power density switched

capacitor circuits and inductive based converter topologies, such as buck or boost, is a suitable

candidate to fulfill the goal of reducing overall converter volume while improving the power

processing efficiency at the same time. Such topologies often utilize two stages consisting of a

switched capacitor converter and an inductive-based converter stage. Those 2-stage structures

result in a significant reduction of the overall volume but at the same time introduce a relatively

large number of extra switches in the conduction path. As a consequence, the conduction losses

of those topologies are often preventing their use in higher current applications. Moreover they

usually require addition of intermediate or flying capacitors that contribute to the overall volume.

1.2 Thesis Objectives

The main goal of this thesis is development of novel converter topologies based on merging

switched capacitor (SC) and inductive based converter stages and, thus, reducing voltage

difference across components of the inductive based converter stage. By merging SC and

inductive based stages, instead of a straight forward connection of two stages, the capacitor of

input/output filter existing in inductive based converter is utilized in the SC stage, eliminating

intermediate and/or flying capacitors. Moreover, the switches between the two stages are shared

and the inductor current can be utilized for charge balancing of the SC stage. Hence, the overall

volume and efficiency can be improved compared to other two stage solutions [7-12].

Two types of hybrid converter topologies are focus of this work that target volume/efficiency

improvements for the two commonly used topologies, namely, buck and boost converters in

applications with large input-output voltage difference.

6

The implementation of the introduced multi-phase dc-dc converter for battery operated point of

load applications is demonstrated. The functionality of the developed boost-based topology is

also verified through its realization as a power factor correction rectifier circuit, i.e. ac-dc

converter.

1.3 Thesis Organization and Contributions

In the first part of the work, a multiphase dc-dc converter based on merging a capacitive divider

stage and a buck converter, as shown in Fig. 1.2 is developed. This topology is suitable for

applications requiring high step-down dc-dc converters and allows for a reduction of the volume

of the step-down converters with a lower penalty in conduction losses compared to other 2-stage

solutions [6], [8], [11]. Compared to the single-stage merged buck converter with capacitive

Cout

L2

L1

Cin1

Cin2

e[n]d[n]

Cr

Lf Lp

G6

G8 G9

G7

Digital controller

ADC &

Transient

detector

PID

Active capacitive divider

DPWM

Minimum Deviation

logic

Switching control

logic

d1[n]

G1

G2 G3 G4 G5

vout(t)

2-phase interleaved buck

converterInput filter

Vin1

Vin2

+

+

_

_

R

+

_

Vbatt

vx2(t)

vx1(t)Q8

Q2Q3

Q5

Q4 Q6

Q7

Q9

Q1

c(t)

ss

lv

tror

tr


digital controller.

7

attenuator [7], the introduced converter provides a common ground between the input and output

voltages. Therefore, it allows for multi-phase operation, which in previous solutions was not

possible, and, as such, provides a suitable solution for medium to high power range applications.

Furthermore, the merged topology has a larger inductor current slew rate than a multiphase buck

converter resulting in a significantly faster transient response.

In the second part of the thesis a universal ac-dc power factor correction rectifier of Fig. 1.3 that

merges a boost power stage and a non-symmetric capacitive attenuator is presented.

This converter reduces the size of the boost inductor to a one third of the value required for the

conventional boost PFC and, for the rest of the power stage; its implementation requires the same

volume and silicon area of components as those of a conventional boost converter. The new PFC

topology also reduces switching losses of the converter through the entire operating range

without any considerable penalty in conduction losses.

Liin(t)

C

2C

+

vout(t)

_

Q1

Q2

D2

+

2Vbus/3

_

+

_

D1

Signal comparators and

mode selector

Dual-input isolated dc-dc

downstream converter

H

vx(t)

+

vin(t)

_Full-wave diode

rectifier

vline(t)

+

_ Vbus/3

H

Load

vct(t)

vtop(t)

cd(t)

Hdvout(t)

H Hd

Input current and buss voltage regulator

Downstream stage

controller

Averaged current programmed mode

controller

Centre-tap voltage

regulator

Pulse redirection

logic

Hvtop(t)

Hvct(t)

d[n]Hvin(t)

cd1(t) cd2(t)c1(t) c2(t)

NSMB Controller

Rsiin(t) Hvin(t) Hvct(t) Hvtop(t)

c1(t)

c2(t)

Figure 1.3. Block diagram of the non-symmetric multi-level buck (NSMB) based PFC rectifier

and its controller.

8

Compared to the three-level boost [9] the inductor reduction is achieved by providing non-equal

voltages across the capacitive divider cells and, in that way, effectively creating a structure that

produces 4-output voltage levels. Therefore, a 33% reduction in the inductor volume along with

improved efficiency is achieved compared to a three-level-boost while having the same

implementation cost. The capacitive divider voltages are regulated with a downstream converter

that, due to dual input operation, also has smaller volume than the conventional downstream

solutions.

To summarize, the main contributions of this thesis are:

• Development of a new multiphase converter topology and its accompanying digital

controller that merges a capacitive divider and a multiphase buck converter that minimizes

switching losses and volume of inductor and also output capacitor of the buck converter by

improving its transient response,

• Development of a four level boost-based PFC converter and its accompanying digital

controller that reduces the size of boost inductor and converter switching losses by utilizing a

non-symmetric capacitive divider instead of the output capacitor of the conventional boost PFC

1.4 Thesis Outline

The thesis is organized as follows:

Chapter 2 reviews the main challenges regarding miniaturization of the switched mode power

supplies summarizing the related previous work. Special attention is given to the prior art with

9

respect to the targeted applications, namely, battery operated point of load (PoL) converters

based on buck converter and ac-dc boost based converters.

Chapter 3 presents the first major contribution of this work which is the development of a multi-

phase dc-dc converter topology based on the multi-phase buck converter. The principle of the

operation for the converter, details of the design procedure and main implementation challenges

for the introduced converter are addressed followed by the results, experimentally verifying the

anticipated advantages.

Chapter 4 introduces a boost-based converter that operates based on the same principle, i.e.

replacing the output filter of boost with an active capacitive attenuator. The new topology is

reducing boost converter volume and losses and is the second major contribution of this thesis.

The converter design, operation and practical implementation challenges have been fully

analyzed for the case when it is employed as an ac-dc power factor correction (PFC) rectifier.

Moreover the unified digital controller that governs the operation of the ac-dc stage and the PFC

down-stream dc-dc converter is presented. This is followed by a set of experimental results from

the developed prototype converter.

Finally, this thesis is concluded in Chapter 5, summarizing the main contributions of the

presented work as well as exploring the directions for possible future research.

10

References

[1] J. illiams “High Efficiency Linear Regulators ” Linear Technology Application Note 32

March 1989.

[2] M.S. Makowski, and D. Maksimovic, "Performance limits of switched-capacitor DC-DC

converters," Power Electronics Specialists Conference, 1995. PESC '95 Record., 26th Annual

IEEE, vol.2, no., pp.1215-1221, 18-22 Jun 1995

[3] Y. Kaiwei, High-frequency and high-performance VRM design for the next generations of

processors, 2004, Virginia Polytechnic Institute and State University.

[4] J. Devincenzi, D. Hodson, M. Djuric, B. McCrigler, et. al. “Nexus 7 Teardown.” Internet:

https://www.ifixit.com/Teardown/Nexus+7+Teardown/9623, July 02, 2012 [June 11, 2014].

[5] “Panasonic VIERA TX-P50VT30E Teardown.” Internet: http://www.fullhd.gr/reviews/tv-

tear/item/7902-panasonic-viera-tx-p50vt30e-teardown.html, April, 21, 2011 [June 11, 2014].

[6] J. Sun; X. Ming, Y. Yucheng, F.C. Lee, "High Power Density, High Efficiency System Two-

stage Power Architecture for Laptop Computers," Power Electronics Specialists Conference,

2006. PESC '06. 37th IEEE , vol., no., pp.1-7, 18-22 June 2006

[7] A. Radić, A. Prodić, "Buck Converter With Merged Active Charge-Controlled Capacitive

Attenuation," IEEE Trans. on Power Electron., vol.27, no.3, pp.1049-1054, March 2012

[8] R.C.N. Pilawa-Podgurski, D.M. Giuliano, D.J. Perreault, “Merged two-stage power converter

architecture with soft charging switched-capacitor energy transfer,” in Proc. IEEE Power

Electronics Specialist Conf., 2008, pp. 4008-4015, June 2008.

[9] T.A. Meynard, H. Foch, "Multi-level conversion: high voltage choppers and voltage-source

inverters," in Proc. IEEE PESC '92, pp.397-403 vol.1.

[10] M.T. Zhang, Y. Jiang, F.C. Lee, M.M Jovanovic, "Single-phase three-level boost power

factor correction converter ," in Proc. IEEE APEC '95, pp.434-439 vol.1.

[11] J. Sun, M. Xu, and F. C. Lee, “Transient Analysis of the Novel Voltage Divider,” in Proc.

IEEE Applied Power Electronics Conf., 2007, pp. 550–556. Feb. 2007.

[12] F. Forest, T.A. Meynard, S. Faucher, F. Richardeau, J.J. Huselstein, C. Joubert, "Using the

multilevel imbricated cells topologies in the design of low-power power-factor-corrector

converters," IEEE Trans. on Industrial Electronics, vol.52, no.1, pp. 151- 161, Feb. 2005.

11

Chapter 2

Background and Previous Art

This chapter presents an overview of the relevant previous work. At first limiting factors of most

commonly used, single stage converter topologies, especially in applications of interest with

large input-output voltage difference, are briefly addressed. Previously developed techniques

utilized for improvement of such converters and their shortcomings are discussed next. The prior

art involving reduction of input-to-output voltage ratio using straight-forward, serial connection

12

of switched capacitor and inductive based solutions is covered in fourth subsection. This is

followed by an overview of the concept of merging the two converter stages and the advantages

of previous solutions using the same concept. The shortcomings of the existing merged solutions

in high conversion ratio applications and those requiring higher power ratings are also discussed,

exposing the areas for further improvements of such converter topologies, which is the main

focus of this dissertation.

2.1 Topology Limits

Traditionally, inductive-based buck converters (Fig. 2.1.a), have been the default switched mode

power converters in voltage step-down DC-DC applications, where they are used in a wide range

of applications requiring moderate to high power levels (>100mwatt) [1]. Boost converter (Fig.

2.1.b), being similar to a buck converter with flipped input/output ports, has a similar dominance

in SMPS applications where an input voltage step-up is desired. These converters provide simple

and relatively cost-effective solutions since they are implemented with a low number of

components and, a relatively simple controller governs their switching actions and regulates the

output voltage. Nevertheless, their relative simple implementation comes with a number of

disadvantageous. Their switches have to be rated for maximum voltage in the circuit, Vin for

L

SW1

D1

Cout

load

+vout(t)

_

0

Vout

iin(t)=iL(t)

Vin

+

_

iin(t) iL(t)

Vin

L

Cout Vout

0

Vin

+

_

load

SW1

SW2

a) b)

Figure 2.1. Most common non-isolated inductive-based converter topologies. a. buck converter.

b. boost converter

13

buck and Vout for boost, their inductors are connected to the converter low voltage side, Vout for

buck and Vin for boost, meaning their inductors have to be rated for the highest of the input or

output converter current, increasing their volume. In addition, since the switches have to

interrupt the inductor current and block the higher of input or output voltage, their switching

losses are relatively high which reduces their efficiency.

A more detailed analysis of such shortcomings of these two most commonly used inductive

based converters, i.e. buck and boost, is presented in the following subsection. As will be shown,

the negative effects of such drawbacks become more severe as the input-to-output voltage

difference grows higher, creating a need for the development of new topologies to minimize

these problems.

2.2 Reactive Components Volume

Reactive components are among the biggest contributors to the weight and volume of the

inductive-based converters [1], [2]. This section reviews the main factors that determine the size

of these components, i.e. energy transfer inductor and output capacitor.

2.2.1 Inductor Volume

In inductive-based converters, the inductor serves the purpose of cycle-to-cycle energy transfer

from the input source to the load connected on the converter output side, where both the input

and the output side behave either capacitive or voltage source like behavior. Storing of this

transferred energy, i.e. differential energy, in each switching cycle over the inductor results in an

inevitably existing ac current ripple superimposed on the dc inductor current. This energy can be

found from

14

LLLLLLLL iLIiILiILiILE 2)4()()(212

212

21 , (2.1)

where ∆E is the transferred energy from input to output in one switching cycle, L is the

inductance value, IL is the average inductor current and ∆iL is the inductor current ripple. Large

inductor current ripples result is increased losses over converter switches and inductor itself and

may lead to magnetic core saturation. In inductive-based converters the inductor size is

determined based on maximum desired inductor current ripple value [2]. As shown in [2], for

buck and boost converters, the amplitude of this current ripple, ∆iL, can be found by equations

2.2 and 2.3 respectively.

swin

outoutbuckL

fV

V

L

Vi

1)1(

2, . (2.2)

swout

ininboostL

fV

V

L

Vi

1)1(

2, . (2.3)

As seen from equations 2.2 and 2.3, close input-to-output voltage difference requiring small

conversion ratios can significantly reduce inductor volume.

2.2.2 Output Capacitor Volume

In dc-dc applications, the output capacitor is mainly chosen to meet requirements for output

voltage variations during load transients. This is due to the fact that output capacitor charge

taken/delivered during large load-steps is much larger than that of causing ac output voltage

ripple at the switching frequency [3]. As discussed later in this chapter, the size of output

capacitor is mainly dependent on controller performance during load transients.

15

In ac-dc applications, the size of output capacitor is determined by the desired ac output voltage

ripple at twice line frequency (∆Vout) [2], which mainly depends on input voltage frequency

(fline), load power, and output voltage and it is not dependent on the converter topology. The size

of the output capacitor in such applications can be found as [2]

outlineout

load

outout

acin

outVV

P

VC

EC

2

_. (2.4)

2.3 Converter Losses

The primary sources of converter losses are conduction and switching losses. Conduction losses

are mainly caused by the on resistances of the switches Ron, diode forward voltage drop (Vfd) and

resistive losses of other components in current conduction paths such as inductors. The fact that

buck and boost converter have a minimum number of components in conduction path, one

semiconductor device and inductor at any moment, enables them to achieve a rather good

performance in terms of minimizing conduction losses. However, this mainly depends on Ron of

switches and Vfd of diodes. Since the figure of merits of semiconductor devices, are inversely

proportional to their blocking voltages (Vds) [4], operation under higher switching voltages

negatively affects conduction losses of buck and boost converters. This is mainly due to

increases of switch on-resistances and diode forward voltage drops for a given silicon area.

Conventional hard-switched buck and boost force switches to commutate under concurrent

presence of non-zero current and voltage across them causing switching losses. Largest portion

of switching losses of these converters is created during the switch commutation period. The

switching losses of a hard switched transistor can be found by [2]

16

swxossswoffonLxsw fVcfttiVP 2

2

1)(

2

1 , (2.5)

where the first term corresponds to the commutation losses [2] and the second term represents

losses due to switch parasitic capacitances. In this equation, Vx is the voltage swing at converter

switching node which is equal to Vin and Vout for buck and boost converters, respectively; ton and

toff are commutation times during turn on and turn off transient of switches and Coss represents

output capacitance of the switch. As shown by this equation, switching losses are proportional to

the switching voltage and switching frequency. Therefore, in applications with large input or

output voltages, buck and boost converters will have relatively large switching losses, both due

to increased switching voltage and also increased parasitic capacitance of switches as they have

to be rated for higher voltages [4].

The discussion in this section indicates that the utilization of a buck or boost converter in

applications with large conversion ratios results in a large inductor volume and at the same time

negatively affects conduction and switching losses reducing system efficiency.

2.4 Volume reduction techniques

This Section reviews the existing methods for volume reduction of inductive-based converter

topologies. In each case the advantageous and drawbacks are briefly addressed.

2.4.1 Increasing Switching Frequency

Traditionally, increase of switching frequency of the converters has been the most commonly

method used for reducing the volume of converters. Increasing switching frequency reduces the

inductor volume by proportionally reducing its current ripple, (as shown in Eq. 2.1 and 2.2).

17

Moreover, switching at higher frequencies allows for higher controller bandwidth [2] that can

improve transient response of the converter, minimizing its output capacitor size in dc-dc. On the

other hand, this raises the frequency-dependent losses, such as magnetic core losses and

switching losses, as predicted by Eq. 2.5, reducing converter efficiency especially at light load

operating conditions. This efficiency degeneration and increased heat density associated with it

are the main factors limiting the switching frequency of high step down converters.

2.4.1.1 Soft switching techniques

Soft switching methods have been developed to reduce switching losses of hard switched

converters [33-36]. Therefore, they potentially allow for converter operation with higher

switching frequencies and volume reduction of reactive components while maintaining high

power processing efficiency. In general these methods implement zero current switching (ZCS)

or zero voltage switching (ZVS) for semiconductor devices by addition of a controlled resonant

circuit. In these methods a soft switching is achieved by creating a resonant current/voltage

through/across the converter switches and commutating switches when that current/voltage is

zero. This allows for operation at higher frequencies with smaller penalties in terms of switching

losses and, therefore, allows for implementation of converters with higher power densities. These

advantages come with the cost of extra circuitries and additional conduction losses introduced by

the resonance current, affecting light load converter efficiency [36-37]. However the adoption of

soft switching converters in some medium to high power applications this tradeoff has proved to

be favorable.

18

2.4.2 Interleaving techniques

Increase of effective switching frequency can also be achieved through the utilization of

interleaved multi-phase topologies where a number of converter switching cells are connected in

parallel and their internal switching instants are sequentially time shifted over equal fractions of

a switching period [5-9]. Interleaved topologies reduce the input and output current/voltage

ripple of the converters, allowing for reduction of the input and output filter size and achieving

improvements in terms of the output capacitor in dc-dc applications by facilitating transient

recovery [10] with lower penalties in terms of switching losses. Moreover, interleaved converters

have proven to be effective solutions for larger power ratings, where the semiconductor

switching components can be fully utilized. However, these solutions still suffer from relatively

high switching losses, since they switch full range of input/output voltages and, when operating

at light and medium loads, from either degradation of efficiency or quality of the input current

waveform [11]. Furthermore, interleaving does not reduce inductor current ripple in each

switching cell, thus their magnetic core losses and inductor copper losses are the limiting factor

for inductor volume reduction and the reduction of inductor volume is not proportional to the

rate of increase in effective switching frequency [12].

2.4.3 Non-linear Controllers

In dc-dc applications of switched mode power supplies, dynamic behavior of the converter is the

main factor determining the output capacitor volume. A converter with poor transient response

requires overdesigned power stage components to avoid failure during large transients. Linear

controllers being designed through state-space averaging modeling are fairly simple to

19

implement but inherently have bandwidths limited to an order of magnitude lower than converter

switching frequency. Recently emerged nonlinear controllers, utilizing digital control techniques

[13-23] have proven to be capable of achieving significant improvements in dynamic behavior of

the converter, only restricted by physical limitations of power stage reactive components, such as

inductor current slew rates, which is determined by converter topology.

2.4.4 Ripple Cancellation

In numerous applications of the ac-dc rectifiers with power factor correction, i.e. PFC rectifiers,

minimization of the output voltage ripple at the twice line frequency is needed. This is done

through increasing the size of converter output capacitor as shown in Eq. 2.4. To minimize the

output ripple at twice the line frequency without paying a large price in the system size and

reliability, a number of solutions have been proposed [24-32]. Arguably, among the most

effective are ripple cancellation based systems [24], [27]-[32]. There, a small auxiliary converter

stage, i.e. ripple cancellation circuit, is used to minimize the ripple. The auxiliary converter

improves the voltage regulation by transferring the component at twice the line frequency from

the output capacitor of the PFC stage, Cout , to its own capacitor, Caux.

2.5 Switched Capacitor Converters

Switched capacitor (SC) converters [38]-[40] realize dc-dc conversion utilizing circuits

consisting of a network of switches and capacitors only, Fig. 2.2. These converters operate by

capacitive energy transfer from input source to the load as opposed to inductive energy transfer

being used in inductive-based converters. This is done through utilization of a number of

switching cells, operating in cyclical phases. In each cycle, a small amount of charge is delivered

to the load depending on the load current and the switching frequency. Elimination of magnetic

20

C3

C4

Cout

C2

iin(t)

Vin

+

_

Φ1 Φ1 Φ1Φ2 Φ2Φ2

SW1 SW6SW5SW4SW3SW2

load

Figure 2.2. A 3-to-1 ratio down-step ladder network switched capacitor converter, Φi represents

phase of operation of switches.

component results in significant gains in converter power density and allows for realization of

fully integrated converters in low power applications.

As shown in [41-42] SC converters can achieve high power density and high efficiency in lower

power applications (up to few watts). Though, SC converters can achieve high efficiency only

when operating at conversion ratios close to their ideal (rational) ratio for the given topology and

operating mode. Operation at wide input voltage range can significantly degrade their efficiency

[43]-[46].

SC converters also introduce additional switching losses due to the capacitive energy transfer.

This is due to the fact that by connecting two capacitors with different voltage levels, an amount

of charge of ∆q is transferred from the capacitor with higher voltage, v1, to the one with a lower,

v2. This reduces the overall electric potential energy of the system of two capacitors by an

amount of ∆q.(v1-v2). This energy is dissipated as heat over the switch resistance and capacitor

equivalent series resistance (ESR) and/or radiated in the air. This loss can be modeled as a

virtual resistance R, controlling the current flow in a switched capacitor circuit [47] as shown in

21

Cout

iin(t)

V1

+

_

loadV2

+

_

R=1/C1fsw

Cout

iin(t)

V1

+

_C1

load

fsw

V2

+

_

a) b)

Figure 2.3. Capacitive energy transfer modeling with a virtual resistor [47]

Fig. 2.3. In an ideal case with negligible or no switch resistance and capacitor ESR, this energy

will be radiated at a very high frequency, contributing to circuit electromagnetic interference,

EMI.

Another drawback of SC converters compared to their inductive-based counterparts is their

pulsating input and output current waveform, which introduces the electromagnetic interference

by conducted emissions. This also results in SC switches to be overrated to cope with high input

current peaks due the short charging period [48]. This problem can be minimized by addition of

a big input capacitor which in turn increases the converter volume significantly [48].

In an optimal design of an SC converter, the switches can be rated for fractions of input voltage

based on the blocking voltage requirement for their steady state operation, i.e. they can be rated

for Vin/3 in example of Fig. 2.3. However, during the start-up transient of the converter when

capacitors are not charged, the switches are exposed to the full input voltage. Therefore in the

practical implementation the benefits associated with lower voltage rated switches cannot be

fully utilized and switches are rated for full range of input voltage. In some cases this issue can

be addressed by addition of extra circuitry [49].

22

2.6 Two-Stage Converter topologies

Among the applications of switched mode power supplies requiring large dc-dc input-to-output

voltage ratios, portable devices are of paramount significance due to their very large market

share. Some examples of such devices include tablets, laptops and gaming consuls, where the

input battery voltage has to be converted from 7-19V to 1V or below, to supply processing units

[50-51].

Utilization of high power density SC converters is not a viable solution in these applications due

to the wide range of input voltage and requirement of tight output voltage regulation during load

transients. Therefore, most of the converters used for these applications are single-stage multi-

phase buck topologies [52].

It has been shown by [53-54] that utilization of two-stage topologies in these applications can

result in a reduction of the overall converter cost and volume. In these solutions, a first stage

single-phase buck converter reduces the level of input voltage. A second stage multi-phase buck

converter connects serially after the first stage, regulating the output voltage as shown in Fig. 2.4

In such topologies the volume and cost reduction is still limited due to having an inductive first

stage that runs at 200-300 kHz [51].

Substituting the first stage of such two stage topologies with an SC converter has proven to result

in further volume reduction and efficiency improvements [46], [51] shown in Fig. 2.5. In this

case, the SC stage can operate with a constant conversion ratio, achieving optimal volume and

efficiency.

23

These 2-stage structures result in a significant reduction of the overall volume but at the same

time introduce a relatively large number of extra switches in the conduction path. As a

consequence, the conduction losses of those topologies are often preventing their use in higher

current applications. In addition, the cascaded topologies also use separate controllers for each of

the two stages increasing hardware complexity.

Input Filter

Cin

Lf

Vbatt

Cout

Vout

R

L1Q1

Q2

0

Vbatt/n

n

Vbatt

Multi-phase buck converter

stageBuck voltage attenuation

stage

LnQ1

Q2

LQ1

Q2

0

Vbatt

Figure 2.4. SMPS volume reduction using two inductive converter stages

Input Filter

Cin

Lf

Vbatt

Cout

Vout

R

L1Q1

Q2

0

Vbatt/n

n

Vbatt

Multi-phase buck converter stageSwitched capacitor Stage

LnQ1

Q2

Figure 2.5. SMPS volume reduction using two-stage approach utilizing a SC voltage attenuator

24

2.7 Topologies Merging Inductive-based Solutions and Capacitive

Attenuator

The benefits of the 2-stage converters are achieved through reduction of input-to-output voltage

difference for the inductive based converter by utilizing a first voltage attenuation stage. A

recent publication [55] shows that same functionality can be achieved by merging a capacitive

divider and a downstream buck converter as shown in Fig. 2.6. There, the switches of both stages

are shared to minimize conduction losses and the buck inductor is used for the SC stage capacitor

charge balancing, eliminating a bulky intermediate capacitor existing in other SC-based solutions

[46], [51]. The charge control of the input capacitors through buck inductor also eliminates the

extra switching losses of switched capacitor converters, due to pulse current transfer between

capacitors during capacitive charging process, forming a virtual resistance [9]. This modification

also reduces the number of switches in the conduction path, i.e. conduction losses, and simplifies

control, allowing regulation of both stages with a single controller. Still, realization of a multi-

phase solution utilizing this topology is not feasible since it does not provide a common ground

between input and output voltages.

Input Filter

Lf

Vbatt

Cout

Vout

R

L

0

Vbatt/2Cin1

Cin2

2

battV

2

battV

Q1

Q2

Q3

Q4

Figure 2.6. Single-phase buck converter with merged capacitive attenuator [55].

25

In case of the boost converter, a similar approach of merged inductive based converter and

output capacitive attenuator can be used to minimize both the inductor size and the switching

losses, by reducing the stress of the components. Multi-level converters [56-62] that have been

originally developed for use in high voltage applications, such as dc-ac inverters and ac-dc

rectifiers operate based on the same principle.

In the flying capacitor multi-cell boost [58], shown in Fig. 2.7, derived from the multilevel

concepts [63], these advantages are achieved by adding few switches and a relatively large flying

capacitor.

A three-level boost-based PFC [57], shown in Fig. 2.8 replaces the output capacitor of the boost

converter with a compact active capacitive divider and, for the same switching frequency, results

in a 50% reduction of the inductor value compared to the conventional boost converter.

L

SW1

Vin

SW3

SW2

D3 D2 D1

+

vout(t)

_

+2vout(t)/3

_

vout(t)/3+_

Cout

C2

C1+

_

Figure 2.7. A four-level boost-derived flying capacitor multi-level converter [58].

26

L

SW1

SW2

D1

D2

C1

C2

+

vout(t)

_

+

vout(t)/2_

+

vout(t)/2_

Vin

+

_

Figure 2.8. The three-level boot converter [57].

The converter topologies introduced in this thesis operate based on similar principle as the

presented merged topologies, further improving their performance and reduce their volume.

Hence the concepts discussed in this section will be revisited in Chapter 3 and 4 of this

dissertation and some of them will be used to derive the new topologies.

2.8 References

[1] M.D. Seeman, V.W. Ng, L. Hanh-Phuc, M. John, E. Alon, S.R. Sanders, "A comparative

analysis of Switched-Capacitor and inductor-based DC-DC conversion technologies," In Proc.

IEEE COMPEL 2010, pp.1-7, June 2010

[2] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. New York, NY:

Springer Media Inc., 2001.

[3] S.M. Ahsanuzzaman, A. Parayandeh, A. Prodić, D. Maksimovic, "Load-interactive steered-

inductor dc-dc converter with minimized output filter capacitance," In Proc. IEEE APEC 2010,

pp.980-985, Feb. 2010.

[4] B.J. Baliga, “Fundamentals of Power Semiconductor Devices,” NewYork, NY: Springer,

2008.

27

[5] B. Miwa, “Interleaved Conversion Techniques for High Density Power Supplies,” PhD

Thesis, Massachusetts Institute of Technology, Department of Electrical Engineering and

Computer Science, 1992.

[6] B. A. Miwa, D. M. Otten, and M. F. Schlecht, “High efficiency power factor correction using

interleaving techniques,” in Proc. IEEE Appl.Power Electron. Conf., 1992, pp. 557–568.

[7] C. Chang, M.A. Knights, "Interleaving technique in distributed power conversion systems,"

IEEE Trans on Circuits and Systems I: Fundamental Theory and Applications, vol.42, no.5,

pp.245-251, May 1995

[8] L. Balogh, R. Redl, "Power-factor correction with interleaved boost converters in continuous-

inductor-current mode," in Proc. IEEE APEC '93. pp.168-174.

[9] P.W. Lee, Y.S. Lee, D.K.W. Cheng, and X.C. Liu, “Steady-State Analysis of an Interleaved

Boost Converter with Coupled Inductors,” IEEE Trans. on Industrial Electronics., vol. 47, no. 4,

pp.787-795, Aug. 2000.

[10] X. Zhou; P. Wong; P. Xu; F.C. Lee, A.Q. Huang, "Investigation of candidate VRM

topologies for future microprocessors," IEEE Tran. on Power Electron., vol.15, no.6, pp.1172-

1182, Nov 2000

[11] C. Wang, “Investigation on Interleaved Boost Converters and Applications,” PhD thesis,

Virginia Polytechnic Institute and State University, July 2009.

[12] M. O’Loughlin, “An Interleaving PFC Pre-Regulator for High-Power Converters,” Texas

Instruments Seminar, http://www.ti.com/download/trng/docs/seminar/Topic5MO.pdf

[13] K. Ka-Sing Leung, H. Shu-Hung Chung, “Dynamic hysteresis band control of the buck

converter with fast transient response,” IEEE Trans. on Circuits Syst. II, vol. 52, pp. 398–402,

July 2005.

[14] A. Soto, P. Alou, and J.A. Cobos, “Nonlinear digital control breaks bandwidth limitations,”

in Proc. IEEE Applied Power Electronics Conf., 2006, pp. 724–730.

[15] Santa C. Huerta, P. Alou, J. A. Olivier, O. Garcia, J. A. Cobos, and A.Abou-Alfotouh, “A

very fast control based on hysteresis of the cout current with a frequency loop to operate at

constant frequency,” in Proc. IEEE Applied Power Electronics Conf., 2009, pp. 799–805.

[16] G. Feng, E. Meyer, and Y.-F. Liu, “A new digital control algorithm to achieve optimal

dynamic performance in DC-to-DC converters,” IEEE Trans. Power Electron., vol. 22, pp.

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32

Chapter 3

Digitally Controlled Multi-Phase Buck-Converter with

Merged Capacitive Attenuator

The focus of this chapter is design and implementation of a new topology that merges a three

level switched-capacitor front end converter with a two-phase buck converter for dc-dc point of

load applications. The introduced converter combines a capacitive divider and an interleaved

buck to reduce the volume of step-down converters with a lower penalty in conduction losses,

input filter size, and controller complexity than other 2-stage solutions reviewed in Chapter 2. At

33

heavy loads, the converter efficiency is comparable to the conventional buck and at light to

medium loads it is improved. The improvements are obtained by utilizing the inductors of the

buck stage to regulate the tap voltages of the capacitive divider. This eliminates the energy

transfer capacitor existing in other switch capacitor (SC) circuits, reduces the number of switches

in the conduction path, and simplifies control of the converter.

3.1 Introduction

In portable devices, such as tablet computers and gaming consoles among the main targets are

volume reduction of dc-dc converters [1], [2] and improvements in their efficiency. In these

systems the reactive components of the power supplies often occupy more than 25% of the

overall volume and are among the largest contributors to the overall device weight [3]. Those

supplies are usually required to step down the voltage of a single or two serially connected

battery cells to a 1V or even lower voltage [4], for digital loads. Due to the quickly changing

nature of the load, which often depends on the software application, the supplies are also

required to have a high efficiency over the full range of operation and fast dynamic response.

As described in Chapter 2, existing 2-stage solutions [5]-[7] achieve lower switching losses and

volume in the applications of interest. However they have not been widely adopted in higher

power applications even in multi-phase configuration. This is due to the fact that these topologies

increase conduction losses which are the dominant source of losses in higher power levels

compared to buck converter because of increased number of switches in conduction path. The

single-phase merged SC-buck converter of [8] reduces the conduction losses of two-stage

34

topologies while achieving similar benefits. However, since this converter can only be realized in

single phase configuration, it does not provide a viable solution for higher power applications.

The main goal of this Chapter is to introduce a new merged switch-capacitor multi-phase buck

converter (MSCB) topology shown in Fig. 3.1 that further reduces the volume of the step-down

converters with a lower penalty in conduction losses compared to other 2-stage solutions [5]-[7].

At heavy loads, the proposed structure has approximately the same efficiency as the conventional

interleaved buck and at light to medium loads the efficiency is improved. Furthermore, the

Cout

L2

L1

Cin1

Cin2

e[n]d[n]

Cr

Lf Lp

G6

G8 G9

G7

Digital controller

ADC &

Transient

detector

PID

Active capacitive divider

DPWM

Minimum Deviation

logic

Switching control

logic

d1[n]

G1

G2 G3 G4 G5

vout(t)

2-phase interleaved buck

converterInput filter

Vin1

Vin2

+

+

_

_

R

+

_

Vbatt

vx2(t)

vx1(t)Q8

Q2Q3

Q5

Q4 Q6

Q7

Q9

Q1

c(t)

ss

lv

tror

tr


digital controller.

35

merged topology has a larger inductor current slew rate resulting in a faster transient response.

This converter operates on the same principle as the single-phase topology consisting of a

capacitive divider and a downstream buck converter introduced in [8]. Hence reduction of

switching losses and inductor volume is achieved as in two stage topologies while the conduction

losses are minimized. That is done by sharing the switches of both stages to minimize conduction

losses and using the buck inductor for the input capacitive divider voltage balancing, eliminating

a bulky intermediate capacitor existing in other SC-based solutions [5]-[7]. The soft charging of

input capacitors in MSCB converter and their discharge through buck inductors also eliminates

the extra switching losses of switched capacitor converters due to pulsed current waveforms with

high pick currents and capacitive energy transfer between capacitors during capacitive charging

process, forming a virtual resistance [9]. This modification also reduces the number of switches

in the conduction path, i.e. conduction losses, and simplifies control, allowing regulation of both

stages with a single controller. An extension of the single-phase system introduced in [8] to a

multiphase operation is not a straightforward task. Mostly, due to a strong interaction between

the upstream and the downstream stage as well as due to the phase interactions. Hence, a simple

parallel connection of the buck stages for the topology shown in [8] cannot be done. The multi-

phase topology of Fig. 3.1 shows a solution for those problems allowing for a significant

extension of the power rating.

3.2 Principle of Operation and System Description

The converter introduced here operates on the same principle as the other 2-stage solutions [5]-

[8]. Namely, the input voltage of the downstream buck converter Vbatt is reduced with a front-

stage switch-capacitor converter. The effect of the input voltage reduction can be quantitatively

36

described through the expression for the inductor current ripple of a buck converter as previously

discussed in Chapter 2. [10]

swin

outoutripple

fV

V

L

VI

1)1(

2

where Vout is the output voltage, L is the inductance value, and fsw is the converter switching

frequency. It can be seen that a decrease of the Vout/Vin ratio allows for reduction of the L without

paying a penalty in the inductor and output capacitor ripple values. In addition to allowing for

filter minimization, the input voltage reduction also minimizes switching losses of the buck

stage, which are proportional to the power transistor switching voltages [10].

In the system of Fig. 3.1, the reduction of the input voltage for the downstream buck converter is

achieved by modifying the input filter and replacing its capacitor with an active capacitive

divider of an approximately same size. The capacitive divider provides two input voltages for the

buck stage vin1(t) and vin2(t), which values are approximately equal to a half of the input battery

voltage Vbatt. Since the volume of a capacitor depends on its energy storage capacity [11], i.e.

We=½CV2, the total volume of the divider capacitors is no larger than that of the conventional

input filter capacitor, even though their individual capacitances are larger. Operation of the

converter is controlled with a single voltage mode digital pulse-width modulation controller

where, as will be described in this section, the regulation of the attenuator tap voltages vin1(t) and

vin2(t) is provided through an inherent feedback loop existing in this topology. For small values

of error signal e[n] the converter operates in steady-state mode. The output voltage is regulated

with a PID regulator, digital pulse width modulator (DPWM) [12], [13], and a switch selector

that sets the transistor switching sequence as described below.

37

3.2.1 Steady-state operation and elimination of the output capacitor of the SC

stage

The operating modes of the attenuator, i.e. SC stage, and the key converter waveforms are shown

in Figs.2 and 3. The converter operates such that the upper buck phase of Fig. 3.1 (controlled by

Q8 and Q9) is always supplied by the voltage across Cin1, i.e. vin1(t), and the lower buck phases

(controlled by Q6 and Q7) by vin2(t). The SC stage operates in synchronization with the buck and,

in each switching cycle, it goes through two modes, shown in Fig. 3.2.

Vbatt

Cin1

Cin2 Q7

Q6

Cr

Lf Lp

G6

G7

Q1

Q2

Q3Q4

Q5

iin(t)

vCr(t)

vC1(t)

vC2(t)

Mode B

iL1(t)

iL2(t)

ip1(t)

ip2(t)

L1

L2

Q8

G8 Q9

G9

Cin1

Cin2 Q7

Q6

Cr

Lf Lp

G6

G7

Q1

Q2

Q3 Q4

Q5

iin(t)

vCr(t)

vC1(t)

vC2(t)

Mode A

Q8

Q9

icharge(t)

iL1(t)

iL2(t)

ip1(t)

ip2(t)

Vbatt

L1

L2

a)

b)

Figure 3.2. Operating modes of the capacitive attenuator; top: mode A; bottom: mode B.

38

In mode A it charges the cascade connection of Cin1 and Cin2, through a quasi resonant circuit

formed of a small capacitor Cr, a parasitic PCB inductor Lp, and switches Q1 and Q3. In this mode

transistors Q2, Q5 and Q8 are open and the upper phase of the buck converter operates in

synchronous rectification mode, i.e. the transistor Q9 is turned on. During this time the lower

buck phase can be in any of the two regular switching states. As described later, the quasi-

resonant switch is used to obtain zero current switching eliminating switching losses of switches

Q1 and Q3.

In mode B the switch control logic changes the circuit configuration such that Cin1 is only

connected to the upper phase and Cin2 to the lower one. During this mode the buck phases can be

in either of the two switching states and discharge the capacitors during the times when their

G8G9

Mode AMode B

vC2(t)

vC1(t)

vCr(t)

iCharge(t)

Vg

Vg /2

Vg /2

iin(t)

0 DTs Ts/2 Tch Ts t

G1G2G3

G7G6

Figure 3.3. Key waveforms of the MSCB converter.

39

main switches (Q6 and Q8) are on, through the inductors of the downstream stages.

3.2.1.1 Inherent centre tap voltage regulation

The previously described operation inherently provides regulation of the SC tap voltages,

eliminating the need for a relatively large charge-balancing output capacitor existing in the front

stage of other SC based 2-stage solutions [5]-[7].

The voltage regulation as well as the current sharing between the phases can be described

through an analysis of the dc equivalent circuit of the converter shown in Fig. 3.4. In this case

the source Icharge represents the average current provided to the divider over one switching cycle,

i.e. during mode A (Fig. 3.2). The equivalent resistances of the phases modeling the losses are

Req1 and Req2. To simplify explanation it is assumed that both phases operate with the same

effective duty ratio D.

Capacitor charge balance equations [10] for the input capacitors result in

echLL IDIDI arg21

where IL1 and IL2 are dc values of the phase inductor currents. By using (3.2) and solving the

circuit of Fig. 3.3, the following expression for the difference in the tap capacitor voltages can be

obtained:

DIRRVV Leqeqcc /2/12121

These equations show that the current sharing is achieved and that for the targeted applications

where Req1-Req2 is relatively small, the tap voltages in steady state remain approximately the

40

Cout

Vout

RReq1DVC1

IL1

Cin1

DIL1Icharge VC1

Req2DVC2

IL2

Cin2

DIL2Icharge VC2

Figure 3.4. Approximate dc equivalent circuit of the converter.

same. The equations also show that the current and voltage sharing is not affected by the

mismatches in the inductor and capacitor values. In fact in the MSCB converter, similar to a

buck converter, the dc operating point of the circuit, i.e. capacitor voltages and inductor currents,

does not depend on the value of circuit components. For the reason, any mismatch between

values of Cin1 and Cin2 or between L1 and L2 will be only reflected in their ac voltage ripple and

current ripples respectively, not affecting the large signal converter operation.

Taking duty ratio mismatches into account, (3.2) and (3.3) will be transformed into (3.4) and

(3.5).

echLeqLeq IIDID arg2211

).(..2

2

1

1

arg2211

eq

eq

eq

eq

eChceqceqD

R

D

RIVDVD

where Deq1 and Deq2 represent effective duty ratios of upper and lower buck phases respectively.

As shown by (3.4), the inductor currents will only be affected by the mismatch in the duty ratios

proportionally. However, the tap voltage will differ from its ideal value (Vbatt/2) due to

41

mismatches in both duty ratio and equivalent resistance of buck phases as shown in (3.5). For

small mismatches this variation in tap voltage can be approximated as

eq

eq

eCh

eq

eq

eCheqbatt

eq

c RD

ID

D

IRV

DV

2

arg

2

arg)

2(

1

where ΔDeq and ΔReq represent discrepancies in the duty ratio and equivalent resistance of one

buck phase from values of Deq and Req in an ideally symmetrical two phase system.

The elimination of the energy storage capacitor also brings another main benefit of this circuit.

Since the extra switches needed for the control of energy storage capacitor are eliminated, the

conduction losses are reduced. This converter has just a minor increase in conduction losses

compared to the conventional buck. When Q7 and/or Q9 are turned on, the downstream stage has

the same conduction losses as the conventional buck and, as described in the following section,

only one low resistance switch is added during the other portion of the switching interval. Also,

since the switches Q1 and Q3 conduct relatively small current, its conduction losses are small.

3.2.1.2 Soft-switching

The SC converters often suffer from excessive switching losses due to direct energy transfer

between the capacitors [7], [9]. To eliminate this problem, a resonant switch formed by a

parasitic inductance of the pcb, Lp, and a small capacitor Cr in series with Cin1 and Cin2 (Fig.

3.2b), and transistors Q1 and Q3 are used. The resonant circuit parameters are chosen such that

the charging of Cin1 and Cin2 is completed over the duration of mode A, as shown in Fig. 3.3. This

period can be expressed as

rpchs CLTT

42

and should not exceed the conduction time of the synchronous rectifier, Q9, to maintain the low

voltage at the input of the upper buck phase. Therefore the converter duty cycle in steady sate is

limited to 1-Tch/Ts, determined by selection of Cr and also the PCB layout determining Lp. In the

targeted applications with large input-to-output voltage difference required duty cycle will not

exceed 40%, leaving a wide range of choice for Cr given the value of Lp, Therefore, Cr has to be

selected such that it satisfies energy storage requirements for one cycle of converter operation

with desired voltage ripple, while .

3.2.2 Transient and low-input mode

Sudden load changes are captured by the transient detector of Fig. 3.1. It triggers the minimum

deviation block that implements a minimum deviation control algorithm [14]. The operation of

this block for heavy-to-light load transients is similar to the minimum deviation control

algorithm for conventional buck converter. However due to utilization of smaller buck phase

inductors by the MSCB converter, it has improved heavy-to-light load transient response.

However during light-to-heavy load transients, utilization of Vbatt/2 by MSCB buck phases would

reduce the inductor current slew rate and hence result in inferior transient response compared to

the buck converter, increasing output capacitor size. Therefore, full range of Vbatt is utilized by

buck phases of the MSCB converter during light-to-heavy load transients, resulting in fast

transient recovery while reducing output capacitor size. In the MSCB converter, during large

light-to-heavy load transients minimum deviation block also changes operation of the switch

control logic by sending tr signal of Fig. 3.1, such that the capacitive divider is bypassed and the

equivalent circuit of Fig. 3.5 is formed. By sending tr and d1[n] signals to the DPWM block, as

shown in Fig. 3.1, the duty value created by PID compensator, d[n], is also overwritten by the

43

Transient/Low-input Mode

Cin1

Cin2 Q7

Q6

Cr

Lf Lp

G6

G7

Q1

Q2

Q3 Q4

Q5

iin(t)

vCr(t)vC1(t)

vC2(t)

iL1(t)

iL2(t)

ip1(t)

ip2(t)

Vbatt

L1

L2

Q8

G8 Q9

G9

Figure 3.5. Converter configuration during a light-to-heavy load transient and low input voltage

range Vbatt<2Vout.

d1[n] through minimum deviation block as described in [14], [15]. In this mode the inductor slew

rate is increased since the buck phases are supplied by the full input battery voltage. In addition,

the steady-state operation of the MSCB converter through modes A and B, provides buck stage

converters with half of input voltage, i.e. Vbatt/2. Since a buck converter can only produce output

voltages less than its input voltage, this will prevent the output voltage regulation during

operating conditions with input voltages where Vbatt/2 falls below Vout. Therefore, in the MSCB

converter, in case the operation for Vbatt < 2Vin is required by the application, when input voltage

falls below a certain level, the operation of the converter may continue in Transient/low input

mode as shown in Fig. 3.5, providing buck stages with full range of input voltage. This is done

through the following procedure.

Considering the gain function of the buck converter,

DV

VDM

in

out )( , (3.8)

44

where D is the dc value of the operating duty cycle. It can be found that for a given output

voltage, the minimum possible input voltage can be determined based on the known maximum

possible duty cycle ratio.

In the MSCB converter, as the DPWM block detects the duty cycle has reached its maximum

value during steady-state operation, i.e. when d(t)*Ts>(Ts-Tch), meaning that the input voltage

has reached its minimum; it sends lv signal to the switch control logic, making the capacitive

attenuator stage configured as shown in Fig. 3.5. Therefore similar to the load transient

condition, the buck stages start operating with full input voltage instead of Vin/2.

3.3 Practical Implementation

3.3.1 Output filter reduction

By looking at (3.1) it can be seen that, in comparison with the conventional buck, the 2-stage

converter topology allows the output filter inductor to be reduced by the ratio (Vbatt-2Vout)/(Vbatt-

Vout), where Vbatt is the input battery voltage. Theoretically, this reduction results in an equivalent

improvement of the inductor current slew rate and, consequently, proportional minimization of

the output capacitor. However, in practice the linearly proportional reduction is not feasible, due

to the finite delays of the control circuit. In the buck converter the size of output capacitor is

selected based on the maximum output voltage deviation during load transients (ΔVmax). In case

of a practical time-optimal controller, ΔVmax can be approximated as

)(2

2

maxmaxmax

outbattoutout

d

VVC

LI

C

tIv

45

where ΔImax is the maximum load current variation and td is the time delay since load transient

happens until the controller reacts. The first term on the right hand side of (3.9) is the result of

the delay in the time-optimal controller which is independent of inductor size. The second term is

due to the lost capacitor charge during the transient. As a result of the non-zero td, the smaller

inductor size will reduce the size of Cout however this reduction will not be directly proportional.

3.3.2 Component voltage ratings and start up transient

In the MSCB converter, reduction of the buck stage inductors and switching losses is achieved

through division of input voltage by two by the capacitive attenuator. Thus, each buck phase is

supplied only by half of the input voltage. This also allows for utilization of lower voltage rated

components for the MSCB converter.

Table 3.1 shows the components voltage ratings for this converter.

As shown in Table 3.1, the switches and capacitors of the capacitive attenuator stage are rated for

Vbatt/2 while the buck stage switches have to be able to block Vbatt mainly due to their operation

at transient mode, Fig. 3.5, where they have to block full range of Vbatt. Since the transistor ON-

resistance per unit silicon area [9], [16] is

Ron sp = α · VB 2

(3.10),

where α is fabrication process dependent constant and VB is the breakdown voltage, in an

optimized design where attenuator stage switches are designed with half of the blocking voltage

as that of the buck stage switches; this results in four times smaller resistance for each of them

for the same silicon area compared to buck switches.

46

However, practical implementation of the MSCB converter and two-stage topologies with

switched-capacitor voltage attenuation stage [5]-[7], utilizing lower voltage rated components

demands the voltage balance across the voltage divider capacitors to be valid at all times. A

significant voltage mismatch among capacitor voltages can results in damage to switches and

capacitors leading to a converter failure. In all these topologies the voltage balance across

capacitors is guaranteed during steady-state operation, however, a discrepancy of capacitor

voltages compared to their steady state desired values can occur due to load transients or during

system start up. In particular, obtaining proper voltage balance of capacitors remains as a

challenge for systems where a switched capacitor circuit is utilized for charge control of SC

stage, [5]-[7], during start-up. In conventional SC-based topologies, [5]-[7] it is not possible to

distribute the charge among all capacitors equally with an unvarying configuration of switches at

the start up moment. Thus during the time period from system start until the voltage balance

across all capacitors is achieved, depending on the SC circuit configuration, a number of

components will experience higher voltages than their steady state values. This translates into

requirement for components rated for higher voltages compared to their steady state blocking

voltages in the practical implementation. Hence conventional SC-based topologies cannot fully

utilize the advantages associated with lower voltage rated switch realization, i.e. smaller ON-

resistance. Depending on the SC converter topology, in some cases this problem can be solved

Table 3.1. MSCB converter component voltage ratings (assuming small ac ripple).

Component Cr Cin1,2 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8,9 Cout

Voltage rating Vbatt Vbatt /2 Vbatt /2 Vbatt /2 Vbatt /2 Vbatt /2 Vbatt /2 Vbatt Vbatt Vbatt Vout

47

Start-up configuration

Cin1

Cin2

Cr

Lf Lp

Q1

Q2

Q3 Q4

Q5

iin(t)

vCr(t)vC1(t)

vC2(t)

iL1(t)

iL2(t)

ip1(t)

ip2(t)

Vbatt

L1

L2

Q8

Q6

Q7

Q9

Figure 3.6. Converter configuration at start-up

with extra start-up circuitry which increasing overall system price and complexity [17]. A simple

solution to this start-up problem is a straight forward addition of start-up circuits that are placed

before the power stage and provide a soft input voltage rise for the SC converter [18]. Those

solutions introduce extra conduction losses addition of the start-up stage switches in the

conduction path. As opposed to previous art solutions [5]-[7], The MSCB converter does not

suffer from start-up and transient related issues due to imbalance of capacitor voltages. That is

mainly due to the series-parallel configuration of the capacitive attenuator of the MSCB

converter. By operating the SC stage in its series configuration during start up and load

transients, Cin1 and Cin2 being in series, they receive the same charge and maintain their equal

voltage balance all the time.

In the MSCB converter at the system start up, Q1 and Q2 are ‘on’, creating a series combination

of Cin1 and Cin2 while the rest of switches are kept ‘off’ as shown in Fig. 3.6. Therefore, Cin1 and

Cin2 receive same current from the input source, charging each of them to Vbatt/2 since they have

48

equal capacitance values. To avoid voltage misbalance due to mismatch in capacitor values, in

the practical implementation a resistive divider with big precision resistors is connected in

parallel with Cin1 and Cin2. The MSCB converter starts operating in steady-state mode when both

input capacitors are charged to Vbatt/2 after a certain period of time.

It is worth mentioning that another issue during a DC-DC converter start-up is that regardless of

converter topology, in case of utilizing an undamped LC input filter with low capacitor ESR,

input capacitors and switches can exposed to voltages up to 2Vin in case of connection of the

input filter to a low impedance input voltage source [10], [19] as shown in Fig. 3.7. This is

caused by formation of an LC circuit by input filter inductor (Lf) and capacitor (Cin) creating an

undamped voltage response across input filter capacitor. To some extent, the series resistance

(ESR) of input capacitor damps this voltage resonance. In fact, as shown in [19], by proper

choice of input capacitor type, a damped filter response can be achieved. Still, in case of utilizing

low ESR ceramic input capacitors, damped input filter design methods discussed in [10] can be

applied to eliminate this initial voltage overshoot across input capacitors. In the case of MSCB

converter a similar situation can also happen through resonance of PCB inductance (Lp) and

input capacitance (Cin1 and Cin2). In this case, the Ron resistance of switches Q1 and Q2 add up

to ESR of capacitors Cin1 and Cin2 and further damp the filter response. In case the expected

damped response is not automatically achieved, proper choice of input capacitor as presented in

[19] and damped filter design methods [10] can be utilized.

Similar to the start-up process, during load transients, the transient mode of operation in MSCB

converter utilizes the series configuration of input capacitors during load transients, as shown in

Fig. 3.5. This eliminates the possibility of creating voltage discrepancy between SC stage

49

loa

d

iin(t)

Vin

+

_Cin

Lf

DC-DC

converter

Input FilterVin

0

Vin

0

Vf

Figure 3.7. start-up transient of LC undamped input filter

capacitors by taking current from only one of the SC capacitors as is the case in previous

solutions.

3.3.3 Conduction losses and switch selection

The elimination of the energy storage capacitor of the SC stage also brings another main benefit

of this circuit compared to other SC-based solutions. Since the extra switches needed for the

control of energy storage capacitor are eliminated, the conduction losses are reduced. This

converter has just a minor increase in conduction losses compared to the conventional single-

stage buck. Fig. 3.8 shows equivalent circuits of the downstream buck for both portions of a

switching interval. When Q7 and/or Q9 are turned on, the downstream stage has the same

conduction losses as the conventional buck and only one low resistance switch is added during

the other portion of the switching interval. Also, since the switches Q1 and Q3 conduct relatively

small current, their conduction losses are relatively small. It can be seen that the new topology

introduces only one extra transistor during the “on states” of the buck phases and does not

increase the conduction losses during the “off” states. As seen from Table 3.1, the blocking

50

vC1(t)

vC2(t)

‘On’ State ‘Off’ State

Cin1

Q2

Q8

Q9

iL1(t) L1

Coutvout(t)

R

Q8

Q9

iL1(t) L1

Coutvout(t)

R

Cin2

Q6

Q7

iL1(t) L1Q4

Coutvout(t)

R

Q6

Q7

iL2(t) L2

Coutvout(t)

R

Figure 3.8. Equivalent circuits of the top and bottom phase of the downstream buck for the both

portions of a switching interval.

voltage of the extra transistors (Q2 and Q4) is Vbatt/2. Hence, their Ron resistances can be smaller

than that of the main switches Q8 and Q6 bringing a small extra contribution to the conduction

losses. In comparison with most other two stage solutions [5]-[7] this penalty in conduction

losses is minor.

It should be mentioned that these extra conduction losses are partially compensated by lower

inductor copper losses, through inductor series resistance, and core losses due to smaller inductor

of the MSCB converter.

3.4 Experimental system and results

To validate the advantages of the introduced 2-stage MSCB converter topology a 7V-to-1V,

10A, 1 MHz experimental prototype was built and its performance compared to that of an

equivalent interleaved buck.

51

Table 3.2. MSCB and multi-phase buck filter components parameters.

Parameter Lf Cr Lp Cin2/Cin1 L1 , L2 Cout

MSCB 100nH 1.6 µF 3n 18.8µF 400nH 35µF

Buck 100nH - - 18.8µF 470nH 40µF

The output filters of the both converters are selected so that current ripples are the same as well

as the output voltage deviation during zero to maximum current load transients. In both cases an

optimal controller [14], [15] resulting in theoretically minimum possible voltage deviation is

used. Also, the input filters are designed such that the converter input voltage ripple is the same.

The parameters of both converters are shown in Table 3.2.

It can be seen that the MSCB reduces the output filter inductor by 15% and the output capacitor

by 13% without paying penalty in the input filter size. The operation of SC stage and gating

signals during steady-state can be observed in Fig. 3.9. The light-to-heavy transient responses are

compared for 2 A to 8 A load steps (Figs.10 and 11). As shown, the MSCB has the same voltage

deviation and about 15% faster settling time than the buck. It can also be seen that, as predicted

by (3.2), the MSCB shares the current equally between the buck phases during steady state. Fig.

3.12 depicts the operation of the converter during start-up. As described before, by using the

start-up configuration of the switches, shown in Fig. 3.6, the voltage balance across input

capacitors, Cin1 and Cin2, is achieved before the converter steady-state operation starts,

eliminating the excessive voltage stress across components as is the case for switched capacitor

converters [5]-[7]. The efficiency results of both converters are shown in Fig. 3.13. The MSCB

52

improves efficiency by up to 9% at light loads (reduces losses by 35%) and by 3% for medium

loads, due to reduced switching losses.

Iin

Vcr

7V

Vc1

Vc23.45V

400mA

6.9V

Figure 3.9. SC stage waveforms and gating signals during steady state operation; top to bottom:

Ch.3 (top): input current, iin(t) (200mA/div); Ch.4 (upper middle): resonance capacitor voltage,

vcr(t) (200 mV/div); Ch.2 (lower middle): bottom input capacitor voltage, vc2(t) (0.5V/div); Ch.4

(bottom): top input capacitor voltage, vc1(t) (0.5V/div); digital channels 1 to 9 are gating signal

G1 to G9. Time scale is 200 ns/div. Operating conditions: vin= 7 V, Vout = 1 V, Pout ~ 2.5 W.

53

Vout

Vx1

IL1

IL2

7V

1V

4A

50mV

1A

2.1 µs

Figure 3.10. Transient response for buck converter; top to bottom: Ch.4 (top): output voltage,

vout(t) (50mV/div); Ch.2 (upper middle): switching node voltage for top phase, vx1(t) (10V/div);

Ch.1 (lower middle): top phase inductor current, iL1(t) (2A/div); Ch.3 (bottom): bottom phase

inductor current, iL2(t) (2A/div); Time scale is 2 us/div. Operating conditions: vin= 7 V, Vout = 1

V, load current step of 2A to 8A.

54

Vout

Vx1

IL1

IL2

3.5V7V

4A

1V

50mV

1A

1.7 µs

Figure 3.11. Transient response for MSCB converter: Ch.4 (top): output voltage, vout(t)

(50mV/div); Ch.2 (upper middle): switching node voltage for top phase, vx1(t) (10V/div); Ch.1

(lower middle): top phase inductor current, iL1(t) (2A/div); Ch.3 (bottom): bottom phase inductor

current, iL2(t) (2A/div); Time scale is 2 us/div. Operating conditions: vin= 7 V, Vout = 1 V, load

current step of 2A to 8A.

55

Vcr7V

Vc1

Vc2

3.4V

3.4V

Vout

Figure 3.12. Start-up transient of MSCB converter: Ch.4 (top): output voltage, vout(t) (1V/div);

Ch.3 (upper middle): resonance capacitor voltage, vcr(t) (2V/div); Ch.2 (lower middle): top input

capacitor voltage, vc1(t) (2V/div); Ch.4 (bottom): bottom input capacitor voltage, vc2(t) (2V/div);

Time scale is 5 ms/div. Operating conditions: start up from zero state to vin= 7 V, Vout = 1 V, Pout

~ 2.5 W.

56

50

55

60

65

70

75

80

85

90

0 1 2 3 4 5 6 7 8 9 10

BuckMSCB

-10

0

10

20

30

40

Power loss reduction

50

60

80

Po

wer lo

ss redu

ction

(%)

Eff

icie

ncy

(%

)

Load Current (A)

Figure 3.13. Efficiency and loss comparison of buck and MSCB converters for 7V-to-1V

operating condition.

57

3.5 Conclusions

A 2-stage digitally controlled converter that merges a switch capacitor converter (SC) with an

interleaved buck (MSCB) is introduced. Through utilization of buck inductors for SC tap

balancing, the MSCB eliminates a bulky energy transfer capacitor existing in other 2-stage SC

solution reducing conduction losses and controller complexity. Reduction of inductor size is

achieved by minimizing voltage swing across the inductor using the SC stage. The smaller

inductor size along with utilization of full range of input voltage allows for transient response

improvement and reduction of output capacitor size. To minimize switching losses of the SC a

quasi resonant switch is employed. At heavy loads the efficiency of the MSCB is comparable to

the conventional buck and at light and medium loads it is improved. The effectiveness of the

MSCB is verified experimentally by comparison with a conventional buck, where the

improvements in efficiency, filter volume, and dynamic response are demonstrated.

3.6 References

[1] N. Rahman, A. Parayandeh, K. Wang, and A. Prodić, “Multimode digital SMPS

controller IC for low-power management,” in Proc. IEEE International Symposium on Circuits

and Systems, 2006, pp. 5327 – 5330.

[2] J.Xiao, A.V. Peterchev, J. Zhang, and S.R. Sanders, “A 4-μA Quiescent-Current Dual-

Mode Digitally Controlled Buck Converter IC for Cellular Phone Applications,” IEEE Journal

of Solid-State Circuits, vol. 39, pp. 2342–2348, Dec. 2004.

[3] Y. Kaiwei, “High-frequency and high-performance VRM design for the next generations

of processors,” Ph.D. thesis, Virginia Polytechnic Institute and State University, 2004.

[4] “Intel Atom Processor 230 Series,” Intel Corp., Oregon, USA, April 2010.

[5] J. Sun, M. Xu, and F. C. Lee, “Transient Analysis of the Novel Voltage Divider,” in

Proc. IEEE Applied Power Electronics Conf., 2007, pp. 550–556. Feb. 2007.

58

[6] J. Sun; X. Ming, Y. Yucheng, F.C. Lee, "High Power Density, High Efficiency System

Two-stage Power Architecture for Laptop Computers," Power Electronics Specialists

Conference, 2006. PESC '06. 37th IEEE , vol., no., pp.1-7, 18-22 June 2006



Power Electronics Specialist Conf., 2008, pp. 4008-4015, June 2008.

[8] A. Radić, A. Prodić, "Buck converter with merged active charge-controlled capacitive

attenuation," IEEE Tran. on Power Electron. Vol.27, pp.1049-1054, Oct. 2011.

[9] W. Kesler, B. Erisman, G. Thandi, “Switched capacitor voltage converters,” Section 4

within Walt Kester, Editor, Practical design techniques for power and thermal management,

Analog Devices, Inc., 1998, ISBN 0-916550-19-2.



[11] R. Aparicio, A. Hajimiri. “Capacity limits and matching properties of lateral flux

integrated capacitors,” in Proc. IEEE Customs Integrated Circuits Conf., 2001, pp. 365-368,

May 2001.

[12] A. Prodić, D. Maksimović, "Design of a digital PID regulator based on look-up tables for

control of high-frequency DC-DC converters," in Proc. IEEE Computers in Power Electronics

Conf., June 2002, pp. 18-22.

[13] A. Syed, E. Ahmed, D. Maksimovic, E. Alarcon, "Digital pulse width modulator

architectures," IN Proc. IEEE PESC 04, vol.6, pp. 4689- 4695, June 2004

[14] A. Radić, Z. Lukić, A. Prodić, and R. de Nie, “Minimum deviation digital controller IC

for single and two phase DC-DC switch-mode power supplies,” in Proc. IEEE APEC 2010, pp.

1–6, Feb 2010.

[15] A. Radić, A. Prodić, and R. de Nie, “Self-tuning mixed-signal optimal controller with

improved load transient detection and smooth mode transition for dc-dc converters,” in Proc.

IEEE ECCE 2010, Sep. 2010

[16] Z. Lukic,A. Stupar, A. Prodić,D. Goder, "Current estimation and remote temperature

monitoring system for low power digitally controlled DC-DC SMPS," In Proc. IEEE PESC

2008, pp.1139-1143,June 2008

[17] Reusch, D.; Lee, F.C.; Ming Xu, "Three level buck converter with control and soft

startup," Energy Conversion Congress and Exposition, 2009. ECCE 2009. IEEE , vol., no.,

pp.31,35, 20-24 Sept. 2009.

[18] M.C. Chiang, W.C. Wang, inventors: Realtek Semiconductor Corp, assignee, " Soft-start

circuit having a ramp-up voltage and method thereof," US Patent US8390263 B2, March 2013.

http://www.google.com/search?tbo=p&tbm=pts&hl=en&q=inassignee:%22Realtek+Semiconductor+Corp.%22

59

[19] G. Perica, “Ceramic Input Capacitors Can Cause Overvoltage Transients,” Linear

Technologies, Milpitas, USA, application note 88, March 2001.

60

Chapter 4

Low-Volume PFC Rectifier Based On Non-Symmetric

Multi-Level Boost Converter

The previous chapter of this thesis introduced a high step-down converter based on the concept

of merging SC and inductive based converters. The focus of this chapter is design and

implementation of a high step-up converter that operates based on the same principle. One of the

most common applications where a high input voltage step-up is required is in PFC rectifiers.

Boost converter being one of the most commonly used topologies, here a novel multi-level

boost-based converter is developed and its application as a PFC rectifier is demonstrated. This

61

PFC rectifier is based on the introduced digitally-controlled non-symmetric multi-level boost

converter (NSMB) that requires three times smaller inductor and has lower losses than the

conventional boost based solution. The NSMB utilizes a non-symmetric output capacitive

divider as the output filter of the boost converter. Regulation of voltage across two output

capacitors at 1/3 and 2/3 of the full output level, creates a four level converter with similar

hardware requirements as of a three-level boost converter. This modification allows for further

reduction of the inductor voltage swing and, consequently, its minimization. This chapter is

organized as follows:

The first Section describes the motivation for this work. Section 4.2 explains the principle of

NSMB converter operation. In Section 4.3 challenges related to the control of the NSMB-based

PFC rectifier are addressed and a practical digital control based solution is presented. Section 4.4

shows experimental results that verify advantages of the NSMB-based converter over

conventional solutions.

4.1 Introduction

The boost converter operating in continuous current mode (CCM) followed by an isolated dc-dc

converter [1], [2] is among the most widely used configurations in single-phase rectifiers with

power factor correction (PFC). This is mostly due to the continuous input current of the boost

stage reducing electromagnetic interference (EMI) filtering requirements and fairly simple

controller implementation [2-5]. This topology is used in a wide range of applications requiring

between 100W and 500W of power. Some examples include laptop and personal computers,

monitors, communication equipment, LCD monitors, TV sets and other consumer electronics.

62

One of the major drawbacks of the boost-based front stage is a relatively large size of the

inductor limiting its use in weight and volume sensitive applications. The large inductor also

causes non-negligible core losses [5], [6] and results in a relatively large parasitic capacitance of

the winding introducing high frequency noise [7]. The conventional boost-based topologies also

suffer from problems related to switching losses [2], [8], causing heat dissipation, whose

handling often requires bulky cooling components. The switching losses are mostly related to the

operation of the transistor and the diode at the relatively high output, i.e. bus, voltage, which for

the universal input (85 Vrms to 265 Vrms) boost PFCs it is usually about 400 V.

To minimize the size of the boost-based PFC system inductors, a number of methods have been

proposed in the past [5-15]. Those can generally be divided into frequency-increase based such

as interleaved converters and topological changes such as multilevel converters. As discussed in

Chapter 2, frequency increased based suffer from relatively high switching losses and, when

operating at light and medium loads, from either degradation of efficiency or quality of the input

current waveform [16]. Multi-level converters [5-11], minimize both the inductor value and the

switching losses, by reducing the stress of the components at the cost of adding few switches and

relatively large flying capacitors. A three-level boost-based PFC [6] replaces the output capacitor

of the boost converter with a compact active capacitive divider and, for the same switching

frequency, results in a 50% reduction of the inductor value compared to the conventional boost-

based solutions.

The main goal of this chapter is to introduce a novel single-phase multi-level boost based PFC

rectifier based on merged inductive-based and capacitive attenuator concept that allows further

reduction of the inductor volume while maintaining the benefits of the previously presented -

multi-level solutions. The new converter, named non-symmetric multi-level boost (NSMB), and

63

its digital controller are shown in Fig. 4.1. The new converter and its controller are primarily

designed for the previously mentioned applications ranging between 100 W and 500W. The new

topology reduces the size of the boost inductor to a one third of the value required for the

conventional boost PFC using the same number and volume of components as the 3-level flying-

capacitor-less divider based solution [6]. In essence, utilizing similar hardware as a three level

converter, the introduced topology operates as a four level converter. This results in the

improvements similar to those obtained by moving from a conventional 2-level boost to a 3-level

topology without increasing hardware complexity. Like other multi-level solutions the NSMB

also reduces the switching losses and components voltage stress. The new topology is also well

suited to be used with efficiency optimization methods and techniques developed for

Liin(t)

C

2C

+

vout(t)

_

Q1

Q2

D2

+

2Vbus/3

_

+

_

D1

Signal comparators and

mode selector

Dual-input isolated dc-dc

downstream converter

H

vx(t)

+

vin(t)

_Full-wave diode

rectifier

vline(t)

+

_ Vbus/3

H

Load

vct(t)

vtop(t)

cd(t)

Hdvout(t)

H Hd

Input current and buss voltage regulator

Downstream stage

controller

Averaged current programmed mode

controller

Centre-tap voltage

regulator

Pulse redirection

logic

Hvtop(t)

Hvct(t)

d[n]Hvin(t)

cd1(t) cd2(t)c1(t) c2(t)

NSMB Controller

Rsiin(t) Hvin(t) Hvct(t) Hvtop(t)

c1(t)

c2(t)

Figure 4.1: Non-symmetric multi-level boost (NSMB) based PFC rectifier and its downstream

stage.

64

conventional boost based topologies [17]-[21], allowing all advantages of the previously

developed methods to be utilized here as well.

The inductor reduction is achieved by providing non-equal voltages across the capacitive divider

cells, through a capacitor divider with a 3:1 conversion ratio, and applying a switching scheme

that results in four inductor voltage levels. Compared to the conventionally used four-level boost

solutions [7], [12], the NSMB has the same inductor volume when operating at the same

switching frequency. Still, the new converter requires a smaller number of switching components

and eliminates the bulky flying capacitor for the regulation of the voltages of the divider taps. In

this case, as shown in Fig. 4.1, the capacitive divider voltages are regulated with the downstream

dc-dc converter that, compared to traditional solutions, also has smaller volume and better

efficiency, due to reduced voltage swing across its components.

The controller for the NSMB PFC of Fig. 4.1 consists of two blocks, input current and bus

voltage regulator and the centre-tap voltage regulator. The first block, regulates the input current

iin(t) and the intermediate bus voltage Vbus, i.e. the output voltage of the first stage. This block is

a modification of the digital average current programmed mode solution presented in [22]. The

second block regulates the centre tap voltage of the capacitive divider vct(t) such that the divider

attenuation ratio of 3:1 is constantly maintained. This regulation is performed by steering the

input currents of a dual-input downstream stage and, in that way regulating the discharging of the

two capacitors. This block is designed to operate in synchronization with any dedicated constant

frequency controller of the downstream stage producing a pulse width modulated signal cd(t).

65

4.2 Principle of Operation of The Non-Symmetric Multi-Level

Boost-Based (NSMB) Front end PFC Stage

To minimize the inductor volume, the introduced non-symmetric multi-level boost (NSMB)

converter of Fig. 4.1 operates on the same fundamental principles as other multi-level solutions.

It utilizes the fact that by reducing the voltage swing across the boost inductor the inductance

value can be reduced as well.

The relation between the inductance value L and the maximum voltage swing of the inductor can

be described with the help of the circuit and timing diagrams shown in Fig. 4.2.a. The figures

demonstrate variation of the inductor voltage in a general boost-based converter operating with

constant output voltage. In the presented equivalent circuit vx_on(t) and vx_off(t) are the values of

the switching node voltage during the inductor charging and discharging phase, respectively.

Figure 4.2.b shows that for the conventional boost the two values are equal to vx_on(t) = 0 and

vx_off(t) = Vbus.

As described in Chapter 2, the inductor size in an inductive based converter is determined based

on the maximum desired inductor current ripple, where for the boost converter it can be found

from Eq. 2.3. For a more general case of the boost-based converter of Fig. 4.2, this current ripple

can be found using a similar methodology. The analysis starts from the expressions for the

inductor current ripple for a general boost-based converter:

I r ipplevL _high(t)

2L

D

fswvin (t) vx_on

2L

D

fsw (4.1)

66

Ir ipplevL_ low(t)

2L

D'

fs wvin (t) vx_off

2L

D'

fs w

, (4.2)

where, vL_high(t) and vL_low(t) are the high and the low values of the inductor voltage during one

switching cycle, respectively, vin(t) is the input voltage, fsw is the switching frequency of the

converter, and D is the duty ratio.

The maximum ripple, occurring for D = 0.5 [6], can be described with the following expression,

obtained by combining (4.1) and (4.2):

I ripple_max vL _high(t) vL _ low(t)

8L1

fswVswing_L

8L

1

fswVswing_ x

8L

1

fsw , (4.3)

where Vswing_L and Vswing_x are the voltage swings of the inductor and switching node, respectively.

_

Liin(t)

Vx_on

+vin(t)

_

+

vx(t)

+

_vL(t) +

_

vL

vx

0 d(t)Ts

Vx_off

vin(t)-vx_off

vin(t)-vx_on

b)a)

Vx_off

+

_

SW1

SW2

Vx_on

t

t

Vswing

Vswing

Liin(t)

vin(t)

_

+

vx(t)

+

_vL(t)

_

SW1

SW2

vL

vx

0 d(t)Ts

Vbuss

vin(t)-Vbuss

vin(t)

0

t

t

Vswing

Vswing

CVbus

_

+ +

Ts Ts

SW1 - on

SW1 - on SW2 - onSW2 - on

loa

d

Figure 4.2: Equivalent circuit for the analysis of the inductor voltage swing and the voltage

waveforms of (a) a general boost-based converter and (b) the conventional boost.

67

It can be seen that the ripple, which determines the inductance value [23], is linearly proportional

to the voltage swing across the switching node. The relation also shows that, for the boost based

converters, the inductor voltage swing is equal to the switching node swing and by minimizing

that value, the inductor can be reduced without affecting the current ripple amplitude.

This analysis shows that for the conventional boost the switching node voltage swing is equal to

its output voltage. In typical PFC rectifiers, this voltage, labeled as Vbus in Fig. 4.2.b, is fairly

high, usually around 400 V, causing the inductor value and the switching losses to be relatively

large. In the applications of interest, the switching losses usually have a large influence on the

overall power processing efficiency of the converter [5], [6], [24]. The losses also indirectly

increase the overall system volume, by imposing additional cooling requirements for the

semiconductor components.

To minimize the swing and, therefore, reduce both the inductor value and switching losses, in the

NSMB converter of Fig. 4.1, an active capacitive divider with 3:1 conversion ratio replaces the

output capacitor and switches of the conventional boost. This allows the switching node voltage

to be changed between four possible values: 0, Vbus/3, 2Vbus/3, and Vbus, effectively creating a 4-

level structure using a 3-level configuration. The divider and its switching sequence are designed

to allow vx_on(t) and vx_off(t) to be dynamically changed as the input voltage changes, such that the

inductor voltage swing is limited to Vbus/3. This value is three times lower than that of a

conventional boost and 33% smaller than the voltage swing of the 3-level topologies [6], [7]

operating at the same effective switching frequency. As a result equal reductions of the inductor

are allowed and large efficiency improvements obtained. It should be noted that similar to the

solution presented in [6] it would be possible to operate the NSMB at the twice switching

frequency of the conventional boost while maintaining the same power processing efficiency.

68

Such an operation would result in a 6 times smaller inductor volume compared to that of the

conventional boost, but would significantly increase power dissipation per unit volume

potentially resulting in increased cooling requirements and reliability problems. For that reason,

throughout the paper comparison was performed with the assumption that the topologies operate

at the same effective switching frequency and simultaneous improvements in power processing

efficiency and volume reduction are targeted.

4.2.1 Non-symmetric active capacitive divider

The operation of the non-symmetric capacitive divider can be explained by looking at the

rectified line input voltage and diagrams of Figs. 4.3 to 4.5. The diagrams describe three

distinctive modes of converter operation, which depend on the instantaneous value of the

rectified line voltage vin(t) = |vline(t)| (Fig. 4.1).

Mode 1: for vin(t) < Vbus/3 the converter operates in mode 1, depicted with the diagrams of Fig.

4.3. Throughout this mode, switch SW1 is kept on, reverse biasing the diode D1, and the other

two switches (SW2 and D2) are active, operating at the switching rate fsw = 1/Tsw. The on-time of

SW2, i.e. duty ratio, is regulated by the controller of Fig. 4.1. The current conducting paths for the

both portions of a switching period are shown in Fig. 4.4 with bold lines, in red, where Fig. 4.3.a

corresponds to the inductor charging process, i.e. on-time of SW2, and Fig. 4.3.b shows its

discharging.

It can be seen that during the on-state of SW2, vx(t) = 0 and during its off state vx(t)=Vbus/3.

Therefore, the maximum voltage swing across the inductor is Vbus/3 equal to the voltage of the

69

vin(t)

Vbus/3

2Vbus/3

0

a)

Tline/2

2C

Liin(t)

Q2

D1

D2

C

+

_

+

_Vbus/3

2Vbus/3

Discharge

vin(t)

_

+

vx(t)=Vbus/3Liin(t)

Q2

D1

D2

C

+

_

+

_Vbus/3

2Vbus/3

Charge

vin(t)

_

+

vx(t)=0

2C

b) c)

Q1 Q1

Mode 1

Figure 4.3: Mode 1 of operation of the non-symmetric multi-level boost front-end stage: a) input

voltage range for mode 1; b) equivalent circuit of the converter during inductor charging phase;

c) equivalent circuit during the discharging.

divider bottom capacitor. It should be noted in this mode both SW2 and D2 operate at Vbus/3 and

the switching losses including diode recovery loss are lower than those of the conventional boost

and 3-level boost, which switches operate at Vbus and Vbus/2, respectively

This mode is maintained as long as vin(t) is lower than Vbus/3 and the condition for the regular

boost operation, i.e. the bottom capacitor voltage is larger than the input voltage, satisfied.

Mode 2 of operation, shown in Fig. 4.4, occurs for Vbus/3 < vin(t) < 2Vbus/3. In this mode, during

the first portion of a switching period, corresponding to the transistor on-state in the conventional

topology, SW1 and D2 are turned on and the switching node voltage is Vbus/3 as it can be seen

from Fig. 4.4.a). During the remaining portion of the switching period, SW2 and D1 are

conducting and, as shown in Fig. 4.4.b), the switching node voltage is 2Vbus/3. It can be seen that,

in this way, the absolute value of the voltage swing is again limited to Vbus/3.

In this mode, the switching losses are approximately the same as those of the conventional boost

(and 3-level boost), since the total blocking voltage of the two switches operating in the each

portion of a switching interval is equal to that of the conventional boost.

70

L

Q1

Q2

D1

D2

+

_

+

_

vin(t)

0

vin(t)

_

+

Tline/2

Vbus/3

C

2C

2Vbus/3

2Vbus/3

Vbus/3

L

Q1

Q2

D1

D2

+

_

+

_

vin(t)

_

+

vx(t)=2Vbus/3

Vbus/3

C

2C

2Vbus/3

DischargeCharge

vx(t)=Vbus/3iin(t)iin(t)

b)a) c)

Mode 2



the discharging.

Mode 3, shown in Fig. 4.5, is activated when vin(t) exceeds 2Vbus/3. Throughout this mode the

transistor SW1 is turned off allowing diode D1 to conduct. In this mode, during the first portion of

the switching interval, SW2 is conducting and the voltage across the switching node is 2Vbus/3 as

shown in Fig. 4.5.a). During the second portion of the interval, D2 conducts and the switching

node voltage is Vbus. Again, the inductor voltage swing is limited to Vbus/3.

In this mode the switching losses including diode recovery loss are again lower than that of the

conventional boost and of the 3-level boost, since both SW2 and the D2 interrupt only one third of

the converter output voltage.

Since, as mentioned earlier, in the applications of interest the switching losses are dominant, an

analysis of conduction losses for the NSMB is given in Appendix A.1. It is shown that the

conduction losses depend on the input voltage amplitude and the amounts of time NSMB spends

in each of the three modes. The analysis also shows that, for an optimally designed NSMB, with

switches D1, SW1 rated at 2Vbus/3 and SW2, D2 rated at Vbus/3, the conduction losses are

approximately the same as those of the conventional boost.

71

L

Q1

Q2

D1

+

_

+

_

D2

vin(t)

0

vin(t)

_

+

Mode 3

Tline/2

vx(t)=2Vbus/3

2C

2Vbus/3

Vbus/3

2Vbus/3

Vbus/3

L

Q1

Q2

D1

+

_

+

_

D2

vin(t)

_

+

vx(t)=Vbus

C

2C

2Vbus/3

Vbus/3

DischargeChargeiin(t)iin(t)

b)a) c)

C



the discharging.

4.2.1.1 Volume Reduction

A. Inductor Volume

As shown in the theoretical analysis of Section 2, the NSMB converter reduces the inductor

value by three times compared to the conventional boost while retaining the same peak inductor

current.

Since the inductor volume is proportional to its energy storage capacity [25], [26]:

WE_L 1

2LIpeak

2

, (4.4)

where Ipeak is the peak inductor, it can be concluded that the inductor volume of the NSMB is

three times smaller as well.

It should be noted that compared to the practical two-phase boost interleaved PFC solutions [13],

[25], [26] the inductor of the NSMB is about two times smaller. Even though the inductance

72

value of the interleaved boost is reduced by four times, compared to the conventional boost the

volume reduction is much smaller. As described in [25], [26], the actually achievable volume

reduction is around a 32%, due to the higher inductor current ripple and, therefore, a larger peak

current.

B. Output capacitor volume

In the NSMB converter, the output capacitor of the conventional boost with a value of Cout, rated

at Vout, is replaced with Cout1 = 3Cout/2, rated at 2Vout/3 and Cout2 = 3Cout, rated at Vout/3. The

output capacitance of the boost PFC is chosen to meet desired hold-up time energy requirement

[27] and the output voltage ripple.

By using the same energy-based criteria to compare the capacitors sizes it can be seen that the

NSMB has the same total capacitor volume as the conventional boost and the 3-level boost,

since, ideally, the size of a capacitor is proportional to its energy storing capacity [28], i.e. to its

1/2CV2 product.

The output voltage ripple is comprised of two components, the high frequency ripple, at the

switching frequency, and the low frequency component at twice the line frequency. In both the

conventional boost PFC and the introduced NSMB the high frequency component is much

smaller than the component at the twice line frequency and therefore, can be neglected in the

analysis [23]. The following analysis shows that the dominant low frequency component is the

same for the both topologies.

To find the amplitude of the dominant ripple, we can look at the general case, where an increase

of the energy E creates a voltage difference V across the capacitor C having an initial voltage

73

V. This voltage difference can be found using the following relation:

)2(2

1)(

2

1)(

2

1 222 VVVCVCVVCE . (4.5)

For the case when V >> V, which is valid for the systems under investigation, the following

approximate expression for the voltage deviation:

CV

EV

, (4.6)

can be easily derived from (4.5).

For a general PFC, the increase of the energy can be calculated by looking at the instantaneous

power delivered from the ac source [23],

)]2cos(1[)( tPtplineloadin

, (4.7)

which, as shown in Fig. 4.6, has two components, a dc component equal to the load power Pload

and an ac component at twice the line frequency. The ac portion of this input power (Pin_ac(t)

shown in Fig. 4.6.b) creates the dominant output voltage ripple. To calculate the peak-to-peak

value of this ripple, the amount of energy stored in the capacitor over a Tline/4 period (shaded

area in the diagram of Fig. 4.6.b) can be calculated as:

line

load

Tt

t

lineload

Tt

t

acinacin

PdttPdttpE

lineline

4/4/

__

0

0

0

0

)]2cos([.)( , (4.8)

and the output capacitor ripple for a boost PFC found by combining (4.6) and (4.8):

74

outoutline

load

outout

acin

boostoutVC

P

VC

EV

_

_2 . (4.9)

In the case of the NSMB converter, the energy described with (4.8) is stored across the two

output capacitors Ctop and Cbottom. The distribution of this energy between capacitors, in general,

is not equal and depends on the input voltage level and the portion of the time the converter is

spending in each of the operating modes. However, the total energy given to the system is the

same as in the boost case and can be described with the following expression:

bottomacintopacinacinEEE

_____

, (4.10)

where Ein_ac_top and Ein_ac_top are the portions of energy stored in the top and bottom capacitors,

respectively.

ΔEin_acvout(t)

Pin_ac(t)Pload

Tline/4

Vout

vline(t)iin(t)

pin(t) Tline/2

a)

b)

c)

2ΔVout

t

t

t

t0 t0+Tline/4

0 Tline

Figure 4.6. Waveforms of the output capacitor voltage of an ideal PFC circuit; instantaneous

input power, voltage and current waveforms (a); decomposition of input power components (b);

and output capacitor voltage ripple (c)

75

By replacing the values in (4.6) for the NSMB case, the voltage ripples for the top and bottom

capacitors Vtop and Vbottom, respectively, can be obtained as:

outout

bottomacin

outout

bottomacin

bottomoutbottomout

bottomacin

bottomoutVC

E

VC

E

VC

EV

____

__

__

_)3/)(3(

2

, (4.11)

outout

topacin

outout

topacin

topouttopout

topacin

topoutVC

E

VC

E

VC

EV

____

__

__

_)3/2)(2/3(

2

, (4.12)

and, since both of the ripple voltages are in phase, the overall ripple of the NSMB can be found

as:

outoutline

load

outout

acin

outout

bottomacintopacin

NSMBout

bottomouttopoutNSMBout

VC

P

VC

E

VC

EEV

VVV

_____

_

___

2

,222

. (4.13)

A comparison of (4.9) and (4.13) reveals that both converters have the same ac output voltage

ripple while utilizing same output capacitance volume.

C. Input filter volume

To fully assess advantages of the NSMB topology over other solutions, input filter requirements

are compared in the following subsection. It is shown that, due to the lower energy of the input

current ripple and noise components, the NSMB potentially can operate with a smaller input

filter than that of the conventional boost and of the standard 3-level boost. In here, the

topological differences in the analysis of the filter requirements are only taken into account and

the other parameters, such as, influences of the PCB layout and footprints of the components,

which also affect the filter volume [29], are left to be studied in the future.

76

A properly designed input filter attenuates the input current ripple and two noise components

generated by the switching action of the power supply. Those are the differential mode (DM)

noise and common mode (CM) noise.

The previous analysis shows that, for the same switching frequency and three times smaller

inductor, the maximum amplitude of the inductor current ripple is the same for all three

configurations. However, as it will be confirmed in the experimental results section, in the case

of the NSMB the total rms value of the ripple component is smaller than that of the conventional

boost, due to longer periods during which the converter operates with close to zero ripple during

mode transitions.

To analyze the influence of the noise components, the equivalent circuits of Fig. 4.7 can be used.

The figure shows the input filter, which includes the ripple and DM reduction components Cx

and LDM and the portion of the filter for CM reduction, comprising of Cy and LCM.

The differential component of the high frequency noise is formed by the current flowing through

the input port of the converter [29], through a path formed by the stray capacitances of the

inductor (labeled as CL1 and CL2). In the case of the NSMB this stray capacitance is smaller than

those of the conventional boost and the 3-level boost, due to the smaller value of the inductor

itself [7]. Therefore, this noise is smaller, as demonstrated in the spectrum measurement, shown

in the experimental section. The low common mode noise allows for reduction of the differential

mode filter components.

The CM noise is mainly generated by the currents flowing from the switching node to the ground

through the parasitic capacitance created mainly by the heat sinks [29], in Fig. 4.7 labeled as Cp1

to Cp6. The power of that noise, and therefore the size of the common mode filter, is proportional

77

L

C1

2C1

SW1

SW2

D2

+

2Vbus/3

_

+

_

D1vx(t)

Vbus/3

iin(t)

vin(t)

_

+Cp3

Cp5Full-wave

diode

rectifier

vline(t)

+

_

Cy1

Cy2

Cx1 Cx2

Input filter

Cp6

Cp4

~~~~

~~

CL2 Cd2

Cs2

Cs3

Cd3

L

C1SW1

+

Vbus

_

D1

vx(t)

iin(t)

vin(t)

_

+ +

_

Cp1

Full-wave

diode

rectifier

vline(t)

+

_

Cy1

Cy2

Cx1 Cx2

Input filter

Cp2

~~~~

CL1 Cd1

Cs1

LDM1

LDM2

LCM

LDM1

LDM2

LCM

Figure 4.7: The input filter and parasitic capacitances of the boost PFC circuit (top) and NSMB

PFC (bottom) circuits.

to the amount of energy stored in those parasitic capacitances during each switching cycle.

Even though the NSMB (and conventional 3-level boost) have a larger number of parasitic

components commutating between the switching node voltage level and the ground, the energy

dissipated in them is smaller. This is mainly due to a lower voltage swing. Fig. 4.7 shows that in

the boost converter, in each cycle, the heat sink parasitic capacitors of SW1 and D1 (Cp1 and Cp2)

are charged/discharged with a voltage swing equal to Vbus, where the size of each capacitor is

proportional to the switch size and the heat sink area. Therefore, the common mode noise is

proportional to the energy transferred through these two capacitors

78

.2

1

2

1 2

2

2

1_ buspbuspboostcmVCVCW (4.14)

In the case of the NSMB converter, the parasitic capacitors Cp1 and Cp2 are replaced by

four capacitors, i.e. Cp3 to Cp6 corresponding to SW1, D1, SW2 and D2, respectively (Fig.

4.7). Those capacitors are exposed to a three times smaller voltage swing and therefore,

their total energy by averaging over different modes of operation is approximately

.18

1

18

1

18

5

18

3 2

6

2

5

2

4

2

3_ buspbusbuspbuspNSMBcm VCVCVCVCW (4.15)

By comparing (4.14) and (4.15) it can be concluded that, considering cp1≈ cp3≈ cp4≈ cp5 >> cp2,

cp6 since the heat sink connected nodes (cathodes) of D1of boost and D2 of NSMB are not

switched, i.e. for the case when Cp3+Cp4+Cp5+Cp6=3*(Cp1+Cp2), the total energy stored in the

capacitances causing CM noise is about 1/2 times smaller for the NSMB case. A similar analysis

for the 3-level boost can show that, since its voltage swing is Vbus/2, the total reduction of the

energy compared to the boost with the same capacitances is about ½ as well. In an optimized

design of the NSMB (discussed in the Appendix A.1), where switching components and heat

sinks are smaller, an even larger improvement in the common mode noise reduction can

potentially be achieved.

4.2.2 Centre tap voltage balancing and isolated downstream stages

The balancing of the capacitor tap voltages in converter topologies incorporating capacitive

voltage dividers is often performed with relatively large flying capacitors [30], [31] or by

redirecting the current of the inductor [6], [12], [32]. For the introduced NSMB the previously

79

used centre tap voltage regulation method cannot directly be applied, due to the non-equal

voltage sharing.

To regulate the centre tap voltage at Vbus/3 without a flying capacitor, here, the downstream

converter, inevitably existing in practically all systems of interest, is used. In order to perform

the charge balancing across the output capacitors a down-stream stage that utilizes a similar

concept of merged input capacitive attenuator with inductive based converter is adopted.

Therefore, the down-stream stage can also benefit from reduced inductor size, reduced voltage

stress across its switches and hence reduced losses in the same way as the MSCB converter of

Chapter 3. However, since isolation is often a requirement for the PFC downs-stream DC-DC

converter, here, adoption of same hybrid SC-inductive concept on flyback and forward

converters as shown in Fig. 4.8 has been explored.

The tap regulation is performed by modifying the technique presented in [32], where the input

current of the downstream portion of a merged switched-capacitor buck converter regulates the

centre-tap voltage of its front end. In this case, a two-input isolated downstream stage is used, as

shown in Fig. 4.8. The centre tap voltage is regulated with the two input currents of the

downstream converter, i1(t) and i2(t) with the help of the centre tap voltage regulator.

Depending on the centre-tap voltage level, the switch-selection logic redirects the pulse-width

modulated signal produced by the dedicated downstream stage controller, cd(t), between the two

switches (SWd1 and SWd2). The switches are controlled such that the current (charge) is taken

either from the top or from the bottom capacitor only. When the centre tap voltage is exceeding

desired Vbus/3 level more current is taken from the bottom cap and when it is lower the top cap

provides more current.

80

Vbus/3

2Vbus/3

SWd1

SWd2

Dual-input isolated

dc-dc converter

vout(t)

i1(t)

Downstream stage

controller

cd(t)Centre-tap voltage

regulator

To SWd1 and SWd2

i2(t)

Load

2C

iload(t)

+

_

+

+

_

C

_

vout(t)Vbuss/3

Vbuss

Figure 4.8: Block diagram of the centre-tap voltage balancing system based on the downstream

converter current steering.

4.3 Practical Controller Implementation

The controller of Fig. 4.1 consists of two main blocks: input current and voltage regulator and

centre-tap voltage regulator. This section addresses challenges related to the practical NSMB

controller realization and shows a hardware-effective solution for its implementation.

4.3.1 Input current and bus voltage regulator

The controller of Fig. 4.9 is a modified version of the average current programmed mode

architecture used for a conventional boost based PFC [33]. In this modification, a new block,

81

Windowed

ADC1

ev[n]kn/Re[n] Voltage loop

compensator

d[n]

ei[n]

Vref

vi_ref(t)

1-bit

∑Δ

Mode selector &

sampling seq.

generator

cmp1

Level

shifter

Rsiline(t)

Windowed

ADC2

Merged multiplier & D/A

Current loop

compensator

reprogram

Digital logic

c(t)

Hvin(t)

Rsiline,avg

Hvtop(t)

DPWM

Low-pass

filter

cmp2

Hvtop(t)Hvct(t)

Input current and bus voltage regulator

c1(t) c2(t)

in.en.Rf

Cf

sel1

Figure 4.9: Block diagram of the input current and bus voltage regulator.

named mode selector and sampling sequence generator is added and the sampling sequence

modified, to accommodate operation with a larger number of switches and eliminate potential

stability problems that will soon be addressed. For the same reason the current loop compensator

is also slightly modified.

The regulation of the input current and the output voltage is performed in a similar manner as in

the previous solutions [33], [34], [35]. Based on the digital equivalent of the bus voltage, error

value ev[n] is produced by the ADC1. Based on this value the voltage loop compensator creates a

signal k[n]/Re, which is inversely proportional to the desired emulated resistance seen at the

input of the PFC rectifier [23]. This value is then passed to the 1-bit sigma-delta modulator that,

together with the level shifter and the RC filter creates a structure behaving as a merged analog

multiplier and digital-to-analog converter eliminating the need for a costly digital multiplier [33].

82

This merged structure produces an analog reference

einrefi

R

nktHvtv

][)()(_

(4.16)

for the current loop, where, H is the gain of the input voltage attenuator and, as mentioned

before, vin(t) is the rectified input voltage (Fig. 4.1). The created analog value is used as the

reference for the current loop. This reference is then compared to the output of the input current

sensor Rsiline(t) and a digital equivalent of the current error signal ei[n] is created, by the

windowed ADC2 [33], [36]. The resulting error is sent to the current loop PI compensator that

produces control signal [33]:

]1[][]1[][ nbenaendnd ii (4.17)

where, d[n] and d[n-1] are the current and previous value of the duty ratio control variable, and

the compensator coefficients a and b are selected following the procedure shown in [36]. The

produced d[n] value is the control input for the digital pulse-width modulator (DPWM)

producing pulse width modulated signal c(t).

The produced pulse-width modulated signal c(t) is then passed to the mode selector, which

operation is described in the following subsection.

To eliminate switching noise related problems and at the same time obtain the average value of

the inductor current over one switching cycle, the current is sampled using the techniques

described in [38], [39]. Depending on the instantaneous value of d[n], the current is sampled

either at the half of the “on” or at the half of the “off” portion of a switching interval.

83

4.3.2 Mode selector and sampling sequence generator

The mode selector and sampling sequence generator, whose block diagram is shown in Fig. 4.10,

outputs pulse-width modulated signals c1(t) and c2(t) for controlling the NSMB transistors SW1

and SW2, respectively. During mode transients the selector also changes stored values of the

digital current loop compensator, to provide seamless transition between different modes. The

detection of the mode of operation is performed with the two comparators (cmp1 and cmp2) and

with the start-up logic, shown in Fig. 4.10. The comparators cmp1 and cmp2 monitor the input

voltage and detect the transition points at which the vin(t) = vct(t) =Vbus/3 and vin(t) = vtop(t) =

2Vbus/3. The compensators also initiate mode transition by sending the signals to the mode

transition logic. Based on the state of the comparators and the previous state of the NSMB power

stage the transition logic redirects c(t) to appropriate transistors. The start-up detector indicates

reprogram

sel1

ev[n]

Mode Selector and s.s. Generator

c(t)

start

sel2

c1(t)

c2(t)Mode transition logic

Start up

detectorS&H1

Hvin

sel1 S&H2sel2

+_

cmp1

+_

cmp2

Hvct Hvtop

Figure 4.10: Block diagram of the mode selector and sampling sequence generator.

84

power up condition of the converter by observing ev[n] and sends the start signal to the mode

transition. logic, which provides a gradual rise of the bus voltage upon a power up. The mode

transition logic

is a finite state machine (FSM), which operation is demonstrated with the diagram of Fig. 4.11

and described in the following subsections.

4.3.2.1 Seamless mode transitions

To understand the stability problem and a solution for it we can observe how the required

conversion ratio changes in the conventional boost based PFC and in the NSMB based system. In

the conventional boost, to maintain a constant bus voltage, the conversion ratio changes

gradually with changes in the input voltage. On the other side, in the NSMB the conversation

ratio drastically changes with each mode transition. Therefore, the duty ratio value required for

maintaining the inductor volt-second balance and the stable output voltage abruptly changes as

well. From a practical point of view this represents a potential problem, since the delays in the

controller reaction could cause mode transition related stability problems.

For example, it can be seen that at the point where the vin(t) is exceeding Vbus/3 (mode 1 to mode

2 transition) the required conversion ratio changes from one to infinity, requiring controller to

change from 0 to full duty ratio value in a single switching cycle.

To overcome this problem, after each mode transition, the mode selector immediately

reprograms the current and the previous values of the duty ratio in the digital current loop

compensator, i.e. d[n] and d[n-1] of Eq. 4.17. This is performed through the reprogram signal,

shown in Fig. 4.10. The decision about the new duty ratio values is made based on the

85

recognition that after each mode transition, the new duty ratio will be either zero or one. Since at

those points, the required conversion ratio of NSMB is either one or infinite. Therefore, after

each transition point is detected by the comparators, the mode control logic either sets both d[n]

and d[n-1] to 0 or to their maximum value. The diagram of Fig. 4.11 shows the reprogramming

values of the PI compensator for all four mode transitions.

4.3.2.2 Sampling sequence

By looking at the operation of the NSMB (Figs. 4.3 to 4.5) it can be noticed that for some

switching states one of the two output capacitors does not share the same ground with the rest of

Mode 1

c1(t) = 1

c2(t) = c(t)

Start = 1

Start = 0

cmp1 = 0

cmp2 = 0

cmp1 = 0

Mode

selection

Start-up

c1(t) = c(t)

c2(t) = c(t)

cmp1 = 1

Mode 2

c1(t) = c(t)

c2(t) = c(t)

cmp1 = 1

cmp2 = 0

PI Reprogram

d[n] = max

d[n-1] = max

Mode 3

c1(t) = 0

c2(t) = c(t)

cmp1 = 1

cmp2 = 1

cmp2 = 1

PI Reprogram

d[n] = 0

d[n-1] = 0

cmp2 = 1PI Reprogram

d[n] = max

d[n-1] = max

PI Reprogram

d[n] = 0

d[n-1] = 0

cmp2 = 0

cmp1 = 1

cmp2 = 0

cmp1 = 0

Figure 4.11: State flow diagram of the mode selector logic.

86

the circuit. While from the output load, which is galvanically isolated from the front end stage,

this does not represent a problem, this floating ground affects measurements of the capacitor tap

voltages. To measure the tap voltages without the use of relatively costly differential amplifiers,

sample and hold circuits (S&H) shown in Fig. 4.10 are used, and the sampling of the capacitor

tap voltages is done at particular time instants denoted by signals smp1 and smp2 as shown in the

diagram of Fig. 4.12. The value of the top capacitor voltage is sampled during the on state of Q2

and for the bottom capacitor the data acquisition is performed during D2 conduction time. The

ADC1 (Fig. 4.1) also samples vtop(t) during D2 conduction time, to obtain the bus voltage value.

4.3.2.3 Start up

The bypass diode commonly used to ease start-up and inrush current problems in conventional

boost solution [40] cannot be used with the NSMB and similar multi-level solutions [4], [5], [6],

[9]. As shown in Fig. 4.13, the bypass diode Ds, [40] would short connect the inductor during the

c2

sel1

t

t

dTsw

Tsw

tblanking

t

tblanking

tblanking

sel2 tblanking

Figure 4.12: Waveforms of the sampling sequence generator.

87

first portion of switching period in mode 3 (Fig. 4.5.b), when vin(t) > vtop(t).

To eliminate the start up problem, the switching sequence is modified during power up, signaled

by the high value of start signal produced by the detector (Fig. 4.10). During this mode the

NSMB operates as a conventional boost, such that both transistors, i.e. Q1 and Q2 of Fig. 4.1, are

turned on during the first portion of a switching interval and D1 and D2 are allowed to conduct

during the rest of the switching period, as shown in Fig. 4.11. Such operation delivers equal

amounts of charge to the both divider capacitors and, ideally, the desired 2:1 distribution of the

bus voltage. Possible voltage variations due to component tolerances are eliminated with the

bleeding resistors [41] Rb forming a 3:1 resistive divider. This mode ends when the capacitors

arecharged to their reference values and the start signal becomes low, causing the NSMB to

switch to the regular mode of operation described in Section 2 and by the diagram of Fig. 4.11.

To eliminate inrush current problem a number of previously presented solutions can be used

[40], [42-44].

L

Q1

Q2

D1

+

_

+

_

D2

vin(t)

0

vin(t)

_

+

Mode 3

Tline/2

2C

2Vbus/3

Vbus/3

2Vbus/3

Vbus/3

iin(t)

CFull-wave

rectifier

Dst

vline(t)

+

_

Rb

2Rb

Figure 4.13: Problem of utilizing bypass diode in the NSMB topology.

88

4.3.3 Centre-tap voltage regulator

As described in the previous section, the regulation of the capacitor voltages is performed with

the input current of the downstream converter. This process is controlled by the centre-tap

voltage regulator that redirects current of the downstream and in that way, regulates the

discharging of the both NSMB capacitors.

The downstream converters that can be used with NSMB have two inputs and also utilize the

advantages of reduced voltage swing to minimize the volume and switching losses. Two of many

possible implementations of the downstream stages include two input non-symmetric flyback

[22] and the two-input non-symmetric forward, shown in Figs. 4.14 and 4.15, describe the

operation of the centre-tap voltage regulator with a non-symmetric forward converter. The

transformer of the forward has two primary windings, where the winding connected to the top

capacitor (i.e. capacitor with higher voltage) has twice as many turns as the one connected to the

bottom capacitor. The current of the top winding is controlled by the transistor Qd1 and of the

bottom by Qd2.The output voltage of the downstream stage is regulated with its own controller

that produces pulse width modulated signal cd(t), which is passed to the centre-tap regulator

through an optocoupler. The centre-tap regulator sends cd(t) either to Qd1 or to Qd2, creating

signals cd1(t) and cd2(t) respectively, as shown in Fig. 4.15. The two signals are sequenced such

that the centre tap voltage is kept at Vbus/3 level. To achieve this, the centre tap voltage is

compared with three times attenuated bus voltage using two comparators (Fig. 4.14) whose

outputs are connected to the block named switch selection logic. The switch selection logic (Fig.

89

cd(t)

Hdvout(t)

Hd

H H

sync1

Dd1

Dd2

loa

d+

vout

_

Cout

n3

n2

Dd3

Ld

Qd1

2n1

n1

i1

i2

+

_

+

_

2Vbus/3

Vbus/3

C

2C

vct(t)

vtop(t)

Qd2

S&H S&H

sync2

R1

+

Switch selection

logic

cd2(t)cd1(t)

cdi(t)

Centre tap voltage regulator

R2

R3

_

+_HVbuss/3+v

HVbuss/3-v

OptocouplerDownstream stage

controller

Cmp1

Cmp2

h

l

Figure 4.14: Centre tap voltage controller regulating operation of a forward based downstream

stage.

4.14) implements the charge-balancing algorithm presented in [32], to keep the capacitors

voltages regulated.

When the centre tap voltage is inside regulation band Vbus/3 vct, where vct is the allowable

centre tap voltage variation, the switch selection logic alternates the signal cd(t) between Qd1 and

Qd2 after each switching cycle of the downstream converter. As a result equal voltage drops

across both capacitors occur as shown in Fig. 4.15, since a two times larger charge (i.e. current)

is taken from the bottom capacitor having twice the capacitance value.

90

cd

t

t

dTsw_d

Tsw_d

t

dTsw_d

cd1

i1

t

t

cd2

i2

Ip

2Ip

Figure 4.15: Key waveforms of the centre-tap voltage regulator (from top to bottom): cd(t) –

pulse width modulated signal of the downstream stage controller; cd1(t) – control signal for Qd1;

cd2(t) – control signal for Qd2; i1(t) – discharging current of the top capacitor of the NSMB; i2(t) –

discharging current of the bottom capacitor of the NSMB.

If the centre tap voltage exceeds the regulation band, comparator cmp1 is activated and the

regulation sequence is modified, such that the discharging of the top capacitor is skipped for

several cycles, until the centre tap voltage is reduced to Vbus/3 level. Similarly, if the centre-tap

voltage drops below Vbus/3 - vct, the comparator cmp2 is triggered and the discharging of the

bottom capacitor is interrupted for several cycles.

91

4.3.4 Design Tradeoffs

By comparing the practical implementation of the NSMB to that of the conventional boost

solution [23] it can be seen that a design tradeoff is involved. The NSMB requires a larger

number of components (the same as 3-level solutions), high side gate drivers, more complex

control, and a non-conventional downstream stage. The following section showing experimental

results demonstrates that in terms of the total volume and power processing efficiency this design

is favorable in the targeted applications, providing 100 W to 500 W of power and operating at

switching frequencies in the range of 100 kHz to 200 kHz. There the inductive components and

heat sinks are by far the largest contributors to the overall volume and the weight of the

converter. The experimental validation shows that the NSMB has significantly better power

processing efficiency and lower volume than the single phase and interleaved boost-based

solutions, which are predominantly used in the applications of interest.

Also, the capacitive divider at the output of the NSMB allows for a reduction of the volume of

the downstream stage and potentially, improving the efficiency of the downstream stage

converter.

Therefore, it can be envisioned that the advantages of the NSMB can potentially be fully utilized

in a system where multiple semiconductor components would be integrated on a semiconductor

chip and optimally sized, in terms of blocking voltage and conducting current. Such an

implementation on a dedicated IC would probably not only result in a reduction of the number of

components but also, as described in the following section, in further efficiency improvements,

due to smaller parasitic capacitances and resistances of the components.

92

4.3.5 Extension to Higher Power Levels

The NSMB configuration of Fig. 4.1 is primarily designed for the PFC applications below 500

W. In order to utilize the converter for higher power ratings, where the conductions losses are

becoming dominant, concept of interleaving, widely used with the conventional solutions [13],

[25] could potentially be applied here as well. In this case, multiple single-phase NSMB

converters, each followed by an isolated DC-DC converter could be connected in parallel.

For the PFC applications exceeding 1 kW, where, as demonstrated in [17], [45], the diode

rectifier significantly degrades power processing efficiency, the bridgeless modification of the

NSMB, shown in Fig. 4.16 could potentially be used. The transformation of the converter into its

bridgeless version is performed using the principles demonstrated in [17], [45], [46]. Validation

of potential advantages of the modified NSMB topologies over the conventional solutions would

require further investigation and are beyond the scope of this paper.

L

iac(t)

C1

2C1

SW1

SW2D2

+

2Vbuss/3_

+

_

D1

+

_

vline(t)

Vbuss/3

SW3

SW4

D3

SWa1

SWa2

Figure 4.16: Bridgeless NSMB converter topology.

93

4.4 Experimental System and Results

To validate the operation of the introduced non-symmetric boost based PFC rectifier, a universal-

input 400 W, 200 kHz experimental prototype was built, based on the diagrams of Figs. 4.1, 4.9,

4.10, 4.11 and 4.14. Also, its performances are compared to that of a conventional boost-based

PFC prototype and a three level boost converter [6], having the same effective switching

frequency, seen by the inductor, and output power rating. Similar to validation procedures

presented in [17]-[21] the comparison of the NSMB is performed with the conventional boost, in

order to assess the sole effect of the new topology on the performance improvements and to be

able to directly compare it with other performance improving solutions. The boost converter is

designed such that it has performance comparable to similar industrial solutions operating at the

same switching frequency [47]. The parameters of the both converters are given in Table 4.1. It

should be noted that the table confirms that the NSMB has three times smaller inductor volume

and, as described in Section 2.a, the total volume of the output capacitors, which is proportional

to their energy storage capacity, in both cases is approximately the same.

Table 4.1: Comparison of NSMB Converter Parameters with Boost and 3-level PFC

Vout Pout fsw Output capacitor(s) Inductor Inductor volume

Boost PFC 400 V 400 W 200 kHz C=100 F (420 V) L= 670 H 44.1 cm3 [48]

NSMB

PFC

400 V 400 W 200 kHz Ctop =150 F (300 V)

Cbottom=300 F (150 V)

L= 220 H 14.5 cm3 [49]

3-level

boost PFC

400 V 400 W 200 kHz Ctop =220 F(220 V)

Cbottom=220 F (220 V)

L= 330 H 24.8 cm3 [50]

94

The controller was built using an FPGA-based development board and the power stage is created

using discrete components. In this discrete implementation the switching components for the

NSMB are not optimized and are the same as those of the conventional system.

Figures 4.17 to 4.20 show the key current and voltage waveforms of the conventional and the

NSMB boost converters for 220 Vrms and 90 Vrms line inputs. By comparing the switching node

voltage swings it can be seen that the NSMB, has about three times smaller voltage swing vx =

Vswing for both operating conditions. To demonstrate the effect of the reduced swing on the

Hvbus(t)

vx(t)Vswing= 400 V

zoom

vin(t)

iL(t)0.375 A




line voltage, vin(t) (200 V/div). Time scale is 1 ms/div. Operating conditions: vline = 220 Vrms,

Vbus = 400 V, Pout = 100 W, C = 100 F , L = 680 H.

95

inductor current ripple and confirm the analysis from Section 2, only in this set of measurements,

the NSMB has the same inductor value as the conventional boost (of approximately 670 µH), for

other measurements NSMB operates with 3 times smaller inductor. A comparison of the ripples

(zoomed waveforms in Figs. 4.17 and 4.18) shows that the NSMB has about three times smaller

ripple allowing for the equal reduction of the inductor value. The waveforms of Fig. 4.18 also

demonstrate stable operation of the NSMB. It can be seen that the controller seamlessly changes

the NSMB mode of operation when the input voltage exceeds or drops below Vbus/3 and 2Vbus/3

values, which for the experimental system are 133.3 V and 266.6 V, respectively.

Hvbus(t)

mode 1

vx(t)

vin(t)

iL(t)

mode 2mode 3

mode 2 mode 1

zoom

133.3 V

266.6 V

0.125 A

133.3 V

Figure 4.18: Key waveforms of the NSM-based PFC rectifier; top to bottom: Ch.1 (top):

attenuated output voltage, Hvbus(t) (2 V/div); Ch.2 (upper middle): switching node voltage, vx(t)

(200 V/div); Ch.3 (lower middle): input line current, iL(t) (0.5A/div); Ch.4 (bottom): input line

voltage, vin(t) (200 V/div). Time scale is 1 ms/div. Operating conditions vline = 220 Vrms, Vbus =

400 V, Pout = 100 W, Ctop = 150 F, Cbottom= 300 F , L = 680 H.

96

Zoomed in transition waveforms are also shown in Fig. 4.21. These waveforms demonstrate

effectiveness of the applied mode transition method based on the PI compensator re-

initialization, described in Section 3. It can be seen that at the transition points, the duty ratio

changes from the maximum value to zero (reducing the swing of inductor voltage to zero as

well). By looking at the waveforms of the both converters a slight current waveform distortion

can be noticed. The distortion occurs due to the quantization effects and the loss of the gain of

the current measurement ADC at low inputs [51]. When the input becomes smaller than the

Hvbus(t)

vx(t)Vswing= 400 V

zoom

vin(t)

iL(t)

0.375 A





= 400 V, Pout = 100 W, C = 100 F , L = 680 H.

97

quantization step of the used 6-bit ADC its gain, and consequently the overall gain of the system,

reduces causing distortion of the current waveform. For high-end applications, where a very low

harmonic distortion is required, a higher resolution ADC can minimize this potential drawback.

Fig. 4.22 illustrates regulation of the output capacitor voltages with a downstream converter

stage with a 70 W output load. The downstream stage operates at 200 kHz switching frequency.

It can be seen that, both capacitors maintain stable voltages and that, during each cycle the

Hvbus(t)

vx(t)

vin(t)

iL(t)

mode 1

zoom

127.3 V

0.125 A

Vswing= 133 V





= 400 V, Pout = 100 W, C = 100 F , L = 680 H.

98

c1(t)

vx(t)

vin(t)

d(t)=0

d(t)Ts

iL(t)

mode 1 mode 2

vx =Vbus/3

c2(t) d(t)≈ 1

Mode_signal

vx(t)

vin(t)

iL(t)

mode 2

d(t)Ts

mode 3

vx

d(t)=0 d(t)≈ 1

Mode_signal

Figure 4.21: Transitions from mode 1 to mode 2 (top) and from mode 2 to mode 3 (bottom);

Ch.m1(top): input line voltage, vin(t) (200 V/div); Ch.2 (upper middle): switching node voltage,

vx(t) (200V/div); Ch.4 (middle): gating signal of SW1, c1(t) (20 V/div); Ch.1 (lower middle):

gating signal of SW2, c2(t) (20 V/div); Ch.3 (bottom): input line current, iL(t), (0.5 A/div); digital

input: mode control signal (0 = mode 1, 1 = mode 2, 2 = mode 3). Time scale is 5 s/div.

Operating conditions vline = 220 Vrms, Vbus = 400 V, Pout = 100 W, Ctop = 150 F, Cbottom = 300

F, L = 230 H.

99

charge taken from the bottom capacitor is twice as large as that taken from the top. As described

in Section 3.d, this results in equal voltage drops across both capacitors. It should be noted that,

as it can be seen from Fig. 4.20, at low line inputs the converter mostly operates in mode 1 (or

modes 1 and 2) causing most of the power to be transferred through the bottom portion of the

downstream stage of Fig. 4.14. To handle these conditions the transistor and the winding on the

bottom primary side of the converter need to be designed such that thy can provide the full load

power. This drawback is completely compensated by the fact that the transistor of the down-

Hvtop(t)

Hvct(t)

i1(t)

i2(t)

i1(t)

i2(t)

Figure 4.22: Capacitor taps voltage regulation with the downstream stage currents; top to bottom:

Ch.1 (top): top capacitor voltage, vupper(t) (100 V/div); Ch.2 (upper middle): bottom capacitor

voltage, vbottom(t) (100V/div); Ch.4 (lower middle): discharging current of bottom capacitor, i2(t)

( 1 A/div); Ch.3 (bottom): discharging current of top capacitor, i1(t), (1 A/div);. Time scale is 2

s/div. Operating conditions vline = 220 Vrms, Vbus = 400 V, Pout = 70 W, Ctop = 150 F, Cbottom =

300 F, L = 230 H.

100

stream stage operates at a three times smaller voltage than that of the conventional downstream

solutions [2], [52]-[53], where most of the losses at the primary side of the converter are caused

by high voltage stress of the transistors.

Power quality and total harmonic distortion for both converters are also experimentally

compared, by extracting the current waveform data from the oscilloscope. In order to capture

accurate information about the inductor currents, the harmonics are measured without an input

filter regularly existing in the applications of interest.

In both cases the power factor is measured to be about 0.98. The harmonic contents for both

converters are shown in Fig. 4.23. It can be seen that the both converters have similar spectrums.

The measurements also show that, similar to 3-level solutions [7], [9], [12], the NSMB has

slightly lower total harmonic distortion (THD) 14.03% vs. 15.48%. It should be noted that with

the use of an input filter the THD values should be significantly smaller. The lower THD of the

NSMB is mostly due to the lower energy of harmonics at the switching frequency and multiple

regions of operation with close to zero inductor current ripple, as shown in Fig. 4.21.

Figures 4.24 and 4.25 show efficiency comparison results for a conventional boost, a three-level

boost and NSMB converters operating with 85 Vrms and 265 Vrms input voltages, respectively. In

this case the boost PFC has power processing efficiency comparable to the commercial solutions

operating at the same switching frequency [47]. The efficiency comparison experiments are

conducted for all converters operating at the same 200 kHz effective switching frequency. It can

be seen that, mainly due to the reduction of switching losses, the introduced NSMB-PFC has up

to 10% better power processing efficiency than the boost converter and up to 4% than the three

101

101

102

103

0

0.9

0.95

1

0

0.05

0.1

0.15

0.85

≈

105

106

≈

≈

≈ ≈ N

orm

ali

zed

harm

onic

am

pli

tud

es

Frequency (Hz)

NSMB

101

0

0.9

0.95

1

0

0.05

0.1

0.15

0.85

≈

≈

≈

≈

105

106

≈

102

103

Frequency (Hz)

Norm

ali

zed h

arm

onic

am

pli

tudes

Conventional boost

Figure 4.23: Amplitudes of harmonics (multiples of 50 Hz) around line frequency and the

switching frequency for the NSMB-based PFC prototype (top) and the conventional boost based

prototype (bottom).

level PFC. The efficiency improvements can be seen throughout the whole operating range,

where, as expected, at light and medium loads, where the switching losses are dominant, the

improvements are more noticeable.

102

80

82

84

86

88

90

92

94

96

98

0 100 200 300 400

NSMB

BOOST

Three_Level

Eff

icie

ncy

(%

)

Output Power (W)


converters for the line input of 265 Vrms.

79

81

83

85

87

89

91

93

95

97

0 50 100 150 200 250 300 350 400

NSMB

Boost

Three_Level

Eff

icie

ncy

(%

)

Output Power (W)


converters for the line input of 85 Vrms

103

It should be noted that in all prototypes the same switching components (Infineon

IPB60R280C6CT Cool MOS switches [54] and STTH10LCD06 diodes from

STMicroelectronics [55], the maximum voltage rating of all components in this case is 600 V)

were used, due to limited selection of semiconductor switching components rated for the

required blocking voltages of the NSMB. Therefore, the design has not been optimized for the

NSMB topology. Still, the obtained efficiency results are comparable or better than those

obtained in the state of the art solutions operating at the same switching frequency [26].

Figures 4.26 and 4.27 compare the loss break down analysis for the boost, three level and NSMB

converters. The loss analysis results are shown for operation with input voltage of 265Vrms and

85Vrms for two cases of light (Fig. 4.26) and heavy (Fig. 4.27) loads for each converter. Each bar

in these figures shows the normalized losses from different contributors to the overall losses of

the corresponding converter and operating conditions.

It is also worth mentioning that most efficiency optimization techniques and volume reduction

methods developed for the conventional boost-based PFC topologies can be applied to the

NSMB as well. Those include utilization of super junction and SiC devices [18], variable

frequency control [19], separate light load control scheme [20], [21], and utilization of soft

switching techniques [17]. For example, a soft-switched NSMB converter can be implemented

employing the ZVT circuit presented in [6]. This means that, in the NSMB, the benefits of all of

these complementary methods can be utilized while maintaining advantages of the smaller

inductor and lower voltage stress over the conventional solutions.

In the targeted cost-sensitive applications (below 500 W) the use of a bridgeless topology is

http://www.st.com/web/en/resource/technical/document/datasheet/CD00238067.pdf

104

0

0.2

0.4

0.6

0.8

1

Boost

265Vrsm

Three level

265Vrsm

NSMB

90Vrsm

Boost

90Vrsm

Three level

90Vrsm

NSMB

265Vrsm

13.5

26.0

3.3

9.3

15.0

46.0

2.9

22.4

17.4

31.8

3.2

17.9

12.8

21.2

8.4

5.1

25.1

58.9

6.6

9.5

26.5

27.3

8.6

6.6

Switching losses

Core losses

Diode bridge losses

Conduction losses



(50W). Length of each bar is normalized based on the losses of the boost at 90Vrms which is

9.8W.

usually avoided [13], due to increased price and fairly limited relative improvements in the

power processing efficiency. This can be demonstrated by looking at the loss breakdown shown

in Figs. 4.26 and 4.27. It can be seen that the diode bridge losses of the NSMB converter are a

small portion of the overall losses at light loads (8.4%) and increase at heavy loads, to 9.8%. The

heavy load results indicate that for, higher power applications which are beyond the scope of this

work, the diode rectifier losses become more dominant and that the use of the bridgeless

solution, shown in Fig. 4.16, is fully justifiable.

As mentioned before, in a potential implementation with custom-designed silicon components

even larger efficiency gains could be expected. This would mostly be due to the further reduction

105

Boost

265Vrsm

Three level

265Vrsm

NSMB

90Vrsm

Boost

90Vrsm

Three level

90Vrsm

NSMB

265Vrsm

Switching losses

Core losses

Diode bridge losses

Conduction losses

29.1

14.7

7.6

2.7

24.3

23.0

5.7

5.5

28.2

16.5

6.0

4.3

53.3

10.0

9.8

0.8

63.0

27.5

7.9

1.5

61.8

15.3

10.2

1.1

0

0.2

0.4

0.6

0.8

1N

orm

aliz

ed L

oss

es



(350W for 85Vrms and 400W for 265Vrms). Length of each bar is normalized based on the losses

of the boost at 90Vrms , which are 50.5W.

of switching losses, caused by increased transistor speed and reduced values of parasitic

capacitances of the semiconductor components.

The diagrams of Fig. 4.28 compare the volume breakdown between different components and

total normalized volumes of the conventional boost PFC, a two-phase interleaved boost based

PFC [26], a three level PFC [6], and the introduced NSMB-based solution for typical 300 W to

400 W applications [25], [26], [47]. The diagrams also show volume comparisons for potential

optimized implementations of the interleaved boost and NSMB, where the silicon switches

would be sized in accordance with their power ratings and implemented in a single package. As

described in Appendix A.1, such an optimized implementation would require the same silicon

106

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Inductor

Output capacitor

Semiconductor

Heatsink

Controller

0.01

Conventional

boostInterleaved

Interleved with

optimized switches

Norm

aliz

ed v

olu

me

0.40

0.30

0.04

0.26

0.01

0.01

0.26

0.30

0.06

0.21

0.26

0.30

0.04

0.21

0.810.83

Three level Three level With

optimized switchesNSMB

0.06

0.13

0.30

0.21

0.01

0.70

NSMB with

optimized siwtches

0.01

0.13

0.30

0.21

0.04

0.69

0.01

0.20

0.30

0.22

0.780.01

0.20

0.30

0.22

0.76

0.040.06

Figure 4.28: Normalized volume distributions of conventional boost-based PFC and three other

solution. In case of the latter three cases, a volume break down in case of implementation with

optimal switches, i.e. lower voltage/current rated switches in single package, is also shown.

area as the conventional boost. It should be noted that in these comparisons the input filter,

whose volume significantly depends on the printed circuit board (PCB) layout is not taken into

account. However as indicated in the analysis of Section 4.2.1, the required volume of the

NSMB input filter is smaller than that of the other analyzed solutions.

It can be seen that compared to the conventional boost, the NSMB has about 30% smaller total

volume and is about 15 % smaller than the interleaved boost, which as shown in [25], has about

32% smaller inductor than the conventional boost. The volume comparison results confirm

discussions of the favorable tradeoff from the previous sections. Since in the conventional boost

a large portion of the volume of is occupied by the inductor and the heat sink, about 65%, and

less than a 5% by the semiconductors, a Trade-off between the inductor reduction and efficiency

107

improvement on one side and an increase in the semiconductor part numbers on the other side is

favorable. In this the semiconductor components include the diode bridge, which in the

conventional boost takes about 50% of the total silicon area, the diode and the transistor, which

take the other 50%. The results show that the three times reduction in the inductor volume and

about a 12% in the heat sink volume, which is proportional to the heat dissipation reduction, are

more than compensating for about 50 % increase in the semiconductor switch volume and a 60%

increase in the volume in the controller size. In this case the size of the controller is estimated by

looking at the volume of analog components and the number of logic gates required for its

implementation for all three cases.

4.5 Conclusions

In this Chapter, a PFC rectifier based on a novel digitally-controlled non-symmetric multi-level

boost converter (NSMB) converter that requires three times smaller inductor and has lower

losses than the conventional boost based solution is introduced. The NSMB is a modified version

of the three-level boost topology. Instead of maintaining the same voltages across the output

divider capacitors, in this system, they are regulated at 1/3 and 2/3 of the full output level. This

modification allows for a further reduction of the inductor voltage swing and, consequently, its

minimization. To regulate the centre-tap voltage, input current of a two-input low-volume

downstream converter stage is utilized. Experimental comparisons with a conventional PFC

verify advantages of the new system.

108

4.6 References

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[5] D. Maksimovic, R. Erickson, "Universal-input, high-power-factor, boost doubler rectifiers,"

in Proc. IEEE APEC '95, pp.459-465 vol.1






[8] D. Damasceno, L. Schuch, J.R. Pinheiro, "Design Procedure to Minimize Boost PFC Volume

Concerning the Trade-offs Among Switching Frequency, Input Current Ripple and Soft-

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[9] Bor-Ren Lin, Tsung-Yu Yang, "Single-phase three-level converter for power factor

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[10] H. Keyhani, H.A. Toliyat, "Flying-capacitor boost converter," in Proc. IEEE APEC 2012,

pp. 2311-2318.





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continuous-inductor-current mode," in Proc. IEEE APEC '93. pp.168-174.

109

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[19] F. Chen, D. Maksimović, "Digital Control for Improved Efficiency and Reduced Harmonic

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[24] M.M. Jovanovic, J. Yungtaek, "State-of-the-art, single-phase, active power-factor-correction

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Instruments Seminar, http://www.ti.com/download/trng/docs/seminar/Topic5MO.pdf

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110

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Suitable for On-Chip Implementation," In Proc. PCC '07 , pp.1527-1531.

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[35] A.H. Mitwalli, S.B. Leeb, G.C. Verghese, V.J. Thottuvelil, "An adaptive digital controller

for a unity power factor converter ," IEEE Trans. on Power Electron., vol.11, no.2, pp.374-382,

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DC SMPS," IEEE Trans. on Power Electron., vol.23, no.1, pp.500-505, Jan. 2008.

[37] A. Prodic, D. Maksimovic, R.W. Erickson, "Design and implementation of a digital PWM

controller for a high-frequency switching DC-DC power converter," In Proc. IEEE IECON '01,

vol.2, no., pp.893-898 vol.2.

[38] D.M. VandeSype, K. DeGusseme, F.M.L.L DeBelie,A.P. VandenBossche, J.A. Melkebeek,

"Small-Signal -Domain Analysis of Digitally Controlled Converters," IEEE Trans.on Power

Electron., vol.21, no.2, pp.470-478, March 2006.

[39] Z. Zhenyu; A. Prodic, P. Mattavelli, "Self-Programmable PID Compensator for Digitally

Controlled SMPS," in Proc. IEEE COMPEL '06. pp.112-116.

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Instruments , Dallas, USA, Application Report SLVA307, August 2008.

111

[44] Kislovski, A.S., "Fast active inrush current limiter for boost-based resistor emulators," In

Proc. INTELEC '94., pp.649-652.

[45] F. Musavi, W. Eberle, W.G. Dunford, “A High-Performance Single-Phase Bridgeless

Interleaved PFC Converter for Plug-in Hybrid Electric Vehicle Battery Chargers, “ IEEE

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[46] D.M. Mitchell,"AC-DC Converter having an improved power factor", U.S. Patent

4,412,277, Oct. 25, 1983.

[47] M. Scherf, W. Frank, “200W SMPS Demonstration Board II,” Infineon Technologies,

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[48] “CTX-10 Series Low-Cost Power Inductors, ” Cooper Bussmann, Chicago, USA,

Datasheet, 2007.

[49] “PCV-2 Inductor Series,” Coilcraft, Datasheet, Cary, USA, 2014.

[50] “CTX-16-17769 inductor, ” Cooper Bussmann, Chicago, USA, Datasheet.

[51] H. Peng; D. Maksimovic; A. Prodic; E. Alarcon, "Modeling of quantization effects in

digitally controlled DC-DC converters," In Proc. IEEE PESC 04, vol.6, pp.4312-4318.

[52] J. Sebastian, P. Villegas, F. Nuno, M.M. Hernando, "Very efficient two-input DC-to-DC

switching post-regulators,"in Proc. IEEE PESC'96, pp. 874-880, 2006.

[53] G. Spiazzi, "Analysis of buck converters used as power factor pre-regulators," in Proc. IEEE

PESC '97, pp.564-570, 1997.

[54] “IPx65R660CFD CoolMOS CFD2 Power Transistor, ” Infenion Technologies AG,

NEUBIBERG, GERMANY, Datasheet, 2011.

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112

Chapter 5

Conclusions and Future Work

This thesis presents two new switched mode power supply topologies that further minimize the

volume of state of the art converters with large input-to-output voltage ratio while improving

their efficiency. The two converter topologies introduced in this dissertation provide low-volume

high performance solutions for two major applications, namely for multi-phase high-step down

converters used in point of load applications and for boost-based rectifiers with power factor

113

correction (PFC). In the following sections, the thesis main contributions are summarized and

possible extensions of this work are discussed.

5.1 Digitally Controlled Multi-Phase Buck-Converter with Merged

Capacitive Attenuator

5.1.1 Conclusions

The 2-stage digitally controlled converter that merges a switch capacitor converter (SC) with an

interleaved buck is introduced in Chapter 3 The new converter improves the power density of

multi-phase step-down converters while improving efficiency. The size reduction is obtained

with a low penalty in conduction losses, input filter size, and controller complexity. Through

utilization of buck inductors for SC tap balancing, the new converter eliminates a bulky energy

transfer capacitor existing in other 2-stage solutions combining a SC and inductive based

converters. The utilization of inductors for centre tap balancing also reduces the number of

switches in conduction path, reducing conduction losses and controller complexity. To minimize

switching losses of the SC stage a quasi resonant switch is employed. At heavy loads the

efficiency of the MSCB is comparable to the conventional buck and at light and medium loads it

is improved. Furthermore, the merged topology has a larger inductor current slew rate resulting

in a significantly faster transient response allowing for the output capacitor reduction. This is

achieved by reduction of inductor size and, at the same time, utilizing full range of input voltage

during light to heavy load transients.

114

The effectiveness of the MSCB is verified experimentally through comparisons with a

conventional multi-phase buck, where the improvements in efficiency, reduction of the buck

inductors and output capacitor volumes, and faster dynamic response are demonstrated.

5.1.2 Future Work

Future work could include development of a controller that performs current sharing between

two MSCB buck phases based on their conduction losses, which is dominant source of losses,

instead of equal current sharing. That would lead to achieving similar temperature among two

phases, which can improve system reliability and prevent failures [1]. For the MSCB converter,

this can be done remotely without requirement for any additional current sensing or temperature

sensing circuits. This is because the information regarding the mismatch in losses between two

phases can be observed from the voltage mismatch between two input capacitors as shown by

Eq.3.6. Therefore, by sensing voltages across the input capacitors, controller can adjust duty

cycle for two buck phases such that similar temperature between two buck phases are obtained.

The input filter used for the MSCB converter in this work is similar to that of a conventional 2-

stage interleaved buck solutions. The soft charging of SC stage in the MSCB could potentially

relax the input current filtering requirements compared to existing 2-stage solutions with front

SC stage. Analytical design of the input filter and evaluation and of its performances for the

MSCB converter and its comparison to those of other existing topologies can be another subject

of future work.

115

The IC implementation that integrates the power stage switches of the MSCB converter is

another potential subject of future research. The IC implementation could fully utilize the

benefits of the MSCB converter, since it would allow for design of optimized switches and gate

drivers with better figures of merit than the existing discrete solutions.

5.2 Low-Volume PFC Rectifier Based On Non-Symmetric Multi-

Level Boost Converter

5.2.1 Conclusions

A rectifier with power factor correction based on a novel non-symmetric multi-level boost

converter (NSMB) and a complementary digital controller are introduced in Chapter 4. In

comparison with the conventional boost-based solutions, the NSMB has three times smaller

inductor as well as reduced switching losses. These advantages are achieved by reducing the

inductor, i.e. switching node, voltage swing to 1/3 of the conventional boost level. At the same

time, the voltage stress across the switching components is reduced to 1/3 for one diode-

transistor pair and to 2/3 for the other pair.

The NSMB is a modified version of the conventional three-level boost topology [2]. Instead of

having the same voltages across the output divider capacitors, this modification uses a non-

symmetric capacitor divider and the capacitor voltages are regulated at 1/3 and 2/3 of the full

output voltage level. As a result a 4-level operation is achieved reducing the inductor by 33%

(compared to that of the conventional solution) without increasing the number of components

required for the implementation.

116

To control the capacitor voltages of the nonsymmetrical divider without using a bulky flying

capacitor, the idea introduced in the previous chapter is again utilized. In this case an isolated

downstream converter is used to provide centre tap voltage regulation. In regular operation, the

downstream stage takes non-equal amounts of charge from the capacitors keeping the capacitors

voltage drops equal during discharging phases. The downstream converter stage has two inputs

and, similar to the NSMB, can utilize principles of the reduced voltage swings to obtain smaller

volume of magnetic components and reduced switching losses.

The mixed signal controller dynamically changes modes of the NSMB operation, depending on

the instantaneous input voltage value. Seamless transitions between 3 operating modes are

provided through the digital PI compensator re-initialization process, where depending on the

type of transition, the new and previously stored values of duty ratio are set to 0 or to their

maximum values. To eliminate the need for differential capacitor voltage measurements, a

switching state dependent sampling and hold technique is applied.

Results obtained with an experimental prototype verify that the NSMB converter requires a three

times smaller inductor and has up to 10 % better power processing efficiency. The results also

demonstrate stable controller operation and seamless mode transitions.

It is important to note that the presented principle of the use of a non-symmetric voltage divider

to create a 4-level converter using 3-level hardware could potentially also be used in 3-level dc-

ac converter applications to reduce the volume of the inductive components.

117

5.2.2 Future Work

The introduced boost-based converter topology utilized for ac-dc applications, can also be

potentially operated as a multi-level dc-ac inverter based on the same operation principles as

shown in [3]. The design and implementation of the NSMB-based inverter could be an

interesting subject for future work.

In Chapter 4, a bridgeless variation of the NSMB converter is proposed. Implementation of the

bridgeless NSMB converter could result in improved power processing efficiency at heavy loads

by reduction of diode bridge losses.

In order to fully utilize the advantages of the NSMB converter, an IC integration of the switching

components and controller is required. The integrated version of the NSMB converter can benefit

from reduced die area for switches, lower parasitic losses and electromagnetic interference

(EMI). Also further efficiency improvements can be potentially be achieved by utilizing lower

voltage rated switches.

118

5.3 References

[1] Z. Lukic,A. Stupar, A. Prodić,D. Goder, "Current estimation and remote temperature

monitoring system for low power digitally controlled DC-DC SMPS," In Proc. IEEE PESC

2008, pp.1139-1143,June 2008



[3] Meynard, T.A. and H. Foch, “Multi-level conversion: high voltage choppers and voltage-source

inverters,” in IEEE Proc. PESC '92, 1992.

119

Appendix A

Analysis of Conduction losses for optimized design of

switching components

The following analysis compares conduction losses of the NSMB converter introduced in

Chapter 4 to those of conventional boost PFC. The comparison is based on the assumption that

the semiconductor components of the both converters are sized in accordance with their voltage

ratings.

120

A.1 Analytical comparison of Conduction losses

The conduction losses corresponding to the boost PFC converter can approximately be described

with the following equation [1]:

dtt D't i V +t D ti R+ti R=P boostLFT

0 boost2Lon

2LLboostboostcond,

L )]()()()()([ , (A1)

where TL is time duration of a half line cycle, iL(t) is the inductor current, RLboost is a resistance

that models copper inductor losses, Ron is the on resistance of the transistor, VF is the diode

forward voltage drop and Dboost is the boost converter duty cycle.

For the NSMB converter, due to the change of conduction path based on the converter operating

mode (shown in Figs. 4.3 to 4.5), the losses are described with three different equations,

corresponding to three distinctive modes of work.

dtt D't i VtiR+t D tiRR+ti R=P NSMB,1LF22Lon,1

TNSMB,1

2Lon,2on,1

2LLNSMBNSMB,1cond,

1

)]() )()(( )()()()([ , (A2)

dtt D't i VtiR +tD t i VtiR+ti R=P NSMB,2LF12Lon,2

TNSMB,2LF2

2Lon,1

2LLNSMBNSMB,2cond,

2

)]() )()(()() )()(()([ , (A3)

dtt D't i Vti VtDt i VtiR+ti R=P NSMB,3LF2LF1T

NSMB,3LF12Lon,2

2LLNSMBNSMB,3cond,

3

)]() )()( ()( ) )()(()([ , (A4)

where Ti represents the time converter operates in mode i during a half of line cycle, RLNSMB is

equivalent resistance of the NSMB inductor modeling its core and copper losses, Ron is the on

resistance of Qi, VFi is forward voltage drop of the diode Di, and DNSMB,i corresponds to the duty

ratio of the NSMB converter during mode i.

The total conduction losses can be found as the sum of the previous three equations:

121

NSMB,3cond,NSMB,2cond,NSMB,1cond,NSMBcond, PPP=P , (A5)

By utilizing volt-second balance [1], the following relations between duty cycles of the boost and

the NSMB can be found:

2-t 3Dt D boostNSMB,1 )()( (A6)

1-t 3Dt D boostNSMB,2 )()( (A7)

)()( t 3Dt D boostNSMB,3 . (A8)

Assuming that area used for implementing the transistors of the NSMB is the same as that

needed for the boost transistor and taking into account that the on resistance of a power a mosfet

per unit silicon area is given by [2]

2

_ . Bspon VR , (A9)

where α is a process-dependent constant and VB is the breakdown voltage, the following relations

between the on resistances of the mosfet resistances can be found:

onon,1 R9

4R

(A10)

onon,2 R9

1R

, (A11)

where Ron is the resistance of the boost transistor and Ron,1 are Ron,2 are the resistances of the

NSMB. The equations are obtained by taking into account that the blocking voltages of Q1 and

Q2 are a 66% and a 33% of that of the boost transistor, respectively.

122

By substituting equations A6 to A8 and A10-A11 into Eq.A2-A4 and then A2-A4 into A5 and

assuming that the forward voltage drops of all diodes are the same, the following relation

between the conduction losses of the two topologies is obtained:

L

1

1

T

LLNSMBLboost

T3

2

Lonboost

T2

2

Lon

T

2

Lonboost

T3

LboostFF

T2

LboostF

T

Lboost'

Fboostcond,NSMBcond,

ttiRR

tdt iRtD3

dtt iR9

dtt iR)9

tD3

dtt itDVV dtt itDVdtt itDVP=P

0

2 )d( )-(

)()(2

)(2

)(2

-)(2

(

)()](2[)()()()(2

, (A12)

The results show that the diodes losses of the NSMB are slightly higher. The value of the diode

losses depends on the input voltage level, i.e. on the portions of time the NSMB spend in each

mode of operation. However, these extra losses can be partially or completely compensated by

the smaller transistor conduction losses and also smaller inductance of the NSMB resulting in

lower copper and conduction losses.

A.2 References



[2] B. J. Baliga, Fundamentals of Power Semiconductor Devices. NewYork, NY: Springer, 2008.

hybrid sc-i b t l -v h efficiency switched … buck and boost converter topologies due to their...

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