Hybrid Silicon Photonics Flip-Chip Laser Integration with Vertical Self-Alignment

A. Moscoso-Mártir1, F. Merget1, J. Mueller1, J. Hauck1, S. Romero-García1, B. Shen1, F. Lelarge2, R. Brenot3, A. Garreau3, E. Mentovich4, A. Sandomirsky4, A. Badihi4, D. E. Rasmussen4, R. Setter4, J. Witzens1*

1RWTH Aachen University, Institute of Integrated Photonics, Sommerfeldstr. 24, Aachen, 52074 Germany 2Now with Almae Technologies SAS, Route de Nozay, Marcoussis, 91460, France

3III-V Lab, Campus de Polytechnique, 1 av. Augustin Fresnel, Palaiseau, 91767, France 4Mellanox Technologies, Hakidma 26, Ofer Industrial Park, Yokneam, Israel

* jwitzens@iph.rwth-aachen.de

Silicon Photonics (SiP) development is motivated by the realization of large-scale and low-cost photonic integrated circuits (PICs), owing to its compatibility with very mature and highly accurate CMOS fabrication technology. However, fabrication and integration of efficient laser sources on SiP remains a challenge. Some of the more prominent solutions that have been implemented in the last years are: i) integration of external laser sources packaged in a photonic micro-bench using active alignment [1,2], ii) heterogeneous integration [3] and hybrid integration based on flip-chip attachment [4-7]. Active alignment has been proven to be a valid solution for commercial products, however the involved laser optical bench requires additional piece parts and assembly steps. Moreover, the final package is significantly larger than the laser die, so that it may also limit the scaling of the integration density. Heterogeneous integration can very significantly relax the required placement accuracy, since laser processing can be done after permanent attachment of the III-V die on the SiP chip, and also allows for higher integration densities. Moreover, transfer printing is actively investigated as a means to increase the associated manufacturing throughput [8]. However, heterogeneous integration also raises the issue of the introduction of III-V materials into the front-end of a Silicon chip fabrication facility and requires customized manufacturing processes that are not directly compatible with standard CMOS technology. Moreover, heat sinking of the laser is also limited by the high thermal resistance of the buried oxide (BOX) interposed between the laser and the Silicon wafer handle, unless additional engineering is done to allow direct thermal contact between the laser and the substrate [9]. Hybrid integration based on flip-chip attachment on the other hand allows for independent fabrication and test of laser and SiP chips, reducing constraints on the semiconductor manufacturing process flow and allowing for the attachment of known good dies and thus an increase of yield. However, it also requires very high placement accuracy, as the beam size at the interface between the moving parts (i.e., at the untransformed output of the laser) is very small. Moreover, it does not easily allow for integration of an isolator directly after the laser, unless the isolator is implemented inside the PIC with planar optics [10]. However, since the sensitivity of lasers to back-reflection is highly dependent on the distance between the laser and the source of the reflection, it might prove acceptable in the long run to move the isolator downstream to the output

interface of the SiP chip. The utilization of eutectic metal layers or of solder as a bonding material between the laser and the substrate of the SiP chip further facilitates heat-sinking of the lasers. Currently available commercial flip-chip bonding machines offer a very high placement accuracy in the in-plane (X- and Y-)axes, as low as 0.5 µm for top of the line equipment if proper reference marks are provided. This submicron accuracy is sufficient to ensure a good coupling between the laser and the waveguides on the SiP chip, which can be further improved by using inverse tapers on either side of the interface (i.e., tapering down the waveguides as they approach the interface to expand and match the mode profiles). Much efforts have been done in recent years to design edge couplers that further relax the required alignment tolerances [11,12]. Alignment in the vertical (Z-)axis remains a challenging problem, since it depends not only on the accuracy of the attachment process, but also on the process control exerted on layer thicknesses during SiP and laser chip fabrication. An effective way to ensure the accuracy of Z-axis placement of the laser inside a recess etched into the SiP chip is the utilization of pedestals sticking out of the recess and acting as mechanical stoppers [3, 5]. This has the advantage of reducing the surface area over which the SiP chip and the laser touch, so that the process becomes much less sensitive to the presence of small quantities of dust (i.e., it may become grey room compatible), while at the same time maintaining a high thermal and electrical conductivity between the laser and the Silicon substrate through the solder material used for the attachment (since the recess in which the laser is placed can be made sufficiently deep to reach the substrate of the SOI chip).  

In this work, we have developed a flip-chip integration process in which the vertical alignment is also guaranteed by a mechanical contact between pedestals defined in a recess etched into the SiP chip and a laser or Semiconductor Optical Amplifier (SOA), see Fig. 1. We have introduced an extra refinement to improve the accuracy in the Z-axis, making the accuracy of vertical alignment independent on the process control exerted on layer thicknesses during SiP or III-V chip fabrication, and, in principle, bringing it to below ±10 nm assuming excessive stress levels do not lead to a warping of the chips. In our process, the top cladding is locally removed from the III-V chip in the mechanical contact areas by means of a wet etch that selectively stops on the active region, and is therefore perfectly vertically aligned with the III-V

waveguiding layer. To define the top of the pedestals on the SiP chip, we first remove the back-end using a selective Reactive-Ion Etching (RIE) process stopping on top of the Si waveguide layer. A second selective dry etch stops at the bottom of the waveguide layer at the interface to the BOX. Finally, we etch 90 nm into the BOX using a timed RIE process, with an excellent tolerance of below ±10 nm, which is possible since a very small nominal thickness of additional material is removed. This last etch allows for accommodating differences between the waveguiding layer thicknesses on the two chips.

 Fig. 1. Schematic representation of the flip-chip attachment concept.

The attachment of the III-V chips is performed using a semi-manual flip-chip bonding system from Finetech. We have defined several markers on the SiP chips to align the chips in both the X- and Y-axes with submicron accuracy (see Fig. 2). In this attachment process, the III-V chip is electrically contacted at the top-contact using a solder paste first dispensed as micro-beads into the SiP recess. The backside of the laser chip is contacted after the flip-chip attachment by wire-bonding it to pads on the SiP chip. Finally, the metal electrode at the bottom of the SiP recess is also wire-bonded to additional pads on the top surface of the SiP chip (see Figs. 1, 3 and 4).

III-V Lab has modified single section semiconductor mode-locked laser (MLL) designs (with a free spectral range of ~100 GHz and a chip length of ~400 µm) intended to serve as multi-carrier light sources [13] in order to enable this flip-chipping process. Fig. 3 shows a subassembly consisting in a bar of three lasers flip-chipped onto a SiP chip (with a total width of 1.5 mm), wherein only the central laser is operated and the two adjacent devices play the role of heat spreaders. Fig. 4. shows a top-view micrograph of the SiP chip, on which the positions of the laser bar, of the soldered areas and of the wire-bonds have been overlaid.

We have obtained promising results with a measured optical power inside the SiP waveguide above 3 mW (see Fig. 5). Optical losses associated to the outcoupling of the light from the SiP chip to an optical fiber were deembedded. This optical power is 3.5 dB below what is expected from an ideal alignment based on simulations and 7 dB below the power initially sourced by the laser. There was still some mode mismatch between the laser and the SiP chip that could be improved by matching of the edge couplers on either side of the interface: While the SiP waveguide was tapered down to a 180 nm by 220 nm cross-section at the interface, the laser

stripe was left as is (1500 nm width, but with a reduced index contrast compared to SiP waveguides). By tapering down the laser stripe to a 500 nm width, an improvement of the insertion losses by 1 dB could be achieved at a given misalignment due to a better matching of the mode profiles (Fig. 6(c,d)). More extreme tapering, down to 300 nm, would again result in comparable perfectly aligned coupling efficiency as in the untapered case, but also in a relaxation of the alignment tolerances (a,b). Horizontal alignment could be further relaxed with the help of advanced edge coupler concepts [11,12]. These insertion losses indicate that we have achieved close to µm alignment in both the vertical (Z-) and lateral (X-) axes, as ~1 µm offset in either one of them would already introduce these 3.5 dB of extra, misalignement driven losses.

Fig. 2. Top view of mask layout with markers for X- and Y-axis alignment

and pedestals for Z-axis alignment.

 Fig. 3. Photograph of an attatched three-laser bar.

Fig. 4. Micrograph of SiP chip. The footprints of the three-laser bar and of the soldererd areas as well as the positions of the wirebonds are overlaid.

 Fig. 5. LI-curve of the flip-chip integrated laser with insertion losses from the grating coupler at the output of the SiP chip normalized out (black curve, left Y-axis) overlaid by the LI-curve of a nominally identical laser mounted on a ceramic substrate and measured with a large area photodetectors (red curve, right Y-axis). Both lasers were measured at 20o C.

It is apparent in Fig. 5 that the Light Out – Current In (LI) curve does not roll off up to high current levels and overlays that of a single laser mounted on a ceramic substrate once the additional insertion losses are taken into account (as compared to a measurement done with a Large Area Detector (LAD) without the coupling losses associated to an interposed optical interface). Fig. 7(a) shows similar overlays between a bar of three lasers attached to a system chip (resulting in additional features in the spectrum, that are attributed to the transfer function of the interposed SiP devices) and the characteristics of a single ceramic substrate mounted laser at different temperatures. It can be seen that the LI-curves also keep the same shape at elevated temperatures. This is contrasted by the LI-curves of a single flip-chip laser (without the heat spreaders), with reduced heat-sinking capability as seen in Fig.

7(b). It is apparent that in this later case the LI-curve rolls off above 150 mA and significantly differs from the characteristics of the ceramic substrate mounted laser. This is consistent with thermal simulations in which we see temperature differences of 6.2o C and 11o C between the laser and the SiP chip (right underneath) respectively for the 3-laser and 1-laser case (assuming a Sn0.62Pb0.36Ag0.02 solder alloy composition, a thermal conductivity conservatively halved to 25 W/mK to take interface resistances into account, a 240 µm solder pad diameter filling a spacing of 20 µm, and a thermal load of 600 mW). Acknowledgements: The authors would like to acknowledge funding from the European Commission for project “Broadband Integrated and Green Photonic Interconnects for High-Performance Computing and Enterprise Systems” (BIG PIPES) under contract 619 591.

Fig. 6. Simulation of laser to SiP waveguide insertion losses assuming a SiP waveguide tapered down to 180 nm by 220 nm, as well as a laser stripe either left with a 1.4 µm width or tapered down to 300 nm (a,b) or 500 nm (c,d) at the interface (wT). Sensitivity to vertical (Z-axis) and lateral (X-axis) displacements is calculated for two scenarios corresponding to a longitudinal (Y-axis) displacement of respectively 1.5 µm and 5 µm between the tip of the inverse taper and the edge of the laser. In the present situation of an un-tapered laser, submicron alignment tolerances are required, but these could be relaxed by either tapering the laser or employing advanced edge couplers on the SiP side.

Fig. 7. Comparison between (a) a three-laser bar and (b) a single laser flip-chipped on a SiP system chip (solid lines, left y-axis) with a comparable single laser mounted on a ceramic substrate (dashed lines, right y-axis). As in Fig. 5, the grating coupler losses at the SiP to fiber output interface are subtracted (residual effects of the interposed system are however still visible). It is apparent that in (a) the two additional un-operated lasers allow for sufficient heat sinking to obtain comparable performance as with a ceramic substrate mounted laser, while this is not the case in (b).

[1] P. De Dobbelaere, “Light source approach for silicon photonics transceivers,” presented at 2014 Europ. Conf. on Opt. Comm. (ECOC), Art. ID WS1.

[2] B. Snyder et al., “Hybrid Integration of the Wavelength-Tunable Laser With a Silicon Photonic Integrated Circuit,” J. Lightwave Technol., vol. 31, no. 34, pp. 3934-3942, Dec. 2013.

[3] A. Abbasi et al., “43 Gb/s NRZ-OOK Direct Modulation of a Heterogeneously Integrated InP/Si DFB Laser,” J. Lightwave Technol., 2016.

[4] T. Shimizu et al., “Multichannel and high-density hybrid integrated light source with a laser diode array on a silicon optical waveguide platform for interchip optical interconnection,” Photon. Res., vol. 2, pp. A19-A24, 2014.

[5] R. A. Budd et al., “Semiconductor optical amplifier (SOA) packaging for scalable and gain-integrated silicon photonic switching platforms,” in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp. 1280-1286.

[6] J. W. Nah et al., “Flip chip assembly with sub-micron 3D re-alignment via solder surface tension,” in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp. 35-40.

[7] X. Zheng et al., “Manufacturable hybrid silicon array laser source using an interposer based back-end-of-the-line integration,” in 2016 IEEE 13th Intern. Conf. on Group IV Photonics (GFP), Shanghai, 2016, pp. 14-15.

[8] A. De Groote et al., “Transfer-printing-based integration of single-mode waveguide-coupled III-V-on-silicon broadband light emitters,” Opt. Exress, vol. 24, no. 13, pp. 13754-13762, 2016.

[9] G. Li et al., “100Gb/s CWDM Transmitter And Receiver Chips On A Monolithic Si-Photonics Platform,” in Proc. 13th Intern. Conf. on Group IV Photonics (GFP), Shanghai, 2016, pp. 164-165.

[10] Y. Shoji and T. Mizumoto, “Magneto-optical non-reciprocal devices in silicon photonics,” Sci. Technol. Adv. Mat., vol. 15, 014602, 2014.

[11] N. Hatori et al., “A Hybrid Integrated Light Source on a Silicon Platform Using a Trident Spot-Size Converter,” J. Lightwave Technol., vol. 32, no. 7, pp. 1329-1336, April 2014.

[12] S. Romero-García et al., “Edge Couplers with relaxed Alignment Tolerance for Pick-and-Place Hybrid Integration of III-V Lasers with SOI Waveguides,” J. Sel. Top. Quant. Electron., vol. 20, no. 4, 8200611, 2014.

[13] A. Moscoso-Mártir et al., “Silicon Photonics WDM Transceiver with SOA and Semiconductor Mode-Locked Laser,” arXiv:1605.08668.