i o organization

8/6/2019 I O Organization

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I/O organizationI/O organizationPeripheral Devices

Computer device, such as a CD-ROM drive orprinter, that is not part of the essential computer,i.e., the memoryand microprocessor.

Peripheral devices can be external -- such as a

mouse, keyboard, printer, monitor, external Zipdrive or scanner -- or internal, such as a CD-ROM drive, CD-R drive or internal modem.


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I/O organizationI/O organization

Peripheral Devices

I/O Interface

Asynchronous Data transfer

Modes of Transfer Priority Interrupt

Direct Memory Access(DMA)

Input-Output processor Data communication processor


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I/O organizationI/O organizationInput/Output InterfacesInput/Output Interfaces

Provides a method for transferring information between internalProvides a method for transferring information between internalstorage (Such as memory and CPU registers) and external I/Ostorage (Such as memory and CPU registers) and external I/Odevicesdevices

Resolves the differences between the computer and peripheralResolves the differences between the computer and peripheraldevicesdevices

PeripheralsPeripherals--electromechanical deviceselectromechanical devices

CPU or MemoryCPU or Memoryelectronics deviceelectronics device

Data transfer rateData transfer rate

PeripheralsPeripherals--usually slowerusually slower

CPU or MemoryCPU or Memory--Usually faster than peripherals , some kinds ofUsually faster than peripherals , some kinds of

synchronization mechanism may be neededsynchronization mechanism may be needed


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I/O organizationI/O organization

Input/Output InterfacesInput/Output Interfaces

Unit of InformationUnit of Information

PeripheralsPeripherals--bytebyte

CPU or MemoryCPU or Memory--WordWord

Operating ModesOperating Modes

PeripheralsPeripherals--Autonomous, AsynchronousAutonomous, AsynchronousCPU or MemoryCPU or Memory--synchronoussynchronous


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I/O BUS and Interface ModulesI/O BUS and Interface Modules

The I/O bus consists of data lines, address lines,The I/O bus consists of data lines, address lines,

and control linesand control lines

Each peripheral device has associated with it anEach peripheral device has associated with it an

interface unit.interface unit. Each interface decodes the address and controlEach interface decodes the address and control

received from the I/O bus, interprets them forreceived from the I/O bus, interprets them for

the peripheral and provides signals for thethe peripheral and provides signals for theperipheral controller.peripheral controller.


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The I/O bus from the processor is attached toThe I/O bus from the processor is attached to

all peripheral interfaces.all peripheral interfaces.

The selected responds to the function code andThe selected responds to the function code and

proceeds to execute it.proceeds to execute it. There are four types of commands that anThere are four types of commands that an

interface may receive.interface may receive.

They are classified as control, status, data outputThey are classified as control, status, data outputand data input.and data input.


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A control command is issued to activate theA control command is issued to activate the

peripheral and to inform it what to do.peripheral and to inform it what to do. A status command is used to test various statusA status command is used to test various status

conditions in the interface and the peripheral.conditions in the interface and the peripheral.

A data output command causes the interface toA data output command causes the interface torespond by transferring data from the bus intorespond by transferring data from the bus intoone of its registers.one of its registers.

A data input command is the opposite of theA data input command is the opposite of thedata output.data output.


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I/O BUS and Memory BusI/O BUS and Memory Bus

Functions of Buses

MEMORY BUS is for information transfersbetween CPU and the Main Memory

I/O BUS is for information transfersbetween CPU and I/O devices through theirI/O interface

Physical Organizations


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Physical Organizations

Many computers use a common single bus system for both

memory and I/O interface units

2-way bus

- Use one common bus but separate control lines for each

function- Use one common bus with common control lines for bothfunctions

Some computer systems use two separate buses, one to

communicate with memory and the other with I/Ointerfaces


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I/O Bus

-Communication between CPU and all interface units is viaa common I/O Bus

An interface connected to a peripheral device may have anumber of data registers , a control register , and a statusregister

A command is passed to the peripheral by sending to the

appropriate interface register Function code and sense lines are not needed (Transfer of

data, control, and status information is always via thecommon I/O Bus)


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I/O versus Memory BusI/O versus Memory Bus In addition to communicating with I/O, the processorIn addition to communicating with I/O, the processor

must communicate with the memory unit.must communicate with the memory unit. Like the I/O bus, the memory bus contains data,Like the I/O bus, the memory bus contains data,

address, and read/write control lines.address, and read/write control lines.

There are three ways that computer buses can be usedThere are three ways that computer buses can be usedto communicate with memory and I/Oto communicate with memory and I/O

1. Use two separate buses, one for memory and other for1. Use two separate buses, one for memory and other for

I/OI/O


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I/O versus Memory BusI/O versus Memory Bus2. Use one common bus for both memory and I/O but2. Use one common bus for both memory and I/O but

have separate control lines for eachhave separate control lines for each3. Use one common bus for memory and I/O with3. Use one common bus for memory and I/O with

common control linescommon control lines

In the first method, the computer has independent setsIn the first method, the computer has independent setsof data, address and control buses, one for accessingof data, address and control buses, one for accessingmemory and other for I/O.memory and other for I/O.

We need separate I/O processor for that to do theseWe need separate I/O processor for that to do thesetasktask


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I/O versus Memory BusI/O versus Memory Bus The memory communicates with both the CPU and theThe memory communicates with both the CPU and the

IOP through a memory bus.IOP through a memory bus. The IOP communicates also with the input and outputThe IOP communicates also with the input and output

devices through a separate I/O bus with its owndevices through a separate I/O bus with its own

address, data and control lines.address, data and control lines. The purpose of IOP is to provide an independentThe purpose of IOP is to provide an independent

pathway for the transfer of information betweenpathway for the transfer of information between

external devices and internal memory.external devices and internal memory.


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Example of I/O interfaceExample of I/O interface


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ISOLATED vs MEMORY MAPPED I/O

Isolated I/O Separate I/O read/write control lines in

addition to memory read/write control lines

Separate (isolated) memory and I/Oaddress spaces

Distinct input and output instructions


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Isolated versus MemoryIsolated versus Memory--Mapped I/OMapped I/O

In the isolated I/O configuration, the CPU has distinct input anIn the isolated I/O configuration, the CPU has distinct input and outputd output

instructions, and each of these instructions is associated withinstructions, and each of these instructions is associated with address of anaddress of aninterface register.interface register.

When the CPU has distinct input and output instructions, and eacWhen the CPU has distinct input and output instructions, and each of theseh of theseinstructions is associated with the address of an interface regiinstructions is associated with the address of an interface register.ster.

When the CPU fetches and decodes the operation code of an inputWhen the CPU fetches and decodes the operation code of an input or outputor outputinstruction, it places the address associated with the instructiinstruction, it places the address associated with the instruction onto theon onto thecommon address lines.common address lines.

At the same time, it enables the I/O read (for input) or I/O wriAt the same time, it enables the I/O read (for input) or I/O write ( forte ( foroutput) control line.output) control line.


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This informs the external components that are attached to theThis informs the external components that are attached to thecommon bus that the address in the address lines is for ancommon bus that the address in the address lines is for aninterface register and not for a memory word.interface register and not for a memory word.

On the other hard, when the CPU is fetching an instruction orOn the other hard, when the CPU is fetching an instruction oran operand from memory, it places the memory address on thean operand from memory, it places the memory address on the

address lines and enables the memory read or memory writeaddress lines and enables the memory read or memory writecontrol line.control line.

This informs the external components that the address is forThis informs the external components that the address is formemory word and not for an I/O interface.memory word and not for an I/O interface.


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When the CPU fetches and decodes the operation code of an inputWhen the CPU fetches and decodes the operation code of an input or outputor output

instruction, it places the address associated with the instructiinstruction, it places the address associated with the instruction onto theon onto thecommon address lines.common address lines.

At the same time, it enables the I/O read (for input) or I/O wriAt the same time, it enables the I/O read (for input) or I/O write ( for output)te ( for output)control line.control line.

This informs the external components that are attached to the coThis informs the external components that are attached to the common bus thatmmon bus that

the address in the address lines is for an interface register anthe address in the address lines is for an interface register and not for a memoryd not for a memoryword.word.

On the other hard, when the CPU is fetching an instruction or anOn the other hard, when the CPU is fetching an instruction or an operand fromoperand frommemory, it places the memory address on the address lines and enmemory, it places the memory address on the address lines and enables theables thememory read or memory write control line.memory read or memory write control line.

This informs the external components that the address is for memThis informs the external components that the address is for memory word andory word andnot for an I/O interface.not for an I/O interface.


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Input Output TechniquesInput Output Techniques

ProgrammedProgrammed

Interrupt drivenInterrupt driven

Direct Memory Access (DMA)Direct Memory Access (DMA)


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Programmed I/OProgrammed I/O

CPU has direct control over I/OCPU has direct control over I/O

Sensing statusSensing status

Read/write commandsRead/write commands

Transferring dataTransferring data

CPU waits for I/O module to completeCPU waits for I/O module to complete

operationoperation

Wastes CPU timeWastes CPU time


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Programmed I/OProgrammed I/O -- detaildetail CPU requests I/O operationCPU requests I/O operation

I/O module performs operationI/O module performs operation

I/O module sets status bitsI/O module sets status bits

CPU checks status bits periodicallyCPU checks status bits periodically I/O module does not inform CPU directlyI/O module does not inform CPU directly

I/O module does not interrupt CPUI/O module does not interrupt CPU

CPU may wait or come back laterCPU may wait or come back later


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I/O CommandsI/O Commands CPU issues addressCPU issues address

Identifies module (& device if >1 per module)Identifies module (& device if >1 per module)

CPU issues commandCPU issues command

ControlControl -- telling module what to dotelling module what to do e.g. spin up diske.g. spin up disk

TestTest -- check statuscheck status

e.g. power? Error?e.g. power? Error? Read/WriteRead/Write

Module transfers data via buffer from/to deviceModule transfers data via buffer from/to device


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Addressing I/O DevicesAddressing I/O Devices Under programmed I/O data transfer is very likeUnder programmed I/O data transfer is very like

memory access (CPU viewpoint)memory access (CPU viewpoint) Each device given unique identifierEach device given unique identifier

CPU commands contain identifier (address)CPU commands contain identifier (address)


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Interrupt Driven I/OInterrupt Driven I/O

Overcomes CPU waitingOvercomes CPU waiting

No repeated CPU checking of deviceNo repeated CPU checking of device

I/O module interrupts when readyI/O module interrupts when ready


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Interrupt Driven I/OInterrupt Driven I/O

Basic OperationBasic Operation CPU issues read commandCPU issues read command

I/O module gets data from peripheral, CPUI/O module gets data from peripheral, CPUdoes other workdoes other work

I/O module interrupts CPUI/O module interrupts CPU CPU requests dataCPU requests data

I/O module transfers dataI/O module transfers data


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CPU ViewpointCPU Viewpoint Issue read commandIssue read command

Do other workDo other work

Check for interrupt at end of each instructionCheck for interrupt at end of each instruction

cyclecycle If interrupted:If interrupted:--

Save context (registers)Save context (registers)

Process interruptProcess interrupt Fetch data & storeFetch data & store


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Direct Memory AccessDirect Memory Access The transfer of data between a fast storage deviceThe transfer of data between a fast storage device

such as magnetic disk and memory is often limitedsuch as magnetic disk and memory is often limited

by the speed of the CPU.by the speed of the CPU.

Removing the CPU from the path and letting theRemoving the CPU from the path and letting the

peripheral device manage the memory buses directlyperipheral device manage the memory buses directly

would improve the speed of transfer.would improve the speed of transfer.

This transfer technique is called direct memoryThis transfer technique is called direct memory

access (DMA)access (DMA)

A DMA controller takes over the buses to manageA DMA controller takes over the buses to manage

the transfer directly between the I/O device andthe transfer directly between the I/O device and

memory.memory.


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Direct Memory Access(DMA)Direct Memory Access(DMA)


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Direct Memory AccessDirect Memory Access The CPU may be placed in an idle state in aThe CPU may be placed in an idle state in a

difference of waysdifference of ways

first common method extensively used infirst common method extensively used inmicroprocessors is to disable the buses throughmicroprocessors is to disable the buses through

special control signals.special control signals.

The bus request (BR) input is used by the DMAThe bus request (BR) input is used by the DMAcontroller to request the CPU to release control ofcontroller to request the CPU to release control of

the buses.the buses.


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DMA ControllerDMA Controller The DMA controller needs the usual circuits ofThe DMA controller needs the usual circuits of

an interface to communicate with the CPU andan interface to communicate with the CPU andI/O device.I/O device.

In additional, it needs an address register, a wordIn additional, it needs an address register, a word

count register and a set of address lines.count register and a set of address lines. The address register and address lines are usedThe address register and address lines are used

for direct communication with the memoryfor direct communication with the memory

The word count register specifies the number ofThe word count register specifies the number ofwords that must be transferred.words that must be transferred.


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DMA ControllerDMA Controller The data transfer may be done directlyThe data transfer may be done directly

between the device and memory under controlbetween the device and memory under controlof DMA.of DMA.

The DMA controller has three resistersThe DMA controller has three resisters

a)a) An address registerAn address register

b)b) A word count registerA word count register

c)c) A control registerA control register


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DMA ControllerDMA Controller The address register contains an address toThe address register contains an address to

specify the desired location in memory.specify the desired location in memory. The address bits go through bus buffers into theThe address bits go through bus buffers into the

address bus.address bus.

The address register is incremented after eachThe address register is incremented after each

word that is transferred to memory.word that is transferred to memory.

The word count register holds the number ofThe word count register holds the number ofwords to be transferred.words to be transferred.


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DMA ControllerDMA Controller This register is decremented by one after eachThis register is decremented by one after each

word transfer.word transfer. The control register specifies the mode ofThe control register specifies the mode of

transfer.transfer.

All registers in the DMA appear to the CPU asAll registers in the DMA appear to the CPU asI/O interface register.I/O interface register.

Thus the CPU can read from or write into theThus the CPU can read from or write into the

DMA registers under program control via theDMA registers under program control via thedata bus.data bus.


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DMA ControllerDMA Controller The DMA first initialized by the CPU then afterThe DMA first initialized by the CPU then after

the DMA starts and continues to transfer datathe DMA starts and continues to transfer databetween memory and peripheral unit until anbetween memory and peripheral unit until anentire block is transferred.entire block is transferred.

The initialization process is essentially a programThe initialization process is essentially a programconsisting of I/O instructions that include theconsisting of I/O instructions that include theaddress for selecting particular DMA registers.address for selecting particular DMA registers.

The CPU initializes the DMA by sending theThe CPU initializes the DMA by sending thefollowing information through the data bus:following information through the data bus:


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DMA ControllerDMA Controller1.1. The starting address of the memory blockThe starting address of the memory block

where data are available for read) or wherewhere data are available for read) or wheredata are to be stored (for write)data are to be stored (for write)

2.2. The word count, which is the number ofThe word count, which is the number of

words in the memory blockwords in the memory block

3.3. Control to specify the mode of transfer suchControl to specify the mode of transfer such

as read or writeas read or write4.4. A control to start the DMA transferA control to start the DMA transfer


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DMA ControllerDMA Controller The starting address is stored in the addressThe starting address is stored in the address

register.register. The word count is stored in the word countThe word count is stored in the word count

register and the control information in theregister and the control information in the

control register.control register. Once the DMA is initialized, the CPU stopsOnce the DMA is initialized, the CPU stops

communicating with DMA unless it receivescommunicating with DMA unless it receives

an interrupt signal or if it wants to check howan interrupt signal or if it wants to check howmany words have been transferred.many words have been transferred.


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DMA TRANSFER


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Direct Memory AccessDirect Memory Access Interrupt driven and programmed I/O requireInterrupt driven and programmed I/O require

active CPU interventionactive CPU interventionTransfer rate is limitedTransfer rate is limited

CPU is tied upCPU is tied up

DMA is the answerDMA is the answer


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DMA FunctionDMA Function Additional Module (hardware) on busAdditional Module (hardware) on bus

DMA controller takes over from CPU for I/ODMA controller takes over from CPU for I/O


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DMA OperationDMA Operation CPU tells DMA controller:CPU tells DMA controller:--

Read/WriteRead/Write Device addressDevice address

Starting address of memory block for dataStarting address of memory block for data

Amount of data to be transferredAmount of data to be transferred

CPU carries on with other workCPU carries on with other work

DMA controller deals with transferDMA controller deals with transfer DMA controller sends interrupt when finishedDMA controller sends interrupt when finished

DMA T fDMA T f


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DMA TransferDMA Transfer

Cycle StealingCycle Stealing DMA controller takes over bus for a cycleDMA controller takes over bus for a cycle

Transfer of one word of dataTransfer of one word of data

CPU suspended just before it accesses busCPU suspended just before it accesses bus

i.e. before an operand or data fetch or a data writei.e. before an operand or data fetch or a data write Slows down CPU but not as much as CPUSlows down CPU but not as much as CPU

doing transferdoing transfer


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DMA Configurations (1)DMA Configurations (1)

Single Bus, Detached DMA controllerSingle Bus, Detached DMA controller

Each transfer uses bus twiceEach transfer uses bus twice I/O to DMA then DMA to memoryI/O to DMA then DMA to memory

CPU is suspended twiceCPU is suspended twice

CPUDMA

Controller

I/O

Device

I/O

Device

Main

Memory


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Single Bus, Integrated DMA controllerSingle Bus, Integrated DMA controller Controller may support >1 deviceController may support >1 device

Each transfer uses bus onceEach transfer uses bus once DMA to memoryDMA to memory

CPU is suspended onceCPU is suspended once

CPU

DMA

Controller

I/O

Device

I/O

Device

Main

Memory

DMA

Controller

I/O

Device


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Separate I/O BusSeparate I/O Bus

Bus supports all DMA enabled devicesBus supports all DMA enabled devices

Each transfer uses bus onceEach transfer uses bus once DMA to memoryDMA to memory

CPU is suspended onceCPU is suspended once

CPU DMA

Controller

I/O

Device

I/O

Device

Main

Memory

I/O

Device

I/O

Device

I/O PI/O P


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I/O ProcessorsI/O Processors

The DMA controller introduced in the previousThe DMA controller introduced in the previous

lecture can improve system performance bylecture can improve system performance by

speeding up data transfers between memory andspeeding up data transfers between memory and

I/O devices.I/O devices.

However, multiple transfers require separate DMAHowever, multiple transfers require separate DMA

transfers, along with the necessary setup for eachtransfers, along with the necessary setup for each

transfer.transfer.

In some cases, data must be manipulated once it isIn some cases, data must be manipulated once it is

read from the I/O device; the DMA controller canread from the I/O device; the DMA controller can

only transfer data.only transfer data.


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Each of these shortcomings is addressed by I/OEach of these shortcomings is addressed by I/O

processors.processors. I/O processors, sometimes called I/O controllers,I/O processors, sometimes called I/O controllers,

channel controllers or peripheral processing unitschannel controllers or peripheral processing units

(PPUs), perform the functions of DMA controllers and(PPUs), perform the functions of DMA controllers andmuch more.much more.

The I/O processor is situated between the I/O devicesThe I/O processor is situated between the I/O devices

and the rest of the system, very much like the DMAand the rest of the system, very much like the DMAcontroller.controller.

/


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Input/output Processor (IOP)Input/output Processor (IOP)


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Unlike the DMA controller however, the I/OUnlike the DMA controller however, the I/O

processor connects to more than one I/O device.processor connects to more than one I/O device. The I/O devices are grouped together on an I/OThe I/O devices are grouped together on an I/O

bus, as opposed to the regular system bus.bus, as opposed to the regular system bus.

Thus, one I/O processor can coordinate transfersThus, one I/O processor can coordinate transfersfrom several different I/O devices.from several different I/O devices.

Generally speaking , I/O processors handle all ofGenerally speaking , I/O processors handle all of

the interactions between the I/O devices and thethe interactions between the I/O devices and theCPU.CPU.


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The CPUThe CPUs only direct I/O interaction is with the I/Os only direct I/O interaction is with the I/Oprocessor itselfprocessor itself

If the CPU must read in data from an I/O device orIf the CPU must read in data from an I/O device orinitiate a block transfer between an I/O device andinitiate a block transfer between an I/O device andmemory, the CPU instructs the I/O processor tomemory, the CPU instructs the I/O processor toperform this task.perform this task.

The I/O processor coordinates the actual data transfer.The I/O processor coordinates the actual data transfer.

The only exception is that the CPU coordinates theThe only exception is that the CPU coordinates thetransfer of data between itself and the I/O processor.transfer of data between itself and the I/O processor.

Ch l /CPU C i tiChannel /CPU Comm nication


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Channel /CPU CommunicationChannel /CPU Communication


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Data Communication ProcessorData Communication Processor A data communication processor is an I/O processorA data communication processor is an I/O processor

that distributes and collects data from many remotethat distributes and collects data from many remoteterminals connected through telephone and otherterminals connected through telephone and othercommunication lines.communication lines.

It is specialized I/O processor designed toIt is specialized I/O processor designed to

communicate directly with data communicationcommunicate directly with data communicationnetworks.networks.

An I/O processor communicates with peripheralsAn I/O processor communicates with peripherals

through a common I/O bus that comprised of manythrough a common I/O bus that comprised of manydata and control lines.data and control lines.


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Data Communication ProcessorData Communication Processor A data communication processor communicatesA data communication processor communicates

with each terminal through a single pair of wires.with each terminal through a single pair of wires. The way that remote terminals are connected toThe way that remote terminals are connected to

a data communication processor is via telephonea data communication processor is via telephone

lines or other public or private communicationlines or other public or private communicationfacilities.facilities.

The converter are called modem.The converter are called modem.

Data can be transmitted between two points inData can be transmitted between two points inthree different modes:three different modes:


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Data Communication ProcessorData Communication Processor1.1. Simplex: 0ne direction onlySimplex: 0ne direction only

2.2. HalfHalf--duplex: transmitting in both directionsduplex: transmitting in both directionsbut data can be transmitted in only onebut data can be transmitted in only one

direction at a time. Need pair of wires.direction at a time. Need pair of wires.

3.3. FullFull--duplex: transmission can send and receiveduplex: transmission can send and receive

data in both directions simultaneouslydata in both directions simultaneously

i o organization

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