BY:

NAVEEN KUMAR DUBEY

BUSES(Inter Integrated Circuit Bus)

CI 2

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@naveen_elex

OUTLINES:-

I2C-Bus:Introduction

Key Features of I2C Buses

Development of I2C

I2C Bus Architecture

The I2C Bus Protocol

MSSP Module in I2C buses

Conclusion

References

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I2C-Bus:INTRODUCTION

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I2C-Bus:INTRODUCTION

The I2C bus was designed by Philips in the early '80s to allow easy communication between components which reside on the same circuit board.

Philips Semiconductors migrated to NXP in 2006.

The name I²C translates into "Inter IC". Sometimes the bus is called IIC .

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INRODUCTION (Contd…)

The original communication speed was defined with a

maximum rate of 100 kbit per second.

There are some more speed options are available

Fast mode - Speed 400 Kilo bit per second.

High speed Mode – Speed 3.4 Mega Bit per second ( available since 1998)

Recently a “Fast plus mode (introduced in 2007 by NXP)” which speed lies in between above two modes.

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Key Features of I2C Buses

Simplicity and flexibility are key characteristics that make this bus attractive to many applications.

Most significant features include:

Only two bus lines are required (SDA & SCL )

No strict baud rate requirements like for instance with RS232

Simple master/slave relationships exist between all components .

Each device connected to the bus is software-addressable by a unique address .

I2C is a true multi-master bus providing arbitration and collision detection .

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Key Features (contd….)

As per recent development there are few more features

The Ultra Fast-mode is a uni-directional mode with data transfers of up to 5 Mbit/s.

Some intelligent control, usually with a single-chip microcontroller

On-chip filtering rejects spikes on the bus data line to preserve data integrity.

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Generation wise development of I2C

Original 1982 - first release

v1.0 1992 - Version 1.0 (of the I2C-bus specification)

v2.0 1998 - This updated version of the I2C-bus

specification meets requirements like

higher bus speeds and lower supply voltages.

v2.1 2000 - Version 2.1 (of the I2C-bus specification )

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Contd….

v.3 - (19th June 2007 introduced by NXP )

Fast mode plus introduced in this version.

v.4 - (13th Feb 2012 ) & V.5 - (19th October 2012)

These are user manual release .

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I2C Architecture

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SCL

SDAMASTER

SLAVE1

SLAVE2

SLAVE

N

I2C Architecture (contd..)

Master device is the one which initiates/ terminates data transfer and generates clock signals.

Slave is a device addressed by Master.

Both the master as well as slave can receive and transmit data .

In I2C communication, a master controller always generates clock (SCL) however data can be generated by both.

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I2C Protocol (Data Communication

Process)

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Protocol (contd..)

Address Formats of I2C

In I2C buses 7 bit as well as 10 bit addressing is possible.

Hence 128 or 1024 slave devices can be addressed .

In Case of 7 bit addressing one address byte is transmitted.

In case of 10 bit addressing two address bytes are transmitted over SDA line.

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Protocol (contd..)

7 bit addressing

10 bit addressing

S 1MSB

2 3 4 5 6 7LSB

R/WR

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Protocol (contd..)

Addressing & Device detection

Each device is addressed individually by software.

New function or address can be easily “imposed” on to an existing bus.

master

Slave-1 Slave-2 Slave-3

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Protocol (contd..)

Communication

Communication must start with : START condition

Start bit always followed bye Slave address.

Slave address always followed by Read/Write bit

The device must always send ACKNOWLEDGE bit (either master or slave)

Communication must terminate with : STOP condition

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Protocol (contd..)

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Protocol (contd..)

Start & Stop Condition

Start Condition – A high to low transition on SDA when

SCL is high.

Stop Condition – A low to high transition on SDA when SCL is high.

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Protocol (contd..)

Bit Transfer

During Data transfer SDA must be stable when SCL is high.

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Protocol (contd..)

Data Transfer & Clock Stretching

Each byte has to followed by Acknowledge Bit.

Number of Byte transferred per transfer is unrestricted .

If slave can’t receive or transmit another complete byte of data, it can hold the clock line SCL LOW (clock stretching) to force the master in to wait state.

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Protocol (contd..)

Acknowledge / Not Acknowledge

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Scenario with NACK (not acknowledge ) Condition

A receiver with the address is not present on I2C bus

The receiver is performing real time task and can not process

information received from I2C bus.

A receiver is master and want to take control on SDA to generate

STOP command. The slave transmitter must release SDA after

reception of NACK ,so that master can generate STOP.

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I2C Protocol Summary

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MSSP Module in I2C buses

The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices.

Developed by Microchip .

MSSP ModesThe MSSP module can operate in two modes: Serial Peripheral Interface (SPI)

- Full Master mode- Slave mode (with general address call)

Inter-Integrated Circuit (I2C)- Master mode- Multi-Master mode- Slave mode

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Module Setup

To configure the MSSP module for Master I2C mode, there are key SFR registers which must be initialized.

Respective code examples are shown for each.

1. SSP Control Register1 (SSPCON1)

• I2C Mode Configuration

2. SSP Address Register (SSPADD)

• I2C Bit Rate

3. SSP Status Register (SSPSTAT)

• Slew Rate Control

• Input Pin Threshold Levels ( I2C)

4. Pin Direction Control (TRISC)

• SCL/SDA Direction

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I2C MODE CONFIGURATION

BIT RATE CALCULATION

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I2C BIT RATE SETUP

SLEW RATE CONTROL

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SCL/SDA PIN DIRECTION SETUP

ACKNOWLEDGE EVENT

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NOT ACKNOWLEDGE EVENT

START EVENT COMPLETION CHECK

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READ EVENT COMPLETION CHECK

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WRITE EVENT COMPLETION CHECK

Conclusion

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The I2C-bus has become a de facto world standard

that is now implemented in over 1000 different ICs

and licensed to more than 50 companies.

Many of today’s applications, however, require higher bus

speeds and lower supply voltages. The updated version of the

I2C-bus specification meets those requirements.

References

http://www.i2c-bus.org/

http://www.nxp.com/documents/user_manual/UM10204.pdf

The I2C Bus Specification, version 2.1, January 2000

http://www.semiconductors.philips.com/buses/i2c

www.phxmicro.com/Animation/I2C_Tutorial.htm

http://ww1.microchip.com/downloads/en/appnotes

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THANK YOU