ib3 =( + 1) ie2 zero-crossing...

12
102 ELECTRONIC DESIGN / APRIL 5, 1999 IDEAS FOR DESIGN A zero-crossing detector delivers an output pulse that synchro- nizes other circuitry to the tran- sitions through zero volts of a sinuso- dial source for both polarity excursions. This detector, which was developed to operate from the ac power line, includes a unique nega- tive-voltage detector/level shifter. In Figure 1, Q2/Q3 appear to be op- erating in their common-base/com- mon-collector modes, respectively. However, in this application they actu- ally function in the common-emitter mode! Essentially, the output result- ing from their combined interactions is that of an npn transistor turned on by a negative current source. The major goals for this design were: 1) efficiency—minimum power consumed while operating, and 2) the circuit should allow no dc current to flow during power outages. The high impedance presented to the power line by the divider/filter (formed by R1, C1, R2, and R3) keeps power loss very low and effectively suppresses noise spikes from reaching the semi- conductors. As required, all transis- tors will be off during the absence of line voltage. For the values given, the detector outputs a pulse 200 μs wide and the network attenuates spikes up to 15 μs wide by more than 27 dB. For this detector to function prop- erly, the transistors used must pos- sess reasonably high betas (β > 75) due to the low drive currents allowed by the divider. It’s also desirable, but not necessary, that they be comple- mentary matched pairs, both in beta values and saturation levels. Matched conditions are assumed in the circuit discussion that follows. Q1 is turned on and kept on while the power line is positive and operates in standard npn fashion. When zero volts occurs on the line, the Sync out- put goes high. As the line goes nega- tive, Q2 turns on and Q2/Q3 perform their magic. As shown in Figure 2, Q2’s emitter will be clamped at -V BE , and the majority of the negative emit- ter drive current received will flow into Q3’s base. This current then is amplified by Q3 so that: I E3 = (β + 1)I B3 = (β + 1)(β/β + 1)I E2 Therefore , I E3 = βI E2 while Q2/Q3 are in a linear mode pulling Sync low. What are the oper- ating voltages when saturation is reached? With -V BE at Q2’s emitter, (+V SAT - V BE ) at Q2’s collector/Q3’s base, Q3’s emitter is +V BE , up from its base and therefore equal to + V SAT . The performance exhibited again appears to be that of an npn. Remember, though, that a negative drive current is turning it on. When Sync is high, charge is stored on the junction and stray ca- pacitances at Q3’s base. If V CC is greater than Q3’s base-emitter breakdown voltage, then some bleeder path must be provided to re- move this trapped charge. Otherwise, breakdown of that diode will occur when Q1 pulls Sync low. Not an ideal situation! R5 accomplishes this task and can be relatively large due to the small value of capacitance involved. A Unique Discrete Zero-Crossing Detector ROBERT W. HILSHER 16 Baltistan Court, Baltimore, MD 21237-4555; (410) 391-4379; e-mail: [email protected]. Circle 523 120 V ac Hot Neutral R1 180k R2 180k C1 240 pF R3 36k Q1 2N3904 Q2 2N3904 9 V + R4 27k Sync R5 680k Q3 2N3906 200 ms 8.333 ms bI E2 I E2 –V BE Q2 Q3 +V SAT I B3 =(b/b + 1) I E2 +V SAT – V BE 1. In this unusual zero-crossing detector, even though Q2/Q3 appear to be operating in their common-base and common-collector modes, respectively, in this configuration they are actually functioning in the common-emitter mode. 2. Most of the negative emitter drive current received will flow into Q3’s base.

Upload: others

Post on 19-Apr-2020

8 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear

102

ELEC

TRON

IC D

ESIG

N /

APRI

L 5, 1

999

IDEAS FOR DESIGN

A zero-crossing detector deliversan output pulse that synchro-nizes other circuitry to the tran-

sitions through zero volts of a sinuso-dial source for both polarityexcursions. This detector, which wasdeveloped to operate from the acpower line, includes a unique nega-tive-voltage detector/level shifter.

In Figure 1, Q2/Q3 appear to be op-erating in their common-base/com-mon-collector modes, respectively.However, in this application they actu-ally function in the common-emittermode! Essentially, the output result-ing from their combined interactionsis that of an npn transistor turned onby a negative current source.

The major goals for this designwere: 1) efficiency—minimum powerconsumed while operating, and 2) thecircuit should allow no dc current toflow during power outages. The highimpedance presented to the powerline by the divider/filter (formed byR1, C1, R2, and R3) keeps power lossvery low and effectively suppressesnoise spikes from reaching the semi-conductors. As required, all transis-

tors will be off during the absence ofline voltage. For the values given, thedetector outputs a pulse 200 µs wideand the network attenuates spikes upto 15 µs wide by more than 27 dB.

For this detector to function prop-erly, the transistors used must pos-sess reasonably high betas (β > 75)due to the low drive currents allowedby the divider. It’s also desirable, butnot necessary, that they be comple-mentary matched pairs, both in betavalues and saturation levels. Matchedconditions are assumed in the circuitdiscussion that follows.

Q1 is turned on and kept on whilethe power line is positive and operatesin standard npn fashion. When zerovolts occurs on the line, the Sync out-put goes high. As the line goes nega-tive, Q2 turns on and Q2/Q3 performtheir magic. As shown in Figure 2,Q2’s emitter will be clamped at −VBE,and the majority of the negative emit-ter drive current received will flowinto Q3’s base. This current then isamplified by Q3 so that:

IE3 = (β + 1)IB3 = (β + 1)(β/β + 1)IE2

Therefore, IE3 = βIE2

while Q2/Q3 are in a linear modepulling Sync low. What are the oper-ating voltages when saturation isreached? With −VBE at Q2’s emitter,(+VSAT − VBE) at Q2’s collector/Q3’sbase, Q3’s emitter is +VBE, up fromits base and therefore equal to +VSAT. The performance exhibitedagain appears to be that of an npn.Remember, though, that a negativedrive current is turning it on.

When Sync is high, charge isstored on the junction and stray ca-pacitances at Q3’s base. If VCC isgreater than Q3’s base-emitterbreakdown voltage, then somebleeder path must be provided to re-move this trapped charge. Otherwise,breakdown of that diode will occurwhen Q1 pulls Sync low. Not an idealsituation! R5 accomplishes this taskand can be relatively large due to thesmall value of capacitance involved.

A Unique DiscreteZero-Crossing Detector

ROBERT W. HILSHER16 Baltistan Court, Baltimore, MD 21237-4555; (410) 391-4379;

e-mail: [email protected].

Circle 523

120V ac

Hot

Neutral

R1180k

R2180k

C1240 pF

R336k

Q12N3904

Q22N3904

9 V+

–R427k

Sync

R5680k

Q32N3906

200 ms

8.333 ms

bIE2

IE2

–VBE

Q2

Q3

+VSATIB3 =(b/b + 1) IE2

+VSAT – VBE

1. In this unusual zero-crossing detector, even though Q2/Q3 appear to be operating in their common-base and common-collector modes,respectively, in this configuration they are actually functioning in the common-emitter mode.

2. Most of the negative emitter drive currentreceived will flow into Q3’s base.

Page 2: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear

Folio ICE-07 21

Centro Universitario de Ciencias Exactas e Ingenierías DIVISION DE ELECTRONICA Y COMPUTACION

CONTROL DE TEMPERATURA DE UN HORNO

Sergio Alfredo Gomez Lopez, Oscar Resendiz Vazquez, Luis Alberto Rodríguez Gallo, Francisco Javier Tirado Garcia

[email protected], [email protected], [email protected], [email protected]

RESUMEN

El presente proyecto muestra el diseño de un sistema para controlar la temperatura dentro de una cámara de un horno por medio de una PC, y a través de la incorporación de interfaces hacia diferentes sistemas, se logra una mejor organización de los recursos, lo cual hace que se tenga un mayor aprovechamiento de la energía, disminuyendo costos de operación y de materiales.

El utilizar la PC, da la precisión y la rapidez necesaria para que el sistema sea seguro y confiable. El uso de las interfaces permite aprovechar su versatilidad para adaptar sistemas digitales con instrumentos analógicos. ANTECEDENTES Los sensores electrónicos de temperatura convierten la cantidad física temperatura en una señal eléctrica. La capacidad de transmitir estas señales a distancias largas es muy buena, y por lo tanto, los puntos de medida y de indicación pueden ser situados lejanamente. Se puede incorporar y procesar las señales en sistemas de control y de regulación.

Un termopar es un sensor de temperatura que suministra una señal de tensión eléctrica, que depende directamente de la temperatura, sin energía adicional auxiliar, a causa de sus características termoeléctricas. Dos conductores metálicos son conectados en sus extremos.

Si las conexiones están a temperaturas diferentes, se puede medir una tensión de

corriente continúa por interposición de un instrumento de medida en el circuito térmico, que se forma de esta manera.

Un termopar no mide temperaturas absolutas, sino la diferencia de temperatura entre

el extremo caliente y el ex-tremo frío. Este efecto termoeléctrico hace posible la medición de temperatura mediante termopares.

Para realizar el control de la planta se utiliza una computadora personal y una interfaz de conversión analógica-digital, y digital-analógica. Por medio de este sistema se realiza el control de la planta, pudiendo así obtener una respuesta rápida en el control de las temperaturas, la cual también utiliza una etapa de potencia para amplificar la señal de salida de la PC.

Page 3: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear

Folio ICE-07 22

Centro Universitario de Ciencias Exactas e Ingenierías DIVISION DE ELECTRONICA Y COMPUTACION

DESARROLLO Para lograr el objetivo propuesto, en primer lugar se obtiene una señal eléctrica analógica a partir del sensor de temperatura, luego se usa un convertidor analógico-digital y una interfaz hacia la PC, en ella se almacenan los datos, para que se comparen con los set points deseados.

La interfaz permite conocer la temperatura actual dentro de la cámara del horno, y de esta manera actuará la PC dependiendo de la temperatura leída, si esta es menor a la establecida previamente, el sistema activará una varilla de cuarzo de 1300 watts, que se encenderá con la potencia necesaria para establecer la temperatura en el punto deseado, el valor de la temperatura de la varilla, será mayor o menor dependiendo de que tan abajo esta la temperatura, así como el tiempo que estará encendida.

En caso de que la temperatura sea mayor a la establecida, el sistema activará un par

de ventiladores, colocados en cada extremo de horno, que servirán para disminuir la temperatura del horno, así a través de la interfaz de la PC controlaremos la velocidad y el tiempo de ejecución de los ventiladores, para establecer la temperatura en el nivel deseado.

Figura 1. Circuito activador de la varilla de cuarzo.

El sofware es implementado con visual basic, que se encarga de realizar la

comparación de los datos y despliega la información en la pantalla en la cual se establecerán los set points, se utilizan circuitos ADC, y DAC, para la entrada y salida de valores de los elementos descritos anteriormente, asi como buffers y otros dispositivos para evitar daños en los circuitos de la PC. En la figura 2 se muestra el diagrama a bloques del sistema.

Page 4: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear

Folio ICE-07 23

Centro Universitario de Ciencias Exactas e Ingenierías DIVISION DE ELECTRONICA Y COMPUTACION

Figura 2. Diagrama a bloques del sistema. RESULTADOS Se tiene un control más exacto de las temperaturas, con lo cual se logra un mayor ahorro de energía. El control desarrollado permite establecer los set points y evita sobreimpulsos. La computadora personal ejecuta el algoritmo de control y se tiene una transferencia mas rápida de datos entre todas las interfaces ya que la computadora personal es la que se encarga de controlar y administrar todo el sistema.

PC Software de Control

Termopar (Sensor de

Temperatura)

Interface ADC

Varilla (Fuente

de Calor)

Interface de Control

Sistema de Enfriamiento

Page 5: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 6: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 7: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 8: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 9: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 10: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 11: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear
Page 12: IB3 =( + 1) IE2 Zero-Crossing Detectorcatarina.udlap.mx/u_dl_a/tales/documentos/meie/carrillo_a_j/apendi… · 1. In this unusual zero-crossing detector, even though Q2/Q3 appear