1

IBM 2000W POWER SUPPLY

PART 2

OPERATIONAL & TECHNICAL

ANALYSIS

By

Isaac Ozkaynak

2

1. INTRODUCTION

In the previous investigation of the IBM 2KW Power Supply (PS), Part 1,

we have furnished the system level findings and measurements, regarding the

unit as a black box. In this report, we delve into operational details of the

subunits, including the theory of operation and pertaining salient waveform

documentation. The power supply block diagram is shown in Figure 1. It is

conventional power supply architecture with the I2C Bus I/O capability. The

overall schematic of the IBM PS is provided as B size inserts to this section.

Figure 1 – Block diagram of IBM Power Supply.

C7

.0022uF

C1

1uF

T2

5.31mH

13

24

T1

3.42mH

13

24

C2

1uF

AC

C10

.86uF

C5

.0022uF

AC

C6

.0022uF

C14

.0022uF

- +

D5D25XB60

C9

1uF

C4

.0022uF

C3

.0022uF

GND

C8

.0022uF

Figure 2 – EMI Filter & Bridge Rectifier Schematic.

3

2. EMI FILTER AND RECTIFIER BRIDGE

The EMI Filter is shown in Figure 2. It is a conventional EMI filter, based

on the use of two Common Mode (CM) Chokes whose measured parameters are

shown in Table 1.

Table 1 – Measured circuit parameters of the EMI Filter Common Mode Chokes

Parameter T1 T2

CM Magnetizing

Inductance

3.42mH 5.31mH

Leakage Inductance 12.4 Hµ 13 Hµ

DC Resistance 10mΩ 9mΩ

As shown in Figure 3, the CM Chokes are placed on top of the C1, C2 and

C9 capacitors for saving space on the motherboard [N.B. We should deploy this

approach whenever the application height dimension allows].

Further electrical circuit and attenuation performance analyses on this EMI

Filter is not conducted as part of this report due to conventionality of the

implementation.

The bridge rectifier is 25A and 600V rated. It shares the same heatsink

with the PFC Power Switch devices, as we shall examine in the next section.

The IBM EMI Filter does not contain any NTC (Negative Temperature

Coefficient) thermistors, which are deployed in the flowing stage, PFC.

4

Figure 3 – Overall assembly of IBM 2KW Power Supply.

Figure 4 – Closer picture of CM Choke Placement in the assembly.

5

3. POWER FACTOR CORRECTION SUB UNIT

The IBM PS employs an interesting approach for implementing high

efficiency PFC performance via use of a rather novel Soft Switching Scheme

which is based on reverse recovery loss reducing active snubber1. PFC section

schematic is shown in Figure 5. L2, C13, D4 and Q1 form the active snubber.

R3

.047

R4

.047

L1

363uH

tRT1

12

+C12

560uF

+ C13

6.8uF

R1

.047

+C11

560uF

D1

1N5406

1 2

K1

R2

.047

C14

.0022uF D4

RHRP3060

1 2

- +

D5D25XB60t

RT2

12

D2DIODE

Q1APT47N60BC3 1

2

3

L2

3.9uH

D3

RHRP3060

1 2

Q2

HGTG30N60A4D 1

2

3

C1

uF

Figure 5 – Schematic of IBM PS PFC Sub Unit.

RT1 and RT2 thermistors mitigate the AC Line voltage peak turn-on

current transient. They are bypassed by relay K1 contacts after C11 and C12

bulk capacitors are charged up to the peak line voltage of the moment. The

reader is assumed as broadly familiar with the PFC Boost Converter operation.

Therefore, we examine here the operation of the active snubber. The PFC Circuit

1 Y. Jang and M. Jovanovic, “A New, Soft-Switched, Hogh-Power-Factor Boost Converter with IGBTs”, IEEE Trans. On Power Electronics, Vol.17, No.4, 2002.

6

shown in Figure 5 is simplified and redrawn in Figure 6. The salient waveforms

during one switching period of the PFC is shown in Figure 7

As Figure 6 implies, the PFC Inductor is assumed to be large enough for

representing its current with a current source, INI . It is also assumed that the

PFC Bulk capacitors (C11 and C12 in Figure 5) are large enough for

representing their voltage with a voltage source, oV in Figure 6. The boost (S)

Figure 6 – Simplified circuit schematic of the active snubber.

and auxiliary switch (S1) operate with overlapping gate signals, Figure 7, during

the ON time sub interval.

Prior to the moment of 0T , Figure 6, we assume that the switch S was off

and the diode D was conducting. At the moment of 0T , switch S is turned on. The

output voltage oV appears across SL and its current, therefore the PFC diode

current, Di , linearly decays towards zero with a slope of

7

Figure 7 – Salient waveforms of the active snubber.

8

Figure 8 – Salient waveforms, when INI is smaller than LspI .

9

D o

S

di Vdt L

= − (1)

It reaches zero at the moment of 1T . At the same time, the the switch S current

reaches INI . The sub interval 1 2T T− is taken up by the continuum of small

reverse recovery charge current in D. At 2T , SL resonates with the “equivalent

capacitance” formed by 1OSSC , CC and DC . The equivalent capacitance is given by

1

1

OSS CEQ D

OSS C

C CC CC C

⋅= +

+ (2)

During this resonance, the SL current reaches the peak of

s

o CL p

S

EQ

V ViL

C

+= (3)

This ends at 3T , when 1DSV reaches zero. Also, at 3T , the clamp diode, CD , starts

conducting. Notice here that there needs to be a voltage difference of .5V≥

between the drain voltages of S and S1, i.e., 1DS DSV V> , for CD to conduct.

Therefore, use of MOSFETs for both switches would not work, unless S is

an IGBT and S1 is a MOSFET. This is the implementation in the IBM PS, S is

an IGBT, HGTG30N60A4D, and S1 is a MOSFET, APT47N60BC3.

With CD conducting, SL current ramps up with a slope of

C

S

VL

(4)

until it reaches zero from the reverse (i.e., negative) direction peak, Eqn. (3), and

continues with the same slope in the positive direction (i.e., towards D). When

10

SL current is in the positive direction, this discharges CC , because the current

flows into the switch S1.

At the moment of 6T , S is turned off. Its current is transferred to CD and

flows in S1. SLi does not change due to both switches being on in the prior sub

interval. At 7T , S1 is turned off, thus its output capacitance linearly charges

towards o CV V+ . Notice here that the switch S turns off under ZVS due to INI

flowing in S1 prior to its turn off. However, the same is not applicable to S1. In

Figure 6, we notice that S1 does not turn off under ZVS, and therefore,

there is a turn off switching loss incurred in S1. This loss may be mitigated

by selecting S1 as MOSFET and arranging fast gate drive. S1 being a

MOSFET (which the case with the IBM PS), would naturally increase its output

capacitance in comparison to a comparable IGBT, and the decreased slope of its

drain voltage rise may mitigate the above mentioned switching loss.

Under light load operation, INI is smaller than the peak resonant current,

given in Eqn. (3). After the moment of 5T , the waveforms shown in Figure 7

change. This change is shown in Figure 8. The snubber Inductor current reaches

INI before the switch S is turned off, therefore, the switch S voltage does not

reach o CV V+ , but remains at oV . Due to CD conducting only before 5T until the

end of the switching period, the voltage across S1 would reach o CV V+ when S1

turns off. Under light load, S1 losses, both of switching (turn off) and of

conductive, increase.

The selection of active snubber components and its design is not within

11

the scope this report, and therefore omitted here.

The PFC Sub Unit uses the Average Current Mode control along with the

use of UCC3818 PFC IC. It employs R1 through R4 parallel combination as the

PFC Inductor current sense element, Figure 5. UCC3818 is not much different

than the PFC IC used in SM-700 product, the multiplier and average current

injection amplifier architectural arrangements are the same.

Figure 9 shows the voltages across the switch S and S1 under light load

of 24 dcA .We could not operate the UUT under full load due to 180A E-Load being

under repair. Figure 9 shows the time expanded view of Figure 8. Figures 11 and

Figure 9 – Voltages across S (CH1) and S1 (CH2), 200V/div. for both.

12

Figure 10 – Time expanded view of Figure 8 waveforms. Same vertical scaling.

12 show the relative turn on and turn off sub intervals for the same waveforms.

As we can see, the switch S turns on before S1, as depicted in Figures 7 and 8.

From Figure 9, we observe that the PFC Sub Unit operates at approximately

68KHz . Figure 13 shows the measurement on the Switch S turn off spike, which

is about 712V. This is well above the 600V rating of the IGBT used, although it is

specified as the minimum in the data sheet.

13

Figure 11 – Turn off intervals for S (CH1) and S1 (CH2) switches.

Figure 12 – Turn on intervals for S (CH1) and S1 (CH2) Switches.

14

Figure 13 – Turn off spike for Switch S, 712V∼ .

Figure 14 shows the PFC Bulk Capacitor AC Ripple voltage under light

load of 4A at the +12V output. As a DC value, it indeed measures 400V, thus its

scope display capture is ignored here. Figure 15 shows the Bulk Capacitor AC

Ripple under 24A load current. Figure 16 shows the PFC Bulk Capacitor

response to 1 24A A− step loading at the output. As we can see, the capacitor

voltage follows the step load due to a few Hertz cross over frequency.

15

Figure 14 – IBM PFC Bulk Capacitor AC Ripple Voltage under light load, 4.0oI A= .

Figure 15 – PFC Bulk Capacitor AC Ripple Voltage under 24oI A=

16

Figure 16 – PFC Bulk Capacitor AC Ripple under 1 24A A− Step Loading.

4. DC-DC CONVERTER

The IBM PS employs a Phase Shifted (PS), Zero Voltage Switching (ZVS)

Full Bridge (FB) Topology with Current Doubler, Figure 17. The Current Doubler

Inductor is shown in Figure 18. Figure 19 shows the current doubler inductors

together. The DC Resistance per winding measures 2 3m mΩ− Ω . The HF

transformer primaries are connected in series between the mid points of bridge

legs. This makes the primary currents equal, and ignoring small deviations of the

turns ratio, therefore the equal secondary currents. The primary to secondary

turns ratio is

8 8 163

5.34

P

S

P

S

N T T TN T

NnN

= + ==

= ≅

(5)

17

Q4

STW45NM60

1

2

3

12V_RTN

Q6FDP047AN08A0 1

2

3

L4

7.5uH1 342

8 7 6 5

+12V

Q13

FDP047AN08A01

2

3

Q14

STW45NM60

1

2

3

+400V

T5

6 5 4 9

1 12 2 11

87

Q3

STW45NM60

1

2

3Q11

FDP047AN08A0

1

2

3

Q7

FDP047AN08A0

1

2

3

Q9

FDP047AN08A0

1

2

3

Q5STW45NM60

1

2

3

Q8

FDP047AN08A0

1

2

3 + C15

3900uF

L3

7.5uH

1 342

8 7 6 5

Q10FDP047AN08A0 1

2

3

T3

24

13

Q12

FDP047AN08A0

1

2

3

T4

6 5 4 9

1 12 2 11

87

Figure 17 – PS-ZVS-FB with Current Doubler.

18

Figure 18 – Current Doubler Inductor.

Figure 19 – Current Doubler Inductors.

19

which is confirmed by the scope captures. PS FB Switching scheme is classic

VPEC style of driving the bridge leg devices at near 50% duty ratio and forming

the forward ON pulses by the phase shift between the two sides. Figure 20

shows the drain voltages of MOSFETs in the lower legs of the bridge.

Figure 20 – Q5 (CH1) and Q4 (CH2) waveforms, Figure 17. Vertical 200V/div.

Figure 21 shows the turn on and turn off separation of the bridge leg

transistors, Q14 turning off and Q5 turning on, Figure 17. . Figure 22 shows the

same devices in the opposite phase of operation.

Figure 23 shows the voltage waveforms across the current doubler

inductors. We measure about 28V peak in the positive direction and -8V in the

20

Figure 21 – Q14 turn off and Q5 turn on.

Figure 22 – Q14 Turn on and Q5 turn off.

21

Figure 23 – Voltages across L3 (CH1) and L4 (CH2), Figure 17.Verical is 20V/div.

negative direction. With the measured time intervals from Figures 23 and 20, the

duty ratio is found to be

3.68 2 70.7%10.4

sDs

µµ

= ⋅ = (6)

We examined the possibility of an air gap being used at the HF

transformers for rendering the magnetizing inductance current helping to extend

the ZVS range, whenever the referred to the primary load current is less than the

magnetizing inductance current. Figure 24 shows the turn on and turn off

transitions under 24A load current. Figure 25 shows the same transitions under 1

22

Figure 24 – FB Bridge leg transitions under 24A load current. Vertical: 200V/div.

Figure 25 – Same as in Figure 24, except 1A load current.

23

A load current, which is the spec. minimum. We observe that the transitional

ramps maintain the same slopes. Figure 26 shows the same transitions under no

load or zero load current.

Figure 26 – Same as in Figure 24, except under zero load current.

We observe from Figure 26, that there is now an abrupt transition in the

initial one third of the transition interval. Furthermore, the measured primary and

secondary magnetizing inductances ( mL ) and leakage inductances ( Lσ ),

324.411.413500

mP

mS

P

S

L HL HL HL nHσ

σ

µµ

µ

===≅

(7)

24

suggest the following,

324.4 5.3411.4

P

S

N HnN

µ= = ≅ (8)

Thus, we conclude that the HF Transformer cores are gapped to the

extend of providing sufficiently low magnetizing inductance, such that the ZVS

continuum would be assured at 1oI A= , which is the specification minimum and

guaranteed. Under no load or zero load current conditions, the continuum of ZVS

does not matter.

Had the core been ungapped, we would have measured minimum 2-3

times the magnetizing inductance measured, Eqn. (7), with 16T of the primary

winding.

5. HOUSE KEEPING POWER SUPPLY

The house keeping power supply employ a DCM (Doscontinuous

Conduction Mode) Flyback topology with multiple outputs. The main circuit is

shown in Figure 27. It is a conventional Flyback DC-DC Converter, which

operates at 100 KHz. The measured magnetizing inductance is

1167.9mPL Hµ= (8)

From the magnetizing inductance value and through the waveform

observations, we conjecture that the housekeeping power supply was designed

for about 10W-12W, which was intended to operate down to approximately 140V-

150V input voltage range. Under DC OFF condition, when the AC Power is

25

D9

D12

START UP

+ C26

100uF

Q15B927

3

2

1

+ C27

100uF

CIRCUIT+ C24

22uF

D14

MUR160

12

R6

1

D10

T6

1

3

2

4

5

6

7

9

10

U6

TLV43123

1

1.17mH

U8LM7815

1

3

2VIN

GN

D

VOUT

D8

+9V

+ C29

220uF

RTN

C23

R10

D7

R9

R5

33K

U5

ICE2A180Z

81

2

3

4

7

5

GNDSS

FB

ISENSE

NC

VCC

DRAIN

R7

D6

D11

+12V

IBM_RV_3.SHT X01

IBM HOUSEKEEPING POWER SUPPLY

COLDWATT, INC.

13809 RESEARCH BLVD., STE.475AUSTIN, TX 78750(512)439-4900URL: HTTP://WWW.COLDWATT.COM

B

3 3Wednesday , October 05, 2005

Title

Size Document Number Rev

Date: Sheet of

+ C30

100uF

C21

+ C28

10uF

FEEDBACK

+15V

D13

HK_RTN

C22

R8

CONTROL

U7

TL431

23

1

+400V

HK_RTN

C25

Figure 27 - IBM PS Housekeeping Power Supply

26

disconnected, it is observed as maintaining regulation down to 56V input voltage.

The total parts count is found to be 50.

The converter uses a power switch integrated into a PWM Chip,

ICE2A180Z of Infineon. The integrated MOSFET power switch is rated for 800V.

The rest of the PWM IC is similar to the internal architecture of UC3844

controller. In the implemented control approach, an opto-coupler is not used and

the error amplifier "cathode" (TLV431) is directly connected to the Pin 2, FB,

which is the PWM Comparator inverting input. The non-inverting input of the

PWM comparator receives the primary inductor current amplified pulses.

The sub unit employs a bootstrap start up approach, in which the unit

starts when the VCC voltage reaches 13.5V and stops, if it drops to 8.5V.

Figure 28 shows the primary and one of the secondary winding voltages.

Figure 28 - Primary (CH1) and secondary (CH2) voltages, CH1:200V/div. & CH2:20V/div

27

The secondary voltage shown in Figure 28 is the voltage waveform of the

winding between Pins 5-4 in Figure 27. Notice that the winding rides on the 9V

DC output. Figure 29 shows the expanded view of Figure 28.

Figure 29 - Expanded view of Figure 28.

Figure 30 shows the secondary voltage waveform, CH2, of the winding

between Pins 9 and 10, Figure 27. This is the winding used for feedback control.

The positive peak voltage is measured as .88 20 17.6V⋅ = and after the paralleled

two diodes, it drops to about 15V. It is suspected of providing the rail voltage for

the PFC sub unit. Figures 31 and 32 furnish the measurements of 2D and 1D sub

intervals, respectively. Figure 33 shows the measurement of 3D time interval.

28

Figure 30 - Feedback winding waveform, CH1: 200V/div., CH2: 20V/div.

Figure 31 - Same as above, cursors measuring 2D interval.

29

Figure 32 - Same as in Figure 30, except measuring 1D time interval.

Figure 33 - Same as Figure 30, except measuring 3D time interval.

30

( )

1

2

3

1 2 3

1.204.164.48

9.84

S

S

S

S

D T sD T sD T sD D D T s

µµµ

µ

⋅ →⋅ →⋅ →

+ + ⋅ →

(9)

From Figure 28, we measure 9.92ST sµ= .We can now use Eqn. (9) for

finding the turns ratio for the feedback winding. For the ideal Flyback converter,

1

2

go

V DVn D

= ⋅ (10)

where

400

12

g

P

S

o

V PFC Output Voltage V

Nn Turns ratioN

V V

= =

= =

=

Using Eqn. (9) in (10), we find that

1

2

9.6154 10g

o

V DnV D

= ⋅ ≅ → ≈ (11)

Figure 34 shows the primary and the secondary waveform between pins

1-2 in Figure 27, for 9V output. The actual measured DC voltage is 8.97V.

Figure 35 shows the primary and the secondary waveform between pins

1-3 in Figure 27. Due to ringing, the peak voltage measurement gets "confused",

so we used the horizontal cursors for the better measurement, which is

740 20 14.8mV V⋅ =

The measured DC Output Voltage is 12.77V. Employing the forward pulse at the

secondary for this particular output, brings about "pseudo pre-loading" effect

31

Figure 34 - Secondary winding waveform for 9V output. CH2: 20V/div.

Figure 35 - Secondary winding waveform for 12V output. CH2: 20V/Div.

32

against loss of load or initial no load condition on other secondary outputs,

excluding the feedback output, by increasing the primary current by the

respective amount of load on the particular output. This leads to the continuum of

stable DCM operation at light or no load, instead of "squeaking mode" of

intermittent bursts of operation.

Finally, we mention that the housekeeping power supply uses RCD clamp

for the core reset at the primary.

6. CONCLUSIONS

Although the IBM 2KW Power Supply does not have any fascinating and

innovative features, its dexterous and insightful design with the emphasis on

attending performance details, nevertheless were impressive. Furthermore, a

crafty approach to all design implementations is observed in all sub units inside

the power supply. A very tight packaging, utilizing every air space inside its box

was also impressive.