ic design front-end solution
TRANSCRIPT
IC Design Front-End Solution
Gateway, SmartSpice, and SmartView
IC Design Front-End Solution
â˘âSilvacoâs Solution for Analog IC Front-End Design â˘âGateway Schematic Capture and Editor â˘âSmartSpice Analog Circuit Simulator â˘âSmartView Waveform Viewer and Post-Processor
Gateway, SmartSpice and SmartView Agenda
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IC Design Front-End Solution
â˘âSilvacoâs Solution for Analog IC Front-End Design â˘âGateway Schematic Capture and Editor â˘âSmartSpice Analog Circuit Simulator â˘âSmartView Waveform Viewer and Post-Processor
Gateway, SmartSpice and SmartView Agenda
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IC Design Front-End Solution
â˘âGateway - Schematic Capture and Editor â˘âSmartSpice - Berkeley based SPICE simulator â˘âSmartView - Graphical postprocessor â˘âAdvantages
â˘âEasy transition from other popular IC design tools â˘âUser-friendly and intuitive design environment â˘âDesign portability between platforms (SunOS, Windows, Linux)
â˘âPDKs (process design kits) to provide standard pre-built design models, cells, symbols, schematics for participating foundries
Silvacoâs Solution for Analog IC Front-End Design
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IC Design Front-End Solution
Analog/Mixed-Signal Design Flow
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IC Design Front-End Solution
â˘âSilvacoâs Solution for Analog IC Front-End Design â˘âGateway Schematic Capture and Editor â˘âSmartSpice Analog Circuit Simulator â˘âSmartView Waveform Viewer and Post-Processor
Agenda: Schematic Capture and Editor
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IC Design Front-End Solution
â˘âPowerful front-end schematic editor and viewer â˘âTightly integrated with Silvacoâs SmartSpice and Smartview tools â˘âCreates multi-sheet, multi-view, hierarchical, or flat designs â˘âImport\export of EDIF 2 0 0 schematics, symbols, and cells â˘âIntuitive left-to-right toolbar implementation to mirror design flow â˘âDialog box approach for building SPICE analysis control cards â˘âAnalog environment for ease of saving and plotting vectors â˘âAbility to switch processes and run process variant simulations on the
same schematic â˘âGenerate both SPICE netlist and LVS netlist from same schematic â˘âHierarchical DC bias for all currents and voltages
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âSchematic showing all paned areas which are may be moved, resized, docked, undocked, or hidden
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âSchematic Area may be maximized for largest possible drawing area
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âTwo Modes of Operation â˘âCapture
â˘âPlace â˘âEdit â˘âCheck â˘âSave
â˘âSimulation
â˘âCapture mode shown at left
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âTwo Modes of Operation â˘âCapture â˘âSimulation
â˘âNetlist â˘âControl Cards â˘âSetup Analysis â˘âChoose Vectors
â Save
â March
â˘âSimulate â˘âPostprocess
â˘âSimulation mode shown at left
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âSession area: â˘âReports schematic editing
actions, warnings, and errors â˘âReports creation of input
deck and netlist â˘âReports simulation feedback
from SmartSpice
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âHierarchical ascending and descending in design and simulation modes
â˘âView any level or levels of a design per user configuration
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âSpreadsheet style editor â˘âChanges in a single attribute dialog
may apply to: â˘âOnly selected instance â˘âSelected instances â˘âMatching symbol instances â˘âAll instances
â˘âEasy to change device models for all devices and generate subsequent runs
Gateway â Editing Instance Attributes
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IC Design Front-End Solution
â˘âDefine symbol type as: â˘âPrimitive
â˘âMOS, Bipolar, active, passive â˘âSpecial
â˘âGND, power, bus, PARAMS â˘âSub-schematic
â˘âDescend into circuit and pass parameters â˘âNetlist
â˘âAttach .SUBCKT netlist via file to symbol â˘âVerilog-A
â˘âAttach Verilog-A module via file to symbol
â˘âDefine symbol pins to have a fixed or non-fixed signal name at instance level
Gateway â Symbol Editor
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IC Design Front-End Solution
â˘âDefine attributes to be changeable or fixed for the instance level â˘âDefine expressions to be passed into the SPICE netlist â˘âSet attribute default values and visibilities â˘âEdit SmartSpice and Guardian Strings
Gateway â Symbol Editor
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IC Design Front-End Solution
â˘âSchematic Drawings generate two netlists: â˘âSmartSpice netlist (represents simulation netlist) â˘âGuardian netlist (represents LVS netlist)
â˘âEach symbol contains two strings: â˘âSmartSpice String â˘âGuardian String
â˘âExample: 4 terminal npn device (references a subcircuit definition for SmartSpice and a BJT transistor for LVS)
Gateway â SmartSpice and Guardian Strings
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SmartSpice String: X_@PREFIX@PATH %C %B %E %VSUB XNPN AREA=@W $M
SmartSpice Netlist: X_Q27 NET8 BANDGAP NET2 GND XNPN AREA=1.5U M=1!X_Q28 BANDGAP NET8 NET3 GND XNPN AREA=5U M=1
Guardian String: @PREFIX@PATH %C %B %E %VSUB NPN AREA='(1.25U*AREA)'!
Guardian Netlist: Q27 NET8 BANDGAP NET2 GND NPN AREA='(1.25U*AREA)' Q28 BANDGAP NET8 NET3 GND NPN AREA='(1.25U*AREA)'!
IC Design Front-End Solution
â˘âHierarchical design checking and reporting system
â˘âZoom to error for each error found
â˘âAutomatically opens any level with error when error is selected in report
Gateway Schematic Capture and Editor
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IC Design Front-End Solution
â˘âSet and save default settings for individuals or workgroups to file
â˘âChoose settings for integrated tools including: â˘âSet versions for SmartSpice and SmartView â˘âParallel SPICE and marching waveforms
â˘âCustomized initialization files â˘âSchematic and symbol grid setting â˘âSheet Border templates â˘âUser-defined shortcuts and bindkeys â˘âColor settings â˘âAutosave and recovery
Gateway - Customize Settings
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IC Design Front-End Solution
Gateway â Control Deck Builder
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IC Design Front-End Solution
Design Flow
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IC Design Front-End Solution
â˘âNetlists and input decks automatically created by Gateway
â˘âNetlists can be made as top-down or as .SUBCKT format
Gateway â Creating Netlists and Input Decks
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IC Design Front-End Solution
â˘âChoose which analysis to plot
â˘âSelect what to be plotted: â˘âVoltage markers on nodes â˘âCurrent markers on pins
â˘âSelect what to be saved â˘âAll currents and voltages â˘âOnly what is marked â˘âSave from control deck â˘âParametric data
â˘âPlot to: â˘âExisting plot â˘âCreate new plot â˘âOverlay simulation runs
Gateway â Pre-Simulation
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IC Design Front-End Solution
â˘âRun-time dialog â˘â Final simulation time â˘âCurrent simulation time â˘â Timestep â˘â Temperature â˘âNumber of CPUs
Gateway â During Simulation
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IC Design Front-End Solution
â˘âDC Bias Display â˘âWhen DCOP calculation
is finished â˘âAnnotate Voltage â˘âAnnotate Current â˘âOperates through
heriarchy
Gateway â DC Bias Current and Voltage
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IC Design Front-End Solution
â˘âSmartSpice finishes simulation
â˘âSmartSpice writes *.raw and *.out files
â˘âSmartView is launched â˘âThe *.raw file is loaded
automatically into SmartView
â˘âReady for cross-probing
Gateway â After Simulation
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IC Design Front-End Solution
â˘âVerilog-A modules may be mapped directly to symbols
â˘âVerilog-A circuits may be as compact models or as behavioral blocks, or both
â˘âVerilog-A circuits and regular analog primitive circuits may be mixed together and simulated
â˘âResults from analog primitive circuit and Verilog-A can be measured and overlaid
Gateway â Running Verilog-A Circuits
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IC Design Front-End Solution
Gateway File Handling
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IC Design Front-End Solution
â˘âSilvacoâs Solution for Analog IC Front-End Design â˘âGateway Schematic Capture and Editor â˘âSmartSpice Analog Circuit Simulator â˘âSmartView Waveform Viewer and Post-Processor
Agenda: SmartSpice Analog Circuit Simulator
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IC Design Front-End Solution
â˘âIndustry leader in analog IC design simulation â˘âBerkeley SPICE compatible â˘âSuperior simulator in speed and convergence â˘â100% HSPICE⢠compatible for netlists,
models, analysis features, and results â˘âCapacity - up to 400 thousand active devices
in 32 bit and 8 million active devices in 64 bit version â˘âModular design to include solvers, parsers, models, and engine â˘âSupports latest technologies â˘âSupported on Solaris, Linux, and Windows
SmartSpice â Analog Circuit Simulator
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IC Design Front-End Solution
â˘âSmartSpice may be run three ways: â˘âBatch Mode
â˘âRun cell characterization â˘âCommand line driven â˘âGenerates HSPICE⢠compatible files
(*.tr, *.mt, *.ac) â˘â Interactive Mode
â˘âGUI interface â˘âEasy access to simulation information and input deck â˘âEnvironment to manage designs
â˘â Integrated to postprocessor â˘âSchematic Mode
â˘âRun directly from schematic capture environment â˘âSchematic changes automatically update the netlist and input deck for up-to-the-
minute simulation environment
SmartSpice â Analog Circuit Simulator
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IC Design Front-End Solution
â˘âDrag and drop input decks â˘âChoose an analysis â˘âChoose what to save or plot â˘âRun Simulation â˘âDisplay Statistics â˘âOpen vector menu and plot
results
SmartSpice â Interactive Mode
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IC Design Front-End Solution
SmartSpice â File Handling
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IC Design Front-End Solution
â˘âSilvacoâs Solution for Analog IC Front-End Design â˘âGateway Schematic Capture and Editor â˘âSmartSpice Analog Circuit Simulator â˘âSmartView Waveform Viewer and Post-Processor
Agenda: SmartView Waveform Viewer and Post-Processor
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IC Design Front-End Solution
â˘âIndustry driven waveform analysis tool
â˘âHierarchical or flat vector arrangement â˘âPre-filtering of data to streamline results â˘âView histories of concurrent simulations
on one plot â˘âVector Calculator with:
â˘âBuilt-in SPICE macros and functions â˘âCapability for user-defined functions
â˘âView *.raw, *.ac0, and *.tr0 formats â˘âSupported on Solaris, Linux, and Windows
SmartView â Graphical Post-Processor
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IC Design Front-End Solution
â˘âUser-sizeable areas for plots, lists, and data
â˘âDrag and drop capability from vector tree into plot
â˘âToolbars â˘âStandard â˘âCustomizable â˘âDockable
â˘âMerge or delete vectors across single or split plots
â˘âUndo and redo capability
SmartView â Graphical Post-Processor
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IC Design Front-End Solution
â˘âVarious measuring devices â˘âView more than one rawfile at a
time â˘âSimultaneous zooming between
plots â˘âTime synchronized panning and
zooming between plots â˘âChanging axis from linear
to log â˘âContext sensitive menus for all
plot objects
SmartView â Graphical Post-Processor
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IC Design Front-End Solution
â˘âPlot to: â˘â Cartesian â˘â Polar â˘â Smith â˘â Spectral Density
â˘â Histogram
â˘âMeasurement Dialogs: â˘â Rise time â˘â RMS â˘â Min,max (P-P) â˘â Delay â˘â Period â˘â Overshoot
â˘â Average â˘â Derivative â˘â Inetgral
SmartView â Measurements Tools
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IC Design Front-End Solution
â˘âParametric Analysis â˘âView sweeps merged â˘âView sweeps separate by variable and
value â˘âAbility to combine and split sweeps
â˘âSweep manager â˘âManage all sweeps in rawfile â˘âChoose which sweeps to display â˘âHandles multiple parametric runs and
secondary sweeps
SmartView â Analyzing Parametrics
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IC Design Front-End Solution
â˘âAMS Toolflow Environment â˘âSchematic, Simulation, and Postprocessor tightly integrated â˘âUnified GUI environment for seamless interaction â˘âDesigns can be ported easily between platforms
â˘âSolaris, Windows, Linux â˘âCompatible with major foundry design kits â˘âEasy transition into Silvaco flow from other vendors
Conclusion
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