ic engineering, fju and interconnection effects switching...
TRANSCRIPT
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Lecture 5
MOS Inverter: Switching Characteristics
and Interconnection Effects
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Introduction
Cload = (Cgd,n + Cgd,p + Cdb,n + Cdb,p) + (Cint + Cg)Lumped linear capacitance
intrinsic cap. extrinsic cap.
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JUFirst-Stage CMOS Inverter With Lumped
Load Capacitance
The question of inverter transient response is reduced to finding the charge-up and charge-downtimes of a single capacitance.
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Delay-Time Definitions
V50% = VOL +0.5(VOH – VOL) =0.5(VOL + VOH)τP = ½ (τPLH + τPHL)
High-to-Low tPHL Low-to-High tPLH
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Rise Time and Fall Time
Rise Time trise: output to rise from V10% to V90%Fall Time tfall: output to fall from V90% to V10%
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Propagation Delay Calculation
Estimate the average capacitance current during charge down and charge up, respectively.
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A More Accurate Method
nDout
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iiidt
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,,
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A More Accurate Method (Cont.)
When the nMOS transistor starts conducting, it initially operates in the saturation region. When the output voltage falls below (VDD – VT,n), the nMOSstarts to conduct in the linear region.
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A More Accurate Method (Cont.)
Saturation region
Linear region
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A More Accurate Method (Cont.)
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A More Accurate Method (Cont.)
At t = t1’, the output voltage will be equal to (VDD- VT,n) and the transistor will be at the saturation-linear region boundary.
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loading
slop
e
Timingmatrix
Consider Inputs With Finite Slopes
Assuming: Input has finite rise tr & fall time tf
A cell’s delay in the Library is often characterized by a table(e.g., 5x5) in terms of two circuit-dependent indexes
- slopes of the input signals- extrinsic loading (related to no. of fanouts)
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Reducing a Cell Delay
Two Major Factors of Cell Delay– The driving current
• The larger current, the shorter propagation delay– The loading capacitance
• The larger output loading, the longer propagation delay
Common Techniques for Speeding Up A Cell– Increase VDD (ID increases)– Use low-VT device (ID increases)
• May introduce a larger sub-threshold current– Gate-sizing: increase the W/L ratio of the gate (ID increases)
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Inverter Design with Delay Constraints
Assumption: ignore the intrinsic capacitance in calculating the loading capacitance.Question: what’s the min. W/L ratio to achieve a given speed ?
By the assumption,Cload is regarded as a constant
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Considering Intrinsic Capacitance
= α0 + αnWn + αpWp
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Asymptotic Speed Limit by Sizing
Due to the drain parasitic capacitance:– Sizing up a transistor (i.e., increasing Wn and Wp) will have a
diminishing effect in reducing the propagation delay.
Limit Delay:
Delay in terms of design parameter Wn and Wp
R = Wp/Wn
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Example: Transient Response
50% reduction in tPHL when Wn = 2 to 3.2 mmBut almost no effect when Wn = 10 to 20 mm
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Example: Delay v.s. Channel Width
Limit value is about 0.2 ns,Determined by technology-specific parameters,Independent of the extrinsic capacitance components
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Optimum Wn for Area-Delay Product
Gate Sizing: is a trade-off for delay reduction by silicon areaQuestion: What’s a good balance between area and delay ?
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Another Side-Effect of Gate Sizing
Sizing Up a Gate– increases its fanin gates’ loading, slightly offseting the speed
advantages
Example– Action: increase the size of gate G3– Side-Effect: the loading capacitances of G1 and G2 will increase,
and therefore the delays across G1 and G2 increase too.
A
B
C
D
E
G1
G2
G3 F
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Three-Stage Ring Oscillator
When n is an odd no. Oscillation frequency
pnTf
τ211
==
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Interconnection Models
τrise (τfall) < 2.5 × (l / v) transmission-line model2.5 × (l / v) < τrise (τfall) < 5 × (l / v) either oneτrise (τfall) > 5 × (l / v) lumped modeling
Time of flight across the line: l/v , l is the length, v is the travel speed Inductance is important when signal rise/fall time comparable to time-of-flight
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An RLCG Interconnection Tree
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Typical Signal Waveforms
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Interconnect in Submicron Design
Interconnect delay begins to dominate the cell delayin the submicron designs
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Typical Interconnection Length
Probability
Wire Length
Chip Diagonal Length
Long running wires need accurate wire models:- inter-module connections- global bus connections- clock distribution networks
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Interconnect Segments
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Interconnect Segment
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Single Line Capacitance
Two basic components(i) Parallel Capacitance: Cpp(ii) Fringing Capacitance
Width-to-height ratio W/H
Fringing effects
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Lateral (Inter-Wire) Capacitance
Lateral cap.
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Inter-Layer Capacitance
Parallel plate cap.
Fringing & overlap cap.Fringing cap.
Lateral cap.
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Double Metal CMOS Structure
Only inter-layer cap. are shown
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Inter-Layer Parasitic Cap. For 0.8 μm
Inter-layer (vertical) capacitances- area cap. (parallel-plate cap.)- perimeter cap. (fringing cap.)
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Summary Of Parasitic Capacitances
Total Cap.
Inter-wire cap. CxInter-layer cap.
Fringing cap.Parallel-plate cap. Cp-p
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Interconnect Resistance Estimation
Rwire = r ·w · t
l
wl
= Rsheet ·
Rsheet = tr
Where r is resistivityt is the thickness
(sheet resistance)
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Interconnect Delay Models
T Model
Distributed RC Model (ladder network)
RC Model
tPLH ~ 0.69 RC
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Uniform RC Ladder Network
assume Rk=(R/N) Cj=(C/N)
For very large N
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Example: Comparison of Models
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Example: Comparison of Models
input
output withdistributed RC model
output withlumped RC model
output with
T model
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Impact of Wire Length to Delay
Assume thatUnit length resistance is RUnit length capacitance is C
Then the delay constant of a wire of k-unit length will be:RC· N· (N+1)/2
i.e., delay is quadratically proportional to the wire lengthFor example, increasing a wire length by 10 timeswill approximately increase the delay by 100 times
Using distributed RC model
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Clock Skew Problem
Definition– Clock skew refers to the maximum clock arrival time difference of the
flop-flops’ clock portsImpact– clock skew may slow down the operating speed
Clock skew minimization– near zero clock-skew can be achieved
in automatic place-and-route (APR) tools via proper buffer insertion– can be done by adopting a regular clock
tree structure (e.g., H-tree) enforced manually
H-treeclock nets
clocksource
clock sink
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Assume that:unit length capacitance is Cunit length resistance is Rthe input gate capacitance of FF’s clock port is Cgthe number labeled with each segment is the length
Example: Clock Skew Calculation
Clock source
FF
FF
A
B
6
6
22
22
1
S
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JUVoltage & Current Outputs of Inverter
Vin Vout
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Energy Transfer at Charge-Up
VDD
0
VDD
0
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VCT
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dVCVVdtdt
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Lecture 6
Combinational MOS Logic Circuits
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Introduction
• nMOS Logic- NOR Gate- NAND Gate
• CMOS Logic• Complex Logic Circuits• Transmission Logic
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Combinational Logic Circuit
Boolean Operations are the basic building block of digital systemsPositive logic convention– Logic ‘1’ represents Vdd– Logic ‘0’ represents a low voltage
Important design concerns:– DC Voltage Transfer Characteristic– VOL, Vth
– Dynamic Characteristics– Silicon Area– Static & Dynamic Power Dissipation
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Two-Input nMOS NOR Gate
Pull-up network
– Pull output voltage to high when both inputs are low
Pull-down network
–Pull output voltage to low when either input is high
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Calculation of VOL
Obviously, VOH = VDD
Three conditions in calculating VOL– VA = VOH , VB = VOL reduced to an inverter – VA = VOL , VB = VOH reduced to an inverter (Equ. 7. 4)– VA = VOH , VB = VOH both drivers are turned on
VOL = Equ. 7. 8
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Design Strategy for nMOS NOR Gate
Set a certain maximum VOL for the worst case– (i.e., output voltage should be less than this value
in normal operation)Worst case happens when only one input is highSet kdriver,A = kdriver,B = kR · kload– This design choice yields two identical drivers– Find the proper channel W and L for each transistor
When both inputs are logic-high,– The output voltage is even lower than the required maximum
VOL because lower equivalent driver-to-load k leads to a lower VOL
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Generalized to Multiple Inputs
Generalized n-input NORAssume that– The input voltages ofall drivers are identicalVGS,k = VGS for k=1,..,n
Reduced to an inverter
No body-effect in any driverSubstrate-bias of depletion-type load is VSB = Vout
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Transient Analysis
Lumped load capacitance is– Cload = Cgd,A + Cgd,B + Cgd,load + Cdb,A + Cdb,B + Csb,load + Cwire
– Valid even for single-input switching– Slower than the equivalent inverter with the same kR
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Two-Input NAND Gate
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Equivalent Driver Transconductance
Consider the only case as pull-down is turned ON– VA = high (VOH) and VB = high (VOH)
Ignore the body-effect of Driver A
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Generalized to Multiple Inputs
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Load Capacitance of NAND Gate (I)
Consider Case (I) • VA = high • VB is from VOH to VOL
Lumped load capacitanceCload = Cgd,load + Csb,load +
Cgd,A + Cgs,A + Cdb,A + Csb,A + Cgd,B + Cdb,B + Cwire
This cap. is conservativeIn reality, only a fraction ofInternal node’s capacitance isReflected into Cload
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Load Capacitance of NAND Gate (II)
Consider Case (II) • VA is from VOH to VOL• VB = VOH
Lumped load capacitanceCload = Cgd,load + Csb,load +
Cgd,A + Cdb,A + Cwire
This cap. is smaller– It means that outputLow-to-high switching isFaster in this case(e.g., 30% faster)– This property could be used for speed optimization
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Example (2-Input nMOS NAND Gate)
Two switching events
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Example: Output Waveforms
For NAND-gate,Turning off the nMOS closer to the output Results in a faster output LOW-to-HIGH transition
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CMOS Two-Input NOR Gate
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CMOS Two-Input NOR Gate
VOH = VDD, VOL = 0VVA = VB = VOUT = Vth → ID = Kn(Vth- VT,n)2
Vth = VT,n + (ID/ Kn)1/2 (7.32)From Fig. 7. 10, M3: linear region, M4: saturation for Vin = Vout
If kn = kp, Vtn = |Vtp|, the switchingthreshold of the CMOS inverter is equalto Vdd/2. the switching threshold of theNOR2 gate is (Vdd+ VT,n)/3, whichis not equal to Vdd/2
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Switching Threshold Voltage
n
p
tpDDn
pTn
th
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kk
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VNORV
kIVVV
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−−−=
−−−=
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1
|)|()2(
2||
)|)|(2
]|)|(2[2
21
21
43
234
2333
Q
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Equivalent Inverter
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Calculating Switching Threshold Vth
Definition: VA = VB = Vout = Vth
To achieve VDD/2 switching threshold:Set VT,n = | VT,p | and kp = 4kn
NOR2 = Equivalent Inverter (pull-down kdown = 2kn)(pull-down kup = (kp/2)
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Internal Parasitic Capacitances
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CMOS Two-Input NAND Gate
Assume that– (W/L)n,A = (W/L)n,A and (W/L)n,B = (W/L)n,B
(From Eq. 7.37)
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Impact of Body Effects on Series-Connected Transistor Chain
A
B
C
D
A B C D
VDD
OUT
1pFα
β
γ
The discharging currentis limited by theuppermost transistor(the one controlled by A)
because it has a larger Vtdue to Body Effects
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Area Comparison
Transistor Count for n-input logic gate– nMOS logic : (n+1)– CMOS logic : (2n)
Real silicon area is used for– Transistor– Signal Routing– Contact– Therefore, the disadvantage of CMOS in terms of
silicon area may not be as worse as the transistor count suggests
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Sample Layout of CMOS NOR2 Gate
VA VB
GND
VDD
nwell
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Sample Layout of CMOS NAND2 Gate
VA VB
GND
VDD
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nMOS Complex Logic
A Boolean function– Z = A(D+E) + BC– OR operations are done
by parallel-connected drivers– AND operations are done
by series-connected drivers– Inversion is provided by the
nature of MOS circuit
EDACB
equivalent
LW
LW
LW
LW
LW
LW
)()(
1
)(
11
)(
1
)(
11)(
++
++
=
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Worst-Case Logic-Low Voltage VOL
Various Paths from VDD to GND lead to different VOL
– A-D Class 1– A-E Class 1– B-C Class 1– A-D-E Class 2– A-D-B-C Class 3– A-E-B-C Class 3– A-D-E-B-C Class 4
Assume all (W/L) the same
– A larger path resistance leadsto a larger VOL
– VOL1 > VOL2 > VOL3 > VOL4where subscript denotesclass number
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Complex CMOS Logic Gates
Dual Network– Given a Boolean expression– Dual network is obtained via the following operations:
• Each variable is replaced by its complement• Change AND to OR operation, and vice-versa
– De-Morgan Law: f = Dual-function(f)’
Example– f = (A(D+E) + BC)’– Dual-function(f) = [A’ + (D’ E’) ] · (B’ + C’)
CMOS Logic– Use n-network’s dual function as the p-network
to replace the depletion-type nMOS load
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Graphical Method for Dual Network
outVDD
P-network
out
GND
D E
A B
C
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Example: CMOS Complex Gate
Vout = A(D+E) + BC
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Example: Equivalency Rule
5.12
151
151
1
151
151
151
1
)(
1
)(
11
)(
1
)(
1
)(
11)(
12
201
301
1
)()(
1
)()()(
11)(
))((
,
,
=+
+++
=
++
++=
=+
=
++
++
=
+++=
CBAED
eqp
CBAED
eqn
LW
LW
LW
LW
LW
LW
LW
LW
LW
LW
LW
LW
CBAEDZ
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Gate Matrix Layout
Poly-gate ordering is important:
– An improper ordering may result in extra silicon area for diffusion-to-diffusion separation
out
GND
A
D EC
B
Stick-Diagram Layout
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Optimal Gate Ordering
Euler Path– Uninterrupted path that traverses each edge of a graph exactly
onceMinimum Layout (without any diffusion break)– Gate ordering forms a common Euler path for n-net and p-net
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Optimized Stick-Diagram Layout
• Poly column separation Dd- only need to allow for one metal-to-diffusion contact
• Advantages: - smaller area and parasitic cap.
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Exclusive-OR Gate
Total no. of transistors: 12 (including two inverters for A and B)
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And-Or-Inverter (AOI) Gate
Enables sum-of-product (SOP) realizationPull-down net consists of parallel branches of series-connected nMOS driver transistors
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Or-And-Inverter (OAI) Gate
Enables product-of-sum (POS) realizationPull-down net consists of series branches of parallel-connected nMOS driver transistors
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Pseudo-nMOS Gates
Always conducting pMOS for pull-upTo reduce silicon areaNonzero static power dissipationVOL is not zero voltage any moreNoise margin is smaller– Depending on the ratio ofpMOS Load’s kp to the pull-down net’s equivalent kdown,eq
Application:– In design where densityis the no.1 concern (e.g., Memory)
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CMOS Full-Adder Circuit
BCACABoutcarryBCACBACBAABC
CBAoutsum
++=+++=
⊕⊕=
_
_
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Full Adder Schematic
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JULayout Using Minimum-sized
Transistors
co’ SUM’
A B C
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Optimized Layout
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Simulated IO Waveforms
Carry-in
B
A
Carry-out
Sum
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N-bit Binary Adder
Ripple-Carry Adder– Constructed by cascaded-connection of full adders– Speed is limited by the long carry chain
( C0 C1 C2 C3 C4 C5 C6 C7 C8 )
FA FA FA FA…
S0 S1 S2 S7
A0 B0 A1 B1 A2 B2 A7 B7
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Transmission Gate (TG)
TG is a bi-directional switch between A and B which is controlled by signal CnMOS passes perfect 0, but only up to (VDD-VT,n)pMOS passes perfect 1, but only down to |VT,p|
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Operating Regions for TG
Vin=VDD
Transmit logic ‘1’
ID
ISD,p
IDS,nVDD
Vout
0 V
ss dd
Isd,p getting smaller
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Equivalent Resistance of CMOS TG
Equivalent resistance is quite a constant
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TG-Based Logic (Steering Logic)
TG-based logic may be smaller than their standard CMOS counterparts
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JUTG-Based Logic – Arbitrary Function
A B F0 0 C’0 1 C’1 0 C1 1 1
n-well
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Sample Layout
F = AB + A C + A B C
x
F
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Only n-network is used to steer input to outputMight be faster than full TG-based logicBut overall noise immunity is weaker because nMOScannot pass a full logic “1”
CPL NAND2 CPL NOR2
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Common Standard Cell Library
Combinational Cells:– Inverter– Buffer– 2-t0-1, 4-to-1, 8-to-1 Multiplexor– NOR gates– NAND gates– And-Or-Inverter (AOI) gates– Or-And-Inverter (OAI) gates– Half Adder and Full Adder Cell
Flip-Flops– JK Flip-Flops– D Flip-Flops with Set, Reset, Enable, Scan, …, etc.
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Combinational Logic Circuits !
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Lecture 7
Sequential MOS Logic Circuits
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Synchronous Design Model
FFs FFs
clk
Comb.logic
Comb.logic
ABC out1
out2
Sequential CircuitsFFs
CombinationalLogic
ABC
OUT1OUT2
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Cross-Coupled Inverters
Bistable Element
Vi1
Vi2
Vo1
Vo2
Voltage-Transfer Curves
Circuit Diagram
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SR Latch Circuit
Transistor schematicGate-level Schematic
Truth Table
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Capacitances of CMOS SR Latch
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Rise/Fall Times of CMOS SR Latch
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NAND-Based SR Latch Circuit
Gate-level Schematic
Truth Table
Transistor schematic
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Clocked Latch Circuit
Gate-level Schematic
Example Waveforms
AOI-based implementation
shortglitch
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Clocked JK Latch
All NANDimplementation
S
R
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Truth Table of Clocked JK Latch
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AOI Realization of JK Latch
NOR-Based JK Latch
AOI-implementation
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Master-Slave Flip-Flop
Qs
Qs
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Sample I/O Waveforms
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CMOS D-Latch (I)
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CMOS D-latch (II)
Master-SlaveD Flip-Flop Tri-state inverter
A
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Sample Layout of CMOS DFF
Cross-coupled inverter-pair
AQm
Qm
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Setup & Hold Time
Valid data
Setup time is due to D-to-Q delay: violated by long-pathsHold time is due to Clock-to-Q delay: violated by short-paths
FFs FFs
clk
Comb.logic
Comb.logic
ABC out1
out2
D Q
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Common Latch Types in Cell Library
Transparent LatchJK Flip-Flop (Edge-Triggered)D Flip-Flop (Edge-Triggered)– Primitive D Flop-Flop– With Asynchronous Set and Reset– With Extra Asynchronous Enable Signal
Scan Flip-Flop– Mux-Scan Flip-Flops– SI means “scan input”– SC means “scan Control”
D-FF
MUX
clk
DSISC
Q
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Sequential Logic Circuits !
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Lecture 8
CAD for VLSI Design( Source ref. EECS244, Prof.K. Keutzer, U.C. Berkeley )
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Circuit synthesis
Performance analysis
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Predicting Technology Trend - Moore’s Law
⇒ Logic capacity doubles per IC every 18 months ( 1975 )
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Semiconductor Technology Roadmap
• Source – Semiconductor Industry Association, ( SIA ), USA, Dec. 1994
• Deep Submicron Technology – feature size < 0.25 μm.
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Time-to-Market (Money)
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Cadence, Mentor
Cadence, ViewLogic
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Level of Synthesis Techniques
Combinational Synthesis
Sequential Synthesis
Behavioural Synthesis
Speed of Designer
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Module mux(q, a, b, sel) ;output q ;input a, b, sel ;reg q ;
always @( a or b or sel )begin
if ( sel )q = a ;
else if ( ! sel )q = b ;
elseq = 1’bx ;
end
endmodule
module statement
Input/output port statement
register statement
behaviour statement
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( Register Transfer Level )
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bq
sel
1
0
Module mux(q,a,b,sel) ;output q ;input a, b, sel ;reg q ;
always @( a or b or sel )begin
if ( sel )q = a ;
else if ( ! sel )q = b ;
elseq = 1’bx ;
end
endmodule
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( stimulus )( your design ) ( waveforms )
SimulationModel
( HDL)
SimulationPattern
( vectors)
Intro
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Software simulation ( cont. )
• Advantages of gate-level simulation1. Verifies timing and functionality simultaneously.2. Approach well understood by designers.
• Disadvantages of gate-level simulation1. Incomplete – results only as good as your vector
set ; easy to ignore incorrect timing / behaviour.
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LVS : Layout versus Schematic ( verification )
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