ic testing

IC testing overview

Prepare by Noty Tseng/ChipMOS

The outlines

• Why do need testing• How to test • Testing related equipment • Device introduction • Testing flow introduction : CP , Laser , FT ,Burn-in • Test program development flow • Calibration • Correlation • Failure analysis• Enter test filed by one case study

Why do need testing

• Cost Reduction• Confirm the spec.• Guarantee user’s application• Improve the reliability• Data collection for front-end improvement.• Testing item/condition depend cost and

quality.

How to do testingTester

processorControl

Timinggenerator ALPG Data

SelectorFormatcontrol

AFM Digital compare

Pin card

VO

VI

MUT

DevicePowerSupply

DC para.measuring

system

Temp.control

Algorithmic patterngenerator :Sequence, Addr. , Data control , Frequency

define by ALPG

Addr./Data

multiplexer.

Addr. ,I/Odriver

For Addr/Data

For Data VOH/VOL Vol.

compare

Compare expect data

Min. cycle rate depend

on ALPG fre.

Testing related equipmentMemory Tester :

workstation

Test Head

Hi-Fix

Tester

Frequency , through put , accuracy , reliability

Key Tester spec.Model T5585 T5591 T5592 LM4

Trage Device

SDRAMDDR

RDRAMSLDRAMPBSRAM

DDRRDRAMDDR-II SSRAM

Frequency(Real/DDR) 250/500MHZ 500MHz/1Gpbs 533MHz/1.066Gpbs 143MHzOverall Timing Accuracy +/-300ps +/-150ps +/-100ps +/-500psDRV/CP Skew +/-180ps +/-50ps +/-30ps +/-200psDriver pin 1536 176 576 2176

I/O pin 1152 176 768 1280

Parallel Duts/System 128 16 64 128

Stations/System 2 1 2 2

ALPG Address Bit X:16 Y:16 X:16 Y:16 X:16 Y:16 X:18 Y:18Output Limits(VIH) -1.5 to 8V -1.8 to 5.5VOutput Limits(VIL) -3V to 5V -2.5 to 5VMinimum Pulse 2.0ns /1V 0.9375ns/1.6V 2.5ns/2VTr/Tf(20% ~ 80%) 1ns +/-200ps /1.5V 400ps+/-100ps /1.6V

Output Resistance 50 ohm +/- 3ohm +/-40mA 50 ohm +/- 5ohm +/-25mA or more50 ohm +/- 2ohm +/-25mA or less

50 ohm +/- 5ohm +/-25mA

Input Limits -2 to 7V -2.5 to +5.5V -2 to -6VEquivalent Input Tr 1.2ns /3V 300ps/1.6V

Input Resistance 50 ohm +/- 3ohm +/-40mA50 ohm +/- 5ohm +/-25mA or more50 ohm +/- 2ohm +/-25mA or less 50 ohm +/- 5ohm +/-25mA

Maximum Unit/System 64 to 192 32 to 128 64Output Valtage -6V to 10V -6V to 10V -6V to 16VOutput Current +/-80mA +/-80mA +/-128mAResolution 2mV 2mV N/A

PMU

Features

Advantest

Pin Electronics

Key accuracy definitionOTA ( Overall Timing Accuracy ) :

It’s mean tester to tester accuracy- Clock generator linearity- Pin to pin skew of driver and comparators-Clock to clock skew- Format to format skew-Jitter including mutual interface between clock ,etc.-Response ambiguity of comparator-Response difference between VOH and VOL comparator.

Key accuracy definitionJitter definition : Skew definition :

Testing related equipmentFinal Test :

TSOP/CSP/PLCC package type Handler : 64 duts parallel Hi-Fix :

Testing related equipment

Prober

Tester

Probe Card

Needle and contact area

PCB

Probe card analyzer

Wafer Sort :

Pogo pin

Testing related equipmentBurn In : Burn in board :

Board/Row/Socket isolate

Burn in oven ( ANDO 8652) :

Dynamic , MBT , TDBI

Testing related equipmentLaser : ESI-9350 :

IC introduction

Over 40%

Testing flow introductionWafer sorting

Redundancy repair

Assembly

Burn-in

FT1

Marking

(For memory only)

FT2

FT3

EQC

(Pre B/I loose test , room temp.)( 125C , high voltage. )

( high speed , high temp.)

(Cool temp)

Testing flow introduction (WS )

Probe Card : Probe card quality will effect testing result1. PCB layout 2. Ground 3. Needle

Probe mark :We can know the testing/contact quality from probe mark.

The purpose :1. Screen out the solid failure before Assembly 2. Do redundancy repair analysis before laser trimming. 3. Collect testing result and feedback to process

New Device Setup• Probe File

– Probe card– Wafer– Device name– Wafer size– Chip size (with scribe)– Notch/Flat degree– Temperature– Map (with coordinates)– Gross die– Test configuration

(option Dr, Flash, … )

• Probe Card – Chip size definition (with scribe)– Wiring table– PCB type– Physical DUT layout (top view)– Relay and capacitor connection– PCB mark and Notch/Flat orientation– Pad diagram, coordinates, and size

1 2 3 4

X

Y

scribe

Notch

T10514

PAD1

Notch

1 8 16 25

50 49 27 26

Throughput/Yield vs. Frequency

10%

20%

30%

0% 2% 3%

Yield Improvement

Probe Frequency

Increased from 50 to 100MHz

Probe Frequency

Increased from 30 to 50MHz0%

Thro

ughp

ut

• 64M SDRAM and 1 lot of wafers(25wafers) was tested at 30 MHz,50 MHz and 100 MHz.• Once the wafer tested, the package test was performed to compare the yield data.• Customers see the improved throughput and yield when test speed is increased.

• Probe-One has scalable capture speed up to 250MHz.

Testing flow introduction ( WS)Redundancy cells ( for memory ) :

Testing flow introduction (WS)MRA ( memory repair analysis ) Transfer fail data from AFM to

buffer memory.

Functional test passed ?

STEP 1Determines repairable/unrepairablecondition based on the fail cell count

Unrepairable?

STEP 2Determines line fail repair

Unrepairable?

STEP 3Determines bit fail repair

Unrepairable?

Repairable Unrepairable Repair not needed

Yes

No

Yes

Yes

No

No

No

Yes

Testing flow introduction (WS)AFM ( Analysis fail memory ):

RepairResult file

PRO file name … …Initializes the MRA –II … …Functional test … …Activates repair analysis process … …Loads repair result … …END

Repair analysispeer process

AFMMRA-IIhardware

◆

RepairCondition file

GUI or text editor

CreationTransfer

Initializes AFM

Fetches fail

Starts fail data transfer

Transfer

Creation

Transfersfail data

Repair analysis

Testing flow introduction (WS)Probe Card type :

Epoxy typehigh noise ,larger probe mark

Vertical typelower noise ,small probe mark

Thin-film(W)redistribution

Ceramic

Wafer

Trace

PadProbe tip

Wafer

Chuck

Tester

Test head

Load board

Solder

Testing flow introduction (WS)Probe Card Clean :

Off- line clean : On- line clean :

Too little clean :Adversely yield

Too much clean :Adversely affect throughput Increase production costReduce the life of probe card

Testing flow introduction (Laser)

Laser trimming :

The success factors to Laser :Laser energy , Spot size , laser wavelength , pulse width ,

passivation thickness , fuse pitch , fuse material ,alignment .....

The purpose :Base on WS analysis result to trimming certain fuse to re-decoder

and replace the failure cell by redundancy cell.

Before laser repair During laser repair

Testing flow introduction (Laser)

SiO2: 2000A SiO2: 2000A

Si3N4: 3000A

SiO2: 1000A

TiN: 500A

Al: 3500A

TiN/Ti: 100A/50A

SiO2: 4150ASiO2: 4150A

SiO2: 5000A

Si3N4: 5000A

SiO2: 5000A

Silicon Wafer

FUSEWINDOW

Fuse structure :

Laser parameter definitions

"L" Laser Alignment Target Specifications "T" Laser Alignment Target Specifications

Clear Area (Low reflectivity) Clear Area (Low reflectivity)

Scan Feature (High reflectivity) Scan Feature (High reflectivity)

Laser Scan Laser Scan

Y-Scan

X-Scan

Feature Width

Feature Length

Total Target Length

Total TargetWidth

Target CoordinateClear Area

ScanDelta

Target Coordinate

X-Scan

Y-Scan

Feature Length

Feature Width

Total Target Length

Scan Delta

Clear Area

Link Width

Link Pitch

Link Length

Spot Size

PlacementAccuracy (Acc)

Laser parameter definitions

Initial metal vaporization

Be care to carcakat lower corner

Stress and Crack PI

Liquid splashing( Post rupture process )

Testing flow introduction (FT )The purpose :

1. Temp. testing.2. DC/AC parameter testing3. Speed sorting4. Pattern

Hi-Fix :Hi-Fix quality will effect testing result 1. Socket ( low L is better )2. Wiring technical

I/O Loading effect :1. It can reduce the damping due to mismatch Z .2. Well select loading ( R , C , current loading )3. It related to I/O interface

Loading For Flash :

For SDRAM

For DDR :

Testing flow introduction (FT )Guard band :

1. To allow for any testing inaccuracy 2.To account for the performance degradation with age in the

entire device life span. 3.Guard band content :

Temp / Vol. / Refresh / Any AC/DC parameter.

FT EQC Spec.

24ns 24.5ns 25ns

- test error + test error - test error + test error - test error

Tester error End of life

VCC:5.7V VCC:5.6V VCC:5.5V

Testing flow introduction (B/I )The purpose :

1.Use high temp. / voltage to induce the infant mortality. 2. Get good reliability by burn in process.

How to determined the burn in time:1. Device 2. Burn in voltage3. Burin in temp.4. The customer acceptable failure rate ( FIT ) after burn in.

FIT : 1 failure per 1E9 unit * hours

Testing flow introduction (B/I )

Dynamic MBT TDBIBIB type R * R R

S S* S*B* B B*

Timing W R (by scan) R (by scan)W W

Flow B/IPre-BI test +B/I+Post-BI

Pre-BI test +B/I+testing+Post-BI

singling poor Middle GoodContact detect ARM Scan test Scan test

The Oven comparison :

Testing flow introduction (B/I )Full contact Wafer Level B/I :

Test program create flowDevice characteristic study

Testing flow define

Testing item condition and spec. define

Create test program by AE

Verify the the program by trial run

Buy off the testing result by customer

1.Pattern sensitivity , speed , key AC/DC parameter ,VCC working range,temp.2.Characteristic program can support to got above data.

Refer to following page.

The program structure :

Analysis the failure mode by utility ,like as shmoo , ..

The pass IC will verify by end application customer.

Main program

PatternSocket program

Timing

MRA file

Testing item condition and spec.

VCC FORCE TEST PINS TEST SPEC VIH/VIL VOH/VOL IOH/IOL TIMING PATTERN5 8 Continuity Test (Addr/Ctrl Pins) 0.0v -100ua All Pins -0.2v/-2.0v NA NA NA NA NA6 8 Power Short Test 0.5v 0.5v Vcc Pins 500uA/NA 2.2v/0.0v NA NA NA NA7 7 Input Leakage Addr Test (High) 3.6v 3.6v Addr Pins -1.0ua/1.0ua FIXL(Odd) NA NA NA NA9 6 Gross Function Test 3.0v NA NA NA 3.0v/0.0v 1.5v/1.5v NA STIM3 Row March (#40), Data=Checker Board12 4 VIH Test 3.6v NA NA NA 2.2v/0.8v 1.5v/1.5v NA VHLTIM Scan March (#30)12 4 VIL Test 2.4v NA NA NA 2.0v/0.8v 1.5v/1.5v NA VHLTIM Scan March (#30)13 4 VOL Test 3.6v 2.0ma DQ Pins 0.4v 2.64v/0.0v 1.5v/1.5v NA STIM3 VOL13 4 VOH Test 2.4v -1.0ma DQ Pins 2.0v 2.0v/0.0v 1.5v/1.5v NA STIM3 VOH14 4 TTL Standby Current Test 3.6v 0.3ma Vcc Pins 0.3ma 2.2v/0.8v I/O=FIXH NA NA NA15 4 CMOS Standby Current Test 3.6v 5.0ua Vcc Pins 5.0ua 3.4v/0.2v I/O=FIXH NA NA NA16 4 Operating Current Test 3.6v NA Vcc Pins 20.0ma 2.64v/0.66v 1.5v/1.5v NA STIM12 Dynamic R/W ICC Pattern (#20)

4 Data Hold Retention Test 3.6v NA NA 2.0v 3.4v/0.2v 1.5v/1.5v NA VDRTIM W0 CHK (#D0)4 Data Hold Retention Test 3.6v NA NA 2.0v 3.4v/0.2v 1.5v/1.5v NA VDRTIM R0W1 CHK (#D8)

28 3 AC Test (HV) 3.6v NA NA NA 2.88v/0.72v 2.4v/0.8v -1.0ma/2.0ma CB21NS Row March (#40)22 3 AC Test (LV) 2.7v NA NA NA 2.32v/0.58v 2.4v/0.8v -1.0ma/2.0ma CB21NS Row March (#40)

DC CONDITION AC CONDITION

17

CAT. BIN Test Item

Test program flow designTN=100 & GOSUB CONTIN

TN=200 & GOSUB OUTLKG

TN=300 & GOSUB INLKG

TN=500 & GOSUB FUN60 ;FUNCTION -60

TN=550 & GOSUB(GLOB3) FUNHZ FUNEDO

TN=600 & GOSUB LATCH

Pattern/socket file

****************************************************

;*** MARCH ROW <XMARCH> ***

;****************************************************

START #10

NOP INIT

IDXI1 6 CHLD COUT /T4 ;INIT

NM: JNI2 . CINC COUT W /T2 ;WRITE

NOP CHLD COUT R /T1 ;READ

NOP CHLD COUT W /D /T2 ;WRITE

JNI2 .-2 CINC COUT R /D /T1 ;READ

NOP CHLD COUT R /D AINV /T1 ;READ

NOP CHLD COUT W AINV /T2 ;WRITE

JNI2 .-2 CINC COUT R AINV /T1 ;READ

JZD NM ACLR

STPS

SOCKET S404K ;SOCKET FILE FOR 104/404 ON T5365 32 DUTS

A0=9

A1=8

A2=7

A3=10

A4=PD26=66

A5=PD25=65

DEFINE MULTIPLE 32DUT 1STN

BIT 4

PPS 1

PIN MODE=B

CHTYPE2

HANDLER

DUT# =VS1 ,PD1-12 ,PD65-68 ,P33-36

DUT1 =PPS1 ,PD1-12A1 ,PD65-68A1 ,P33-36A

DUT2 =PPS2 ,PD13-24A1 ,PD77-80A1 ,P41-44A

DUT3 =PPS5 ,PD1-12B1 ,PD65-68B1 ,P33-36B

DUT4 =PPS6 ,PD13-24B1 ,PD77-80B1 ,P41-44B

END

Timing setsST40RW:;TRCDMIN & EARLY WRITE2 & RMW

; TS1 TS2 TS3 TS4 TS5

; (READ) (WRITE) (RMW) (REFRESH)(PAUSE)

RATE = 71NS 75NS 110NS 71NS 1MS

; WSTRB1= 65NS+TR6 71NS:2,65NS+TR6 74NS ,65NS+TR6 71NS:2

WSTRB1= 63NS+TR6 69NS:2,63NS+TR6 72NS ,63NS+TR6 69NS:2

RASST= 25NS 25NS 25NS 25NS OPEN

RASSP= 65NS 65NS 100NS 65NS OPEN

CASST= 42NS 42NS 51NS OPEN :2

CASSP= 65NS 85NS 101NS OPEN :2

XADST= 22NS 22NS 22NS 22NS :2

XADSP= OPEN OPEN OPEN OPEN :2

YADST= 39NS 39NS 43NS 39NS :2

YADSP= 58NS 58NS 61NS 58NS :2

WEST = 71NS 39NS 86NS OPEN :2

WESP = 107NS 55NS 91NS OPEN :2

OEST = 51NS OPEN 51NS OPEN :2

OESP = 65NS OPEN 74NS OPEN :2

DINTR= 0NS 0NS 0NS 0NS :2

DINST= 20NS 39NS 83NS 20NS :2

DINSP= 40NS 58NS 94NS 40NS :2

DREL1= 0NS 39NS 83NS 0NS :2

DRET1= 10NS 58NS 94NS 10NS :2

Main program+------------------------------------------------------+

;| FUNCTION TEST [ TRCDMIN & EARLY WRITE1] |

;+------------------------------------------------------+

FUN60:

GOSUB SVIN1 ;SET VOLTAGE

GOSUB ST60A ;SET TIMING

GOSUB SPIN1 ;SET PIN CONDITION

CALL CALB("C404H", CA1) ;CALIBRATION POINT

VS1=VCCTYP ;VCC= 5.0V

REG MPAT PC=#330

TEST TN

MEAS MPAT P404

GOTO CONTINUE

Main program ( cont.);========================================================

; CATEGORY & SORT TABLE

;========================================================

STABL:

CATEGORY TABLE

CATEGORY1= PT(AND101-112,125-126,133-136,233-236,243-246,@

,301-312,325-326,333-336,343-346,361-372,385-386,@

,500,550,600);PASS

CATEGORY3= FT500 ;MARCH COLUMN

CATEGORY5= FT550 ;HZ/EDO FAIL

CATEGORY7= FT(OR 100-199) ;CONTINUITY

CATEGORY8= FT(OR 200-299) ;OUTPUT LEAK

CATEGORY9= FT(OR 300-399) ;INPUT LEAK

CATEGORY10= FT600 ;LATCH-UP

CATEGORY END

SORT TABLE

SORT2(FAIL)= NC5

SORT3(FAIL)= NC(OR8-9)

SORT4(FAIL)= NC3

SORT5(FAIL)= NC10

SORT7(FAIL)= NC7

SORT1(PASS)= NC1

SORT END

Testing time

Factors to increase testing time :1. Memory size ( 4M x16 ) , 4M is memory size ,

but not 64M 2. How many testing Patterns use ( MR ,MC , CB , ,… ) 3. What’s kind pattern use ( 4N, 8N , NxN ,.. ) 4. What’s testing cycle rate used ( 5ns , 6ns , 10ns , 60ns,. )

Calibration Autocalibration independent on Test Program :

- Linearly of all edge output by timing generator- Driver output level offset- Comparator reference offset

For tester any errors inherent and activates the system auto after power on 30 mins.

Autocalibration dependent on Test Program :- Driver pin-to-pin skew- Comparator pin-to-pin skew- Skew between driver and comparator- Driver I/O timing.

Autocalibration dependent on Test Program

Test Program∫

CALL CALB

MEASURE

∫

CALL CALB

MEASURE

∫

END

Create calibration file

File

Transmission of the data tocalibrate timing

Collection of thedata to calibratetiming

Collection of thedata to calibratetiming

Transmission of the data tocalibrate timing

Transfer calibration file

t

1st 2nd 3rd nth time

Autocalibration dependent on Test Program

MAIN Program ∫

Test Condition Setting

∫

CALL CALB

MEASURE

∫

Test Condition Setting

∫

CALL CALB

MEASURE

∫

END

1 st path․Calibration Data generation

․Create the data file after 2 nd path․Transfer Calibration file

Other file creation

Auto Calibration Program

Autocalibration dependent on Test ProgramSTART

1st path

Has 10 min.elapsed?

2℃ change?

Transfer calibrationdata to CAL SYSTEM

Create calibrationdata file

END

NO

NO

YES

YES

YES

NO

Performance Board data

Target delay (Δt/2)auto calculated

Probe termination

Measured circuit Open

Reflected signalinput trigger

TEK CSA 803C

PB data : It’s signal delay time of Hi-Fix

CorrelationCorrelation :

In order to get uniform testing result at differenttester , Hi-Fix, probe card and dut , we must verify if theperformance of key parameter in reasonable divergence between tester , Hi-Fix , prober Card and dut.

The divergence spec. :It dependent on tester accuracy. More higher frequency

tester should have better accuracy.

Problem :Tester accuracy is not good for device speed /parameter now.

It will cause larger difference testing result for some margin lots.

Correlation procedureVerify the wiring

Verify the Hi-Fix to Hi-Fix , P.C. to P.C. key parameter

Verify the tester to tester key parameter

Program offset

Bin to Bin confirm for tester, P.C. Hi-Fix

Trail run

Verify Dut to Dut key parameter

Enable one dut every time

Select pass and fail bin some sample

Base on above data for program offset

3-5 lot trail run

Key parameter :DC : Voh/Vol , VCC , Vih/Vil ,..

AC : Speed, tSETUP ,tHOLD ,..

How to got parameter data :

By Eng manualBy characteristic program

Failure analysis Fail bit map analysis :

Failure analysis 2/3D Shmoo plot :

***** SHM2 REV.03

DATE: 2001/04/13 TEST: 220

SAMPLE#: 263 SHMOO#: DUT#: 1

DEVICE: TCN128KX36 LOT#:

COND: FUNC: MPAT P1TCND1

FUNC: PC #00000030

X-AXIS: RATE1<2> X-DELT= 2.000NS

Y-AXIS: VCC VS1 Y-DELT=-100.0MV

32.00NS 52.00NS 72.00NS ()

(VCC) V

+---------+---------+-

4.200V +. .** . . ***********+

4.100V !. ** ***********!

4.000V >!. *** ***********!<

3.900V !. *** ************!

3.800V !. *** ************!

3.700V +. .***. .************+

3.600V !. *** ************!

+---------+---------+-

^

32.00NS 52.00NS 72.00NS ()

Failure analysis Data Log :

TEST PROGRAM :F256TC1C REV.:1.0C

BS62LV256 TEST PROGRAM FOR FT1(25^C,R.T.) TEST

TECN PROGRAM RELEASE DATE 2001/03/19

DATA LOG PRO F256TC1C AT 2001/04/03 13:57:19

DEVICE: SAMPLE: 1 LOT NO:

DUT I/F: TESTER: 0-1 OPERATOR:

COMMENT: F256TC1C 25^C 03/19/2001 REV: C

TEST GO/NOGO DATA UPPER LOWER PIN/VS DUT

0600 U-FAIL 32.38MA 30.00MA ........ VS1 DUT1

0600 U-FAIL 32.24MA 30.00MA ........ VS1 DUT2

0600 U-FAIL 31.72MA 30.00MA ........ VS1 DUT3

0600 U-FAIL 31.60MA 30.00MA ........ VS1 DUT4

0600 U-FAIL 32.50MA 30.00MA ........ VS1 DUT5

0600 U-FAIL 31.64MA 30.00MA ........ VS1 DUT6

0600 U-FAIL 32.06MA 30.00MA ........ VS1 DUT7

0600 U-FAIL 32.34MA 30.00MA ........ VS1 DUT8

0600 U-FAIL 32.88MA 30.00MA ........ VS1 DUT9

0600 U-FAIL 31.38MA 30.00MA ........ VS1 DUT10

0600 U-FAIL 32.52MA 30.00MA ........ VS1 DUT11

0600 U-FAIL 32.28MA 30.00MA ........ VS1 DUT12

0600 U-FAIL 32.08MA 30.00MA ........ VS1 DUT13

0600 U-FAIL 31.90MA 30.00MA ........ VS1 DUT14

0600 U-FAIL 32.36MA 30.00MA ........ VS1 DUT15

0600 U-FAIL 32.06MA 30.00MA ........ VS1 DUT16

0600 U-FAIL 32.00MA 30.00MA ........ VS1 DUT17

0600 U-FAIL 32.08MA 30.00MA ........ VS1 DUT18

0600 U-FAIL 31.70MA 30.00MA ........ VS1 DUT19

TOTAL TEST TIME = ********

Enter testing filed

How to improve your EQC reject for customer ?

Let’s enter testing field by following case study !

1.Theme:

How to reduce 64M SDRAM QC reject rate

Author: Noty tsengSupporter: Lydia ChenDate: May.10,1999

1.The theme selected 2.Reason for selecting 3.Present situation 4.Cause analysis

5.Evaluation & Execution 6.Confirmation 7.Standardization 8.Remaining problem

QC story

2.Reason for selecting:

2-1. 64M SDRAM is the major product in production.

2-2. The QC reject rate is higher than the other product.

2-3. The retest responsibility is not very clear to assume.

2-4. On duty engineer spent much time to do failure analysis and disposition.



QC story

3-2. Testing Flow:



QC story

Burn - in 125oC 24hrs

FT3 -10oC 3mins soak

FT2 85oC After B/I test(Tighten)

FT1 85oC pre-B/I test

EQC 85oC sampling

(Loose)

5-2 Temperature issue:5-2-1: Soaking time5-2-2: Testing temperature:

5-3 Mix issue:5-3-1: Operator mis-handling :

5-4 Escape issue:5-4-1: Tester and Handler got abnormal:

5-5 program issue:5-5-1: Operator mis-keyin:5-5-2: Runcard error:



QC story



QC story

5-6 Device issue: There were many experiments to be executed:

5-6-1:Exp1

purpose: Compare the different EQC reject rate by FT2 retest parts( if auto retest or not )Procedure:

a. Select 100 lots to do the experimentb. In FT2 step,don’t combine the retest parts.(Just 1st pass parts go to next step)c. Calculate the final QC reject rate in the experiment.

FRN(A): The total lots processing QC step in the experiment period.FRE(B): The 97 lots in experiment.

A normal flow (auto retest fail parts) FT3 Making EQCFT1 B/I FT2

B no retest fail parts Pass FT3 Making EQC

Fail



QC story

The average QC rate rate in experiment period is 1.6%

But the QC reject rate for the 97 experiment lots is “0%”

period 3/17-3/28 3/28-4/01 4/10-4/20 4/30-5/04Total Lot In 304 97 288 195

QC reject lot 4 1 5 4

QC reject rate 1.32% 1.03% 1.74% 2.05%

1.32%1.03%

1.74%2.05%

0.00%

0.50%

1.00%

1.50%

2.00%

2.50%

3/17-3/28 3/28-4/01 4/10-4/20 4/30-5/04

Period

QC reject rate in experiment period

QC reject rate



QC story

5-6-2:Exp2

purpose: Compare "2nd Pass" FT2 devices' stabilityProcedure:

a. Select 20 lots to do the experimentb. In FT2 step,separate the 1st fail parts.c. Retest 1st fail parts (using FT2 program)==>2nd Passd. Retest 2nd Pass parts (using FT2 program) every 3 days

FRN: All lots in production that we except there is no any device got rejected for retestingusing the same test program

FRE: The 2nd Pass parts of selected 40 lots in experiment.

FT2 2nd Pass 100% FT2 100% FT2100% FT23 days 3 days3 days

SWR:9904043,LOT:ERT0412AADate handler Input pass fail BIN1 BIN2 BIN4 BIN5 BIN6 BIN7 BIN84/16 K39/40 1080 1026 54 0 2 52

4/20 K39/40 1080 1015 65 10 1 1004 0 3 1 61

4/23 K39/40 1080 1017 63 7 0 1010 0 1 0 62

5/10 K39/40 1080 995 85 1 0 994 0 18 2 65



QC story

Shmoo solid fail

Y i e l d T r e nd

9 5 .0 0 %

9 3 .9 8 % 9 4 .1 7 %

9 2 .1 3 %

9 0.0 0%

9 2.0 0%

9 4.0 0%

9 6.0 0%

9 9 /4 /1 6 9 9 /4 /1 9 9 9 /4 /2 2 9 9 /4 /2 5 9 9 /4 /2 8 9 9 /5 /1 9 9 /5 /4 9 9 /5 /7 9 9 /5 /1 0

y ield 線性 (yield )

y ield 9 5 .0 0 % 9 3 .9 8 % 9 4 .1 7 % 9 2 .1 3 %

4 /1 6 4/2 0 4 /2 3 5/1 0



QC story

5-6-2:Exp3

purpose: Compare ”1st Pass" FT2 devices' stabilityProcedure:

a. Select 3 lots to do the experimentb. In FT2 step, just the1st pass parts go to next step.c. After QC step,select 1080ea to do retest FT2 test program every 3 days.

FRN: The 2nd Pass parts of selected 40 lots in experiment.(EXP2)FRE: The 3 lots in the experiment.



QC story

P9037LBRADate Input pass fail BIN1 BIN2 BIN4 BIN5 BIN6 BIN7 BIN84/17 1080 1080 0 22 1 1057 0 0 0 0

4/20 1080 1080 0 13 4 1063 0 0 0 0

4/23 1080 1080 0 11 0 1069 0 0 0 0


4/20 1080 1079 1 14 1 1064 1 0 0 0

4/23 1080 1079 1 10 0 1069 1 0 0 0


4/20 1080 1080 0 15 2 1063 0 0 0 0

4/23 1080 1080 0 13 0 1067 0 0 0 0

The there lots got very stable phenomenon. There is no more worst phenomenon happen by days.



QC story

Time

Failure rate

1st pass (Expected)2nd pass

Early Death Curve

ic testing

Documents