DESIGN OF FMO AND MANCHESTER ENCODING TECHNIQUES FOR DSRC

APPLICATIONS

Presented by

G.Raghul

P.G scholar - VLSI Design

V.S.B Engineering College,Karur

Guided By

Mrs.R.Dhayabarani, Mr.R.Vivek,

Associate Professors,Department of ECE, V.S.B. Engineering College,Karur

DESIGN OF FMO AND MANCHESTER ENCODING TECHNIQUES FOR DSRC

APPLICATIONSAbstract: To design the encoding techniques such as (i)FMO(Flexible

Macro Block Ordering) (ii) Miller Encoding for DSRC application.

The coding diversity between FMO/Manchester coding limits the design of VLSI architecture of both codings.

Using SOLS(Similarity Oriented logic Simplification) technique, the diversity was eliminated.

It also used to achieve HUR(Hardware Utilization Rate) as 100%.

DESIGN OF FMO AND MANCHESTER ENCODING TECHNIQUES FOR DSRC

APPLICATIONSSYNOPSIS• DSRC (DEDICATED SHORT RANGE COMMUNICATION)• ENCODING TECHNIQEUS USED IN DSRC APPLICATION• FMO ENCODING AND MANCHESTER ENCODER• HARDWARE UTILIZATION OF FMO AND MANCHESTER

ENCODER• HARDWARE ARCHITECURE OF FMO AND MANCHESTER

ENCODER• VLSI ARCHITECTURE OF FMO AND MANCHESTER

ENCODINGS USING SOLS TECHNIQUE• PERFORMANCE EVALUATION • RESULT ANALYSIS

DSRC-DEDICATED SHORT RANGE COMMUNICATION

• Dedicated Short Range Communication is a simplex or duplex short range to medium range wireless communication.

• Specially for automotive vehicles.• Categorized as (i) vehicle to vehicle (ii)vehicle to road-side

communications.• The vehicle to vehicle communication involves message

sending for public safety and information announcement. • The vehicle to road side communcation involves intelligent

transportation service as Electronic Toll Collection (ETC) Parking-service, Gas-refueling.

DSRC-DEDICATED SHORT RANGE COMMUNICATION

• BLOCKS

ENCODING TECHNIQEUS USED IN DSRC APPLICATION

• The reliability of the signal is too important in vehicle-safety issues.

• To increase the signal reliability the DC-balance take major role in DSRC.

• The purpose of DC-balance is to keep the information as constant on both transmitter and receiver.

• Hence the DC-balance enables the receiver architecture to become more efficient and feasible.

• The FMO,Manchester,Miller encodings are used to achieve this DC-balance in DSRC

FMO ENCODING

• Fmo encoding consist of two parts (i) A-former half cycle of CLK (ii)B-later half cycle of CLK.

CODING RULES OF FMO

(i)The FMO code must allow the transition between A and B, when X is the logic-0.

(ii)There is no transition is allowed between A,B,when X is logic-1.

(ii)There must be a transition between two consecutive input datum

HARDWARE UTILIZATION OF FMO AND MANCHESTER ENCODER

• The hardware utilization of FMO and Manchester is derived from hardware architectures of both encoder.

• The hardware architecture of Manchester is simply XOR operation as X xor CLK.

• It is too difficult to design the hardware architecture of FMO encoder.

• It is designed by the FSM of FMO encoder.

FSM,TRANSITION TABLE OF FMO

PREVIOUS STATE CURRENT STATE

A(t-1) B(t-1) X=0 X=1

A(t) B(t) A(t) B(t)

0 0 1 0 1 1

0 1 0 1 0 0

1 0 1 0 1 1

1 1 0 1 0 0

HARDWARE ARCHITECURE OF FMO AND MANCHESTER ENCODER

• From the hardware architecture the boolean expression is derived as

A (t) = ~B(t-1)

B (t) = X B (t-1)• The boolean expression of

FMO encoder is

CLK A (t) + B (t) (~ CLK)

SOLS TECHNIQUE• The similarity oriented logic simplification classified as

(i)Compact of Area with Retiming (ii) Sharing of Logic Operation.

SOLS TECHNIQUE• The transistor count of the FMO encoding architecture without and

with compact of area retiming are followed as 72,50.• Thus it reduces 22 transistors.

(ii)SHARING OF LOGIC OPERATION• The Manchester encoding denoted as X CLK and it is also equal

to X (~CLK) + (~X) CLK.Using multiplexer, it is shown as FMO code CLK A (t) + B (t) (~ CLK)

Manchester code CLK (~X) + X(~ CLK)

SHARING OF LOGIC OPERATION

• The concept of sharing of logic operation is to integrate (~X) into A(t) and X into B(t).

• The logic for A(t)/(~ X) and B(t)/X are derived as

SHARING OF LOGIC OPERATION

VLSI ARCHITECTURE OF FMO AND MANCHESTER ENCODINGS USING SOLS

TECHNIQUE

PERFORMANCE EVALUATION

• HARDWARE UTILIZATION RATE(HUR)

Coding

Active Components(transistor

count) / Total Components(transistor

count)

HUR

FMO 6 (86) / 7 (98) 85.71%

Manchester 2 (26) / 7 (98) 28.57%

Average 4 (56) / 7 (98) 57.14%

Coding

Active Components(transistor

count) / Total Components(transistor

count)

HUR

FMO 5 (44) / 5 (44) 100%

Manchester 5 (44) / 5 (44) 100%

Average 5 (44) / 5 (44) 100%

RESULT ANALYSIS

• The SOLS technique eliminates the limitation on hardware utilization by two important techniques.

• Using compact area retiming the number of transistor is reduced as 22.

• Using logic operation sharing,the HUR was achieved as 100%.• The maximum operation frequency of both Manchester and

FMO encodings are 2 GHz,900 MHz.• The power consumption of Manchester and FMO encodings

are 1.58 mW,1.14 mW.