rwires between the plug in the middle and the end of the cable (sdrives) do exist. But, "~1:1-~ n

Chapter 3] . Hard Disk Drives

select 3 and drive select 4 are not used, so you may

Of all hard disk interfaces used on the PC, the ST412/506 Is the least «intelligent». It is a puresignal Interface, thus the controller Is unable to pass any command to the drive. The drive Itselfaccommodates only the control circuitry for stabilizing the disk rotation and the head position-ing. All other control functions are carried out by the controller Itself, for example, Interpretationof the commands from the PC system, the encoding and decoding of the read and write data,the generation of address marks, etc.

ST412/506 controllers and drives were used first in the XT, and later also in the AT. Because theXT BIOS was not designed as standard for the support of hard disks, all XT controllers musthave their own BIOS with the hard disk functions of INT 13h. The start address of this BIOSextension Is usually c8000h. The AT, on the other hand, supported hard disks from the first day,and the required routines are already Implemented In the system BIOS at address fOOOOh. Butthere are other differences between XT and AT controllers with an ST412/506 Interface:

- The XT controller uses DMA channel 3 for transferring data between sector buffer and mainmemory; In the AT, on the other hand, the BIOS carries out a programmed I/O by meansof the port instructions IN and OUT without using any DMA channel

- The XT controller employs IRQ5 for Issuing a hardware interrupt; the AT controller IRQ14.- The XT controller is accessed via the XT task file, the AT controller via the AT task file; the

register assignment and addresses of these +™m t-^v &\~~ ----XT

_ _..«vucx via me AI tasK tile;

icgwiei assignment and addresses of these two task files are Incompatible; drivers forhard disk controllers with an ST412/506 interface cannot be used for an AT controller.The commands for an XT controller always consist of a 6-byte command block to a singleregister; the AT controller, on the other hand, k r»rr»n-^~™-j *--—^^^x, on the other hand, is programmed by means of single commandbytes to several individual registers.

Connecting and Confiiluring ST412/506 Hard Disk Drives

The

the control cable, an eventual second h d di kto h ^ ** ^ ** t0 *" ™d °f

a control cable without twisted w^ Aen on T"**" " ** ^ ff >™ a r e us in§drive select 1 by m e a n s of t h e ^ s o ^ d l ^ * G M *** 8ekct ° a n d * * * D: as

cable with twisted wires then y o u Z c o t f ' T ^ * * ^ " y ° U a r e U s i n§ a «>"**for floppy d r ive , B e c a u s e ^ S ^ T ^ ^ ^ 3S *** "** h as JL the caseenabled. exchange of t l l e s e I e c t signals, the intended disk is always

3 1 ! 3 The ESDI int@

ESDI was conceived by Maxtor In 1983 as a powerful and intelligent successor to the ST412/506interface. The main problem of the long transfer distances between hard disk and data separ-ator was solved, In that ESDI already Integrates the data separator on the drive.

883

bDUl Is designed for a transfer rate of up to 24 Mbits/s between drive and controller; typically10-15 Mbits/s are achieved. ESDI hard disks use the RLL method for data encoding. Further-more, an ESDI controller is Intended for connecting up to seven ESDI drives, and may accessard disks with a maximum of 64 heads In four groups of 16 heads each, as well as a maximum

of 4096 cylinders. The controller of Its predecessor Interface (ST412/506), on the other hand,allowed a maximum of only 16 heads and 1024 cylinders.

An ESDI controller may also pass complete commands which are decoded and executed by thedrive. On the other hand, the generation of address marks, synchronization pattern and thedecoding of the NRZ into parallel bit data for the PC system bus are carried out by the control-ler. Thus an ESDI controller Is neither a pure controller which takes over all control functions,nor a host adapter which solely establishes a connection to the system bus; instead, it Is some-thing like an intermediate product between controller and host adapter. ESDI signals and ESDIcommands will not be discussed here because the interface Is already outdated.

For the connection of ESDI hard disks, in principle the same rules as for an ST412/506 driveapply. First you must configure the drives, that Is, adjust their ESDI address. Because of thedifferent uses of the cable wires and the binary encoding of the drive address on the controlcable, no cables with twisted wires are available for ESDI to free you from this drive configu-ration. With ESDI you always need to assign every drive an ESDI address. However, It Is notsignificant here which plug of the control cable you connect with which ESDI drive.

31.6 Drives with IDE, AT Bus or ATA Interface

Recently, a new hard disk interface standard was established for PCs which is overtaking theST412/506 standard more and more: the so-called IDE or AT bus interface. IDE Is the abbrevia-tion for intelligent drive electronics ~ an Indication that the connected drives are intelligent ontheir own. With the conventional controller-hard disk combination, the drive itself has onlythose electronic elements required to drive the motors and gates of the drive. The more exten-sive control for executing commands (for reading a sector, for example, a head seek, the readingof the encoded signals, the separation of data and clock signal, the transfer into main memory,etc. must be carried out) Is taken over by the electronic equipment on a separate adapter, thatis, the hard disk controller. Thus the drive itself is rather «stupid». A further disadvantage ofthis solution Is that the still encoded signals must run from the drive via the data cable to thecontroller to be decoded there. The transfer path worsens the signals; a high data transfer ratebetween drive and controller falls because of the relatively long signal paths. Further, the ex-ploding market for hard disk drives gave rise to a nearly infinite variety of drive geometries andstorage capacities, so that a separate controller (which possibly comes from a third-party manu-facturer) Is simply overtaxed to serve all hard disk formats.

The falling prices for electronic equipment during the past few years, in parallel with a remark-able performance enhancement, gave a simple solution: modern and powerful hard disk drivesalready integrate the controller, and It Is no longer formed by a separate adapter card. Thesignal paths from disk to controller are thus very short, and the controller can be adapted In anoptimized way to the hard disk It actually controls. The IDE and SCSI Interfaces follow this

I of integrating drive and controller into a single unit. But SCSI has another philosophy

884 Chapter; f

In other aspects; details concerning SCSI are discussed in the next chapter. ESDI, as a midcj,course, integrates the data separator on the drive but the rest of the controller (for example, f|sector buffer and drive control) Is still formed on a separate adapter.

The IDE Interface (discussed In the following sections) lies, In view of its performance, betweerthe conventional solution with a separate controller and an ST412/506 interface to the drive oithe one side, and the SCSI and ESDI hard disks as high-end solutions on the other.AT the end of 1984, Compaq Initiated the development of the IDE Interface. Compaq was-looking for an ST506 controller which could be directly mounted onto the drive and connectedto the main system by means of simple circuitry. In common with hard disk manufacturers suclias Western Digital, Imprimis and Seagate, the AT bus Interface arose In a very short time. Toomany cooks spoil the broth, and so in the beginning Incompatibilities were present everywhere, -To take remedial action several system, drive and software manufacturers founded an interestgroup called CAM (common access method), which elaborated a standard with the name ATA(AT attachment) In March 1989. Besides other properties, the command set for IDE drives wasalso defined. As well as the 8 commands with several subcommands already present on theAT controller, 19 new commands were added, which mainly refer to the drive control in viewof low power consumption. For example, the sleep command for disabling the controller andswitching off the drive If no access has been carried out for a while Is one of these. AppendixH lists all the necessary and optional commands. Today, all manufacturers orient to this speci-fication, so that Incompatibilities are (nearly) a thing of the past. You may use the terms AT bus, 'IDE and ATA synonymously. An extension to the standard with a higher transfer rate, and alsoto drives with removable mediums (especially CD-ROM), Is presently in preparation, and will ••be called Enhanced IDE; this seems to be a response to the triumph of SCSI However, moreflexibility and higher performance aren't at all bad for IDE either.

'sical CPU-Drive interface

IDE is a further development of the AT controller with an ST506 Interface so that the AT bus -hard disks orient to the register set and the performance of such hard disks. Thus, IDE is alogical interface between system and hard disk, and accepts high-level commands (for example,read sector or format track). ESDI and ST412/506, on the other hand, are physical interfaces -between controller and drive and refer, for example, to the control signals for the drive motorsto move the head to a certain track. As with IDE the controller and hard disk form an insepa-rable unit, it is the job of every manufacturer to design the control of the drive and the transferof the data. The definition of a physical Interface Is therefore obsolete.

The physical connection between the AT bus in the PC and the IDE Interface of the drives (orbetter, the controllers on the drives) Is established by a so-called host adapter. The motherboardplays the role of host here. The host adapter accommodates only a few buffers and decodercircuits, which are required to connect the IDE drives and the AT system bus. Newer mother-boards already Integrate these host adapters, otherwise they need a separate adapter card whichIs Inserted Into a bus slot. Many host adapters further have a floppy controller so that they areoften called an AT bus controller. That's not correct as the controller is located Immediately onthe board of the drive; the adapter only establishes the connection between the drive and system

885

bus. To the system and you as a programmer, the AT bus drives appear to be the usual con-trollers and drives with an ST412/506 interface which had been operating in your PC up to now.Thus AT bus drives can be accessed by the routines of INT 13h implemented in the conventionalAT BIOS. Unlike ESDI or SCSI hard disk drives, no BIOS extension is required.For connecting the drives, only a single 40-wire flat conductor cable is used, with which youconnect the host adapter and the drives. The IDE interface can serve a maximum of two drives,one of which must be the master, and the other the slave (adjust the jumper or DIP switchaccordingly). The master drive is assigned address 0, the slave address 1. Table 31.10 lists theassignment of the 40 wires and the signals running on them.

pin 20 of the cable Is locked to avoid a mlsinsertion of the plug. Most of the 40 IDE lines aregrounded or can be directly connected to the AT system bus. This explains the name AT businterface. Between host adapter and IDE drive there are only five signals, CSlFx, C83Fx,SPSYNC, DASP and PDIAG, which control the IDE drives and are not connected to the ATbus. The two first signals CSlFx and CS3Fx are chip select signals generated by the host adapterto select the register group with the base address If Oh or the register group with the baseaddress 3f0h. The meaning of the accompanying registers is described below.With the spindle synchronization signal SPSYNC the spindle motor rotation of master and slavecan be synchronized. This Is advantageous If, for example, drive arrays are formed or a mirror-ing is carried out. But many IDE drives don't Implement this, and the SPSYNC pin Is not used.The two signals DASP (drive active/slave present) and PDIAG (passed diagnostic) return ac-knowledge signals by the slave to the master during the course of Initialization. Also, thesesignals are not implemented in many older IDE models manufactured before trie ATA standardbecame effective. That's not very serious; only some diagnostics routines are not always ex-ecuted correctly. If your diagnostics software reports-some obscure errors, although your driveshave been running error-free for several months, then the reason may be the lack of one or bothsignals.

An optional but, nevertheless, important signal Is IORDY. With a low level a drive can informthe CPU that it requires additional clock cycles for the current I/O cycle, for example, forreading the sector buffer or transferring the command code. The CPU then inserts wait states.But many IDE drives don't use this signal, and always fix the corresponding line at a high levelFor performance enhancement the IDE standard defines two more signals, which were not tobe found on an ST506 controller In the original AT: DMARQ (DMA request) and DMACK(DMA acknowledge). In the AT, the data exchange between main memory and the controller'ssector buffer was not carried out via a DMA channel, as was the case on the PC/XT, but bymeans of the CPU; a so-called programmed I/O (PIO) Is executed. If, for example, a sector is tobe read, then the sector data read Into the sector buffer Is repeatedly transferred via the dataregister into a CPU register by an IN instruction, and from there into main memory by a MOVinstruction, until the sector buffer is empty. Thus the AT controller didn't carry out a DMAtransfer, and therefore didn't provide any DMA control signals. As with modern and powerfulDMA chips, the transfer rate between sector buffer and main memory Is much higher (a factor°f two can readily be achieved) and the development of multitasking systems like OS/2 requesta relief from such «silly» data transfer operations, the two optional DMA control signals are

Chapter] Hard Disk Drives887

IDE signal p j n Signal meaning

RESETGNDDD7DD8DD6DD9DD5

DD10DD4DD11DD3

DD12DD2DD13DD1

DD14DDODD15GND2)

DMAQ3)

GND_DiOWGNDDIORGND

IORDY3)

DMACK3)

GND

!NTRQ_

IOCS16D A 1 _

PDIAGDAODA2__

CS|FxCS3FxDASPGND

1234567

1011121314

l* 1516171819202122232425262728293031323334353637383940

reset drivesgrounddata bus bit 7data bus bit 8data bus bit 6data bus bit 9data bus bit 5data bus bit 10data bus bit 4data bus bit 11data bus bit 3data bus bit 12data bus bit 2data bus bit 13data bus bit 1data bus bit 14data bus bit 0data bus bit 15groundpin 20 markDMA requestground

write data via I/O channelgroundread data via I/O channelgroundI/O access complete (ready)spindle synchronizationDMA acknowledgegroundinterrupt request16 bit transfer via I/O channeladdress bus 1passed diagnostic from slaveaddress bus 0address bus 2chip select for base addr. 1fOhchip select for base addr. 3f0hdrive active/slave presentground

AT signal

RESET DRV1)

SD7SD8SD6SD9SD5SD10SD4SD11SD3SD12SD2SD13SD1SD14SDOSD15

DRQx

IOW

IOR

IOCHRDY

DACKx

[ R Q x _I/OCS16SA1

SAOSA2

1) inverted signal of AT bus signal2) pin locked to prevent incorrect insertion of plug3) optional

Signaldirection

host~»drive

bidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectionalbidirectional

drive->host

host—>drive

host-»d rive

drive-^hostdrive-»drivehost-^drive

cfrive-»hostdrive-»hosthost-^d rivedrive-»drivehost—xdrivehost-»drivehost-^drivehost-xirivedrive-»host

implemented in the new IDE standard. Some AT bus hard disks can be instructed by a softwarecommand or a jumper to use a DMA channel instead of PIO for exchanging data between sectorbuffer and main memory. But as the programmer, you must then take into account the prepar-ations for carrying out such a DMA transfer.

The integration of the controllers on the drives makes it possible to integrate more intelligenceinto the hard disk control To this belongs, for example, intelligent retries if an access has failed.It is especially important that many IDE drives carry out an automatic bad-sector remapping.Usually, you can mask defective sectors and cylinders during the course of a low-level format-ting process via the defect list, and use error-free alternative sectors and tracks instead. But if,after such a low-level formatting, a sector or track is damaged, the mapping is no longer pos-sible and the sector is lost for data recording. This becomes fiendish, especially in the case ofsneaking damage. The controller then always needs more retries to access the sector concernedcorrectly. Using the in-built retry routine, the operating system seldom recognizes anythingabout this as the data is read or written correctly after several retries. But at some time the pointis reached where even the retry routine is overtaxed, the sector is completely inaccessible, andall data is lost. Many IDE drives are much more clever: the controller reserves several sectorsand tracks of the hard disk for later use during the course of bad-sector remapping. If thecontroller detects several failed accesses to a sector, but finally leads to a correct data access,then the data of the sector concerned is written into one of the reserved spare sectors and thebad sector is marked. Afterwards, the controller updates an internal table so that all futureaccesses to the damaged sector are diverted to the reserved one. The system, or you as its user,doesn't recognize this procedure. The IDE drive carries out this remapping without any inter-vention, in the background.

The emergence of battery-powered laptops and notebooks gave rise to the need for power-saving drives. In a computer, powerful hard disks are one of the most power-consuming com-ponents, as they require strong current pulses for fast head seeks, and unlike floppy drives thehard disks are continuously running. Most specialist drives for portable computers can beswitched off or disabled by software commands to minimize power consumption. Also, for theIDE hard disks according to the ATA standard such commands are optionally implemented. Inthe order of decreasing power consumption such hard disks can be operated in the active, idle,standby and sleep modes. Of course, it takes the longest time to «awaken» a drive from sleepinto the active state. For this purpose the disk has to be accelerated from rest to the operationrpm, the head must be positioned, and the controller needs to be enabled.

3162 Features of IDE Hard Disk Drives

Intelligent drives with an embedded controller, the most powerful among all IDE hard disks,carry out a translation from logical to physical geometry. The high recording density allowsdrives with up to 50 sectors per track in the outer zone with a large radius. IDE hard disks runvirtually exclusively with an interleave of 1:1. To reduce the average access time of the drives,some hard disks are equipped with a cache memory which accommodates at least two tracks,*rt most cases. Even If your PC is unable to stand an interleave value of 1:1 as the transfer viathe slowly clocked AT bus Is not fast enough, this is not a disaster. Because of the 1:1 interleave,

889

the data is read very quickly Into the controller cache which Is acting as a buffer. The Qfetches the data from the cache with the maximum transfer speed of the AT bus. An Interimvalue which is adjusted too low, therefore, has no unfavourable consequences as It would dwithout the cache.

For high-capacity IDE hard disks, the RLL encoding method Is mainly used; simpler ones %also use the MFM method. High performance IDE drives enable data transfer rates betweedrive and main memory of up to 5 Mbytes/s; a value which comes near the top of the practicevalues of SCSI On average, transfer rates of more than 3 Mbytes/s are realistic for usual IQ-drlves. Thus they are located between the older ST412/506 controllers and the high-end SCS;"solutions. The simpler Interface electronics of the IDE host adapter and the support of the A]bus drives by the AT's en-board BIOS make It appear that the IDE hard disks are a rather good'solution for personal computers in the region of medium performance.An IDE Interface manages a maximum of two drives. As long as the connected drive meets theIDE Interface specification, the internal structure of the drive Is insignificant. For example, it ispossible to connect a powerful optical drive by means of an IDE interface. Usually, one wouldselect an SCSI solution as this is more flexible In a number of ways than the AT bus.One restriction of IDE Is the maximum cable length of 187/ (46 cm); some manufacturers alsoallow up to 247/ (61 cm). For larger systems which occupy several cabinets, this Is too little, butfor a personal computer even In a large tower case It is sufficient. These values are part of theIDE standard. Thus, it is not Impossible that the cables may be longer; but the IDE standarddoes not guarantee this.

The AT File

The CPU accesses the controller of the IDE hard disk by means of several data and controlregisters, commonly called the AT task file. The address and assignment of these registers isidentical to that of the hard disk controller with an ST506 interface In the IBM AT, but note thatthe registers are not compatible with the XT task file, or other Interfaces such as ESDI or SCSI.The AT task file is divided into two register groups with port base addresses ifOh and 3f0h. Thefollowing sections describe the registers of the AT task file and their meaning in more detailTable 81.11 lists all the registers concerned.

The data register, which Is the only 16-bit register of the AT task file, can be read or written bythe CPU to transfer data between main memory and the controller. The original AT interfacesupported only programmed Input/output via registers and ports, but no data transfer bymeans of DMA. The reading and writing Is carried out In units of 16 bits; only the ECC bytesduring the course of a read-long command are passed byte by byte. In this case, you must usethe low-order byte of the register. Note that the data in the data register is only valid if the DRQbit In the status register Is set.

The CPU can only read the error register; It contains error information concerning the last activecommand If the ERR bit In the status register Is set and the BSY bit In the status register Iscleared; otherwise, the entries In the error register are not defined. Note that the meaning of thisregister differs for the diagnostics command. Figure 31.16 shows the structure of the error register.

Register

data registererror registerprecompensation

sector countsector numberfinder LSBcylinder MSBdrive/headstatus registercommand registeralternate status registerdigital output registerdrive address

Table 31.11: The AT task file

Address[bit]

1fOh1f1h1f1h1f2h1f3h1f4h1f5h1f6h1f7h1f7h3f6h3f6h3f7h

WidthWrite(W)

16888888888888

Reac

R/WRWR/WR/WR/WR/WR/WRWRWR

7

BB

K

6 5O

4QZ

3 2

JABT

1

|NT

O

0

BBK: 1 =sector marked as bad by host

UNC: 1 =uncorrectable data error

NID: 1=ID mark not found

ABT: command abort1 =command aborted

NTO: 1 =track 0 not foundHUM: 1 =data address mark not found

x: unused

0=no error0=no or correctable data error

0=no error

0=command executed

0=no error

0=no error

0=medium not changed0=no medium change required

Enhanced IDE only:MC: 1=medium changedMCR: 1 =medium change required

Figure 31.16: Error register (Iflh).

A set NDM bit indicates that the controller hasn't found a data address mark on the data carrier.If NTO is set this means that after a corresponding command the drive was unable to positionthe read/write head above track 0. If the controller had to abort execution of the active com-mand because of an error, the ABT bit is set. If the MD bit is equal to 1 the c o n t r o l waunable to detect the ID address mark concerned on the data carrier. A set UNC bit shows thatan uncorrectable data error has occurred; the data is invalid even after applying the ECC code^If BBK is equal to 1 then the CPU has earlier marked the sector concerned as bad; it can nolonger be accessed.

For supporting drives with removable volumes, enhanced IDE implements the (formerlyreserved) MC and MCR bits. A set MC bit indicates that the volume in the, dnve has beenchanged, thus it corresponds to the disk change bit of the floppies. A set MCR bit shows that

390Chapters

the user has requested a medium change/ for example, by operating the eject key. The systemmust complete all running accesses and send a pulse or command to the drive actually to ejecthe volume.

The precompensation register (l£lh) is only implemented for compatibility reasons with the ATtask file of the original AT. All data passed by the CPU is ignored. The IDE hard disk driveswith an embedded controller process the precompensation Internally without any Interventionby the CPU.

The sector count register (If2h) can be read and written by the CPU to define the number ofsectors to be read, written or verified. If you pass the register a value of 0, then the hard diskcarries out the command concerned for 256 sectors, and not for 0 sectors. After every transferof a sector from or Into main memory, the register value is decreased by one. Thus the register'scontents, which can be read by an IN instruction, indicate the number of sectors still to be read,written or verified. Also, during the course of a formatting process, the controller decrementsthe register value. Note that the meaning of the register differs somewhat for the command setdrive parameters.

The sector number register (If3h) specifies the start sector for carrying out a command with diskaccess. After processing every sector the register contents are updated according to the executedcommand. Thus the register always indicates the last processed sector Independently of whetherthe controller was able to complete the concerned command successfully or not.The two registers cylinder MSB (If5h) and cylinder LSB (If4h) contain the most-significant(MSB) and least-significant byte (LSB) of the 10-bit cylinder number. The two most-significantbits are held by the register cylinder MSB, the eight least-significant ones by the register cylinderLSB. The six high-order bits of register cylinder MSB are Ignored, thus the registers are able torepresent cylinder numbers between 0 and 1023, as Is also the case for the original AT. Becausemany IDE hard disks carry out a translation, the physical cylinders of the hard disk are notlimited to this range. The physical drive geometry Is then converted into a logical one, whichhas a maximum cylinder number of 1023. After processing of each sector, the contents of bothregisters are updated, thus the registers always indicate the current cylinder number. Some IDEdrives, and especially hard disks corresponding to the enhanced IDE standard, also use the sixhigh-order bits in the MSB cylinder register If5h. Therefore, a total of 65 535 cylinders can beaddressed at the most.

By means of the registers drive/head (If6h) you can determine the drive for which the com-mand concerned Is to be carried out. Furthermore, head defines the start head with which thedisk access begins. Figure 31.17 shows the format of this register.

The three most-significant bits always have value of 101b. The DRV bit defines the addresseddrive, and the bits HD3-HD0 specify the number of that head with which the command con-cerned starts to execute. A maximum of 16 heads can therefore be accessed. IDE drives whichcan carry out a logical block addressing (LBA), additionally Implement the L bit. If L equals 1/LBA Is enabled for the present access.

The status register (If7h) can only be read by the CPU, and contains status information concerningthe last active command. The controller updates the status register after every command, or tfan error occurs. Also, during the course of a data transfer between main memory and controller/

nard Disk Drives 891

7

1

6

L

5

1

4

Q

3co

ax

2CM

QX

1

aX

0o

QX

oRV: drive1 =slave 0=masler

HD3-HD0: head number (binary)0000=head0 0QQ1=head1 0010=head2 1111=head 15

Enhanced IDE only:L: 1=LBAmode 0=CHS mode

Figure 3117: Drive/head register (If6h).

the register Is updated to carry out handshaking. If the CPU reads the status register an even-tually pending interrupt request (via IRQ14 in the PC) is cancelled automatically. Note that allbits of this register except BSY and all registers of the AT task file are Invalid if the BSY bit isset in the status register. Figure 31.18 shows the structure of the register.

7 6 5 4 3 2 1 0

BSY:

RDY:

WFT:

SKC:

DRQ:

CORR:

IDX:

ERR:

0=drive not busy

0=drive not ready

0=no write fault

0=in progress

0=no data access possible

0=not data error

busy1 =drive is busyready1 =drive is readywrite fault1= write faulthead positioning (seek)1 =completedata1 =can be transferredcorrectable data error1 =data errordisk index1 =disk index has just passed 0=disk index did not passerror1=error register contains error informationO=error register does not contain error information

%wre 3118: Status register (If7h).

he BSY bit is set by the drive to indicate that it Is currently executing a command. If BSY isset then no registers may be accessed except the digital output register. In most cases you getany Invalid information; under some circumstances-you disturb the execution of the activec°namand. A set RDY bit shows that the drive has reached the operation rpm value and Is readyto accept commands. If the revolution variations of the spindle motor are beyond the tolerablerange, for example because of an insufficient supply voltage, then the controller sets the RDY

892 TChapters -ard Disk Drives 893

bit to 0= A set WFT bit indicates that the controller has detected a write fault. If the SKC bit -equal to 1, then the drive has completed the explicit or implicit head positioning. The drirclears the SXC bit immediately before a head seek. A set DRO bit shows that the data resist**is ready for outputting or accepting data. If DRQ is equal to 0 then you may neither read dahfrom the data register nor write data into it. The controller sets the CORK bit to inform the CPUthat it has corrected data by means of the ECC bytes. Note that this error condition doesn't abortthe reading of several sectors- Upon the passage of the track beginning below the read/writehead of the drive, the controller sets the IDX bit for a short time. If the ERR bit is set, the errorregister contains additional error information.

The command register (If7h) passes command codes; the CPU is only able to write to it. Thecommand register is located at the same port address as the read-only status register. Theoriginal AT has eight commands in total with several variations. The new IDE standard addi-tionally defines some optional commands, but I want to restrict the discussion to the requestedcommand set which is already implemented on the IBM AT. The execution of a command startsimmediately after you have written the command byte into the command register. Thus youhave to pass all other required data to the corresponding registers before you start the commandexecution by writing the command byte.

Table 31.12 lists the requested IDE commands as well as the parameter registers that you mustprepare for the corresponding commands.

Command

SRST:

i i i ' '••

system reset1=reset all connected drivesinterrupt enable1=!RQ14 always masked

7 3 2 1 0I I I I

X X X X X tew

IEN

X 1

0=accept command

O=interrupt after every command

calibrate driveread sectorwrite sectorverify sectorformat trackseek headdiagnosticsset drive parameters

SC

XX

XX

XX

XX

XX

XX

CY

XX

XX

XX

XX

XX

DR

XX

XX

XX

XX

XX

XX

HD

XX

XX

XX

XX

XX

XX XX

SC: sector count SN: sector number

DR: drive (in register drive/head)

HD: head (in register drive/head)

xx: parameter necessary for corresponding command

CY: cylinder MSB and LSB

figure 31.19: Digital output register (3f6h).

If you set the SRST bit you issue a reset for all connected drives. The reset state remains activeuntil the bit is equal to 1. Once you clear the SRST bit again, the reset drives can accept acommand. With the IEN bit you control the interrupt requests of the drives to the CPU. If IENis cleared (that is, equal to 0) then an interrupt is issued via IRQ14 after every command carriedout for one sector, or in advance of entering the result phase. If you set IEN to 1 then IRQ14is always masked and the drives are unable to issue an interrupt. In this case, the CPU may onlysupervise the controller by polling.

With the read-only drive address register (3f7h) you may determine which drive and whichhead are currently active and selected. Figure 31.20 shows the structure of this register.

7 6 5 4 3 2 1 0

X I JHS3

|HS

2

| H

S1

| H

SO

|DS

I|

DS

O

WTGT: write gate1 =write gate closed 0=write gate open

HS3-HS0: currently active head as 1 'complementDS1, DSO: currently selected drive

%

figure 31.20: Drive address register (3f7h).

If the WTGT bit is cleared (that is, equal to 0), the write gate of the controller is open and the read/write head is currently writing data onto disk. The bits HS3-HS0 indicate the currently activehead as 1' complement. Similarly, the bits DS1 and DSO determine the currently selected drive.

"31.19.* * * > * *e CPU is only

C ° n t r o l l e r / S behaviour; its structure is shown in Figure

31.6.4 IDE Interface Programming and Command Phases

The programming and execution of the commands for an IDE interface proceed similar to afloppy controller or other hard disk interface in three phases:

- Command phase: the CPU prepares the parameter registers and passes the command codeto start the execution.

""• Data phase: for commands involving disk access, the drive positions the read/write headsand eventually transfers the data between main memory and hard disk.

895j3rd Disk Drives

- Result phase: the controller provides status information for the executed command in,corresponding registers, and issues a hardware interrupt via IRQ14 (corresponding top76h). "

The controller's command and register are written and read by the CPU via ports, but uij.the PC/XT, the IBM AT and all compatibles don't use the DMA controller for transferring £sector and format data between main memory and controller. Instead, this data transfer is atcarried out by programmed I/O via CPU and data register. This means that the CPU writes sectand format data into or reads them from the data register in units of 16 bits. Only the ECCbyfc.are read and written in 8-bit portions via the low-order byte of the data register. To synchronizeCPU and controller for a data exchange, the controller issues a hardware interrupt at varioustimes via IRQ14:

- Read sector: the controller always enables IRQ14 when the CPU is able to read a sector.:eventually together with the ECC bytes, from the sector buffer. Unlike all other commands, -.this command doesn't issue an interrupt at the beginning of the result phase, thus tk •number of hardware interrupts is the same as the number of read sectors. \

- Write sector: the controller always activates IRQ14 when it expects sector data from the CPU, INote that the first sector is transferred immediately after issuing the command, and the jcontroller doesn't issue an interrupt for this purpose. Furthermore, the controller activates,via IRQ14, a hardware interrupt at the beginning of the result phase. Thus the number ofhardware interrupts coincides with the number of written sectors.

- All other commands: the controller issues a hardware interrupt via IRQ14 at the beginningof the result phase.

The interrupt handler for INT 76h corresponding to IRQ14 in the PC must therefore be able todetermine whether the controller wants to output data, is expecting it or whether an interrupthas occurred which indicates the beginning of a result phase. If you intend to program such ahandler, use the status and error register to determine the interrupt source. The IRQ14 controlleris disabled as soon as the CPU reads the status register (If 7h). If IRQ14 remains active, you mustread the status information via the alternate status register (3f6h).

Note for your programming that the controller of the addressed drive starts command executionimmediately after the CPU has written the command code into the command register. Thus youhave to. load all necessary parameter registers with the required values before you start com-mand execution by passing the command code.

Appendix H lists all requested controller commands for the IDE interface, and the three optionalcommands for identifying the controller as well as reading and writing the sector buffer. As anexample one command is discussed here in more detail: write four sectors beginning withcylinder 167, head 3, sector 7 with ECC bytes. The format for this command Is shown in Figure31.21.

If the L bit Is set then the four ECC bytes are also supplied by the CPU and not generatedinternally by the controller. The ECC logic then doesn't carry out an ECC check. For a singlesector you therefore have to pass 516 bytes. If L is equal to 0 then this means a normal writecommand. The CPU only passes the 512 data bytes, and the controller generates the four ECC

Number of Sectors to WriteSector Count (1f2h)Sector Number (1f3h)Cylinder LSB (1f4h)Cylinder MSB (1f5h)

1 DRV HD3 HD2JHD1HD0

long=with ECC bytes

0=without ECC bytes

retry1 =carry out retry procedure 0=no retry procedure

sector count: number of sectors to be written onto disk

sector number (start sector)

cylinder number (start cylinder)drive

0=drive 01=drive1head1111=head15

Yipire 31.21: Write sector command.

bytes internally and writes them, together with trie data bytes, onto disk. Trie R bit controls theinternal retry logic of the controller. If R is set, then the controller carries out an in-built retryprocedure if it detects a data or address error during the course of the command execution. Onlyif these retries are also unsuccessful does the controller abort the command and return an errorcode. If R is cleared, the controller aborts the command Immediately without any retry if anerror has occurred.

With sector count you may determine the number of sectors to be written onto disk. Possiblevalues are between 0 and 255; a value of 0 writes 256 sectors onto disk. The sector numbersS7-So indicate the number of the start sector to be written first. If the number of sectors to writeis larger than 1, the controller automatically counts up the sector number until It detects the endof the track. Afterwards, it proceeds with the next head, and eventually with the next cylinder,until all sectors have been written or an error occurs. The values C9-C0 of the cylinder numberdefine trie start cylinder for the write process. The two bits C9 and C8 represent the two mostsignificant bits of the 10-bit cylinder number. Using DRV you can select one of the two drives,and with HD3-HD0 trie head of the drive for which the command is to be carried out.Immediately after the command byte has been written, the controller starts the command execu-tion, that is, the data phase. It sets the BSY bit in the status register to indicate that it hasdecoded the command and prepared the sector buffer for accommodating the 512 data bytes,as well as the four ECC bytes. If this is finished, trie controller clears the BSY bit and sets theDRQ bit In the status register to inform the CPU that it now expects the sector data. The CPUfirst transfers the 512 data bytes word by word, and afterwards the four ECC bytes byte by byte.K all 516 sector bytes have been passed the controller sets the BSY bit again and clears the DRQbit. Now it begins to write the data onto disk.

896Chapter. Hard Disk Drives

897

If the first sector has been written then the controller Issues an interrupt 76h via IRQ14. \\handler concerned now transfers the 516 bytes of the following sector data via the data registerJto the controller in the same manner as described above. This process is repeated four timejuntil all four sectors, together with their ECC bytes, have been written. |

Example: Write four sectors starting with, cylinder 167^ head 3^ sector 7 together with ECC Ibytes onto master drive (languages Microsoft C 5.10). |

iunsigned int word_buffer [1024]; |

unsigned char byte_buffer [16]; §

unsigned int *word_pointer; |

unsigned char *byte_pointer; !

int int_count; |

main () j{ int word_count^ byte_count; l;

void far ^old_irql4;word_pointer = &word_buf f er;byte_pointer = &byte_bu£fer;

init_buffers();

/* initialize */

/* pointer */

old_irql4 = _dos_getvect(0x76);

_dos_setvect (0x7 6, new_irgl4());

while((inp(0xlf7) & 0x80) == 0x80);

outp(0xlf2, 0x04);

©utp(0xl£3, 0x07);

outp(0x1f4, 0xa7);

outp(0xl£5, 0x00);

outp(Qxl£6^ 0xa3);

outp(0xlf7, 0x33);

/* write first sector (512 data bytes

while ((inp(0xlf7) & 0x80) == 0x80 II

word_pointer = word_buf f er;

for (word_count = 0; word_count < 256;

outpw(0xlf0^ *word_pointer);}

byte_pointer = byte_buf f er;

for (byte_count = 0; byte_count < 4;

outp(0xlf0, *byte_pointer);}

int_count=0;

while (int__count < 4);

_dos_setvect(0x7 6, old_irql4());

status_check();

exit(0);

}

void interrupt far new_irql4()

{ int word_count# byte_count;

/* initialize buffer */

/* set new interrupt */

/* for IRQ14 */

/* wait until BSY in status register is cleared */

/* register sector counti 4 sectors */

/* register sector number: 7 */

/* register cylinder LSBs 167 */

/* register cylinder MSB? 0 */

/* register drive/head: DRV=0y head-3 */

/* register commands opcodesOOHOO^ Lsl, R=l */

+ 4 ECC bytes */

(inp(0xlf7) & 0x08) I =0x08); /* wait until BSY in

status register is cleared and DRQ is set */

/* initialize pointer */

word_count++, word_pointer+ +) {

/* transfer 256 words = 512 data bytes */

/* initialize pointer */

byte_count+ + byte_pointer-f + ) {

/* transfer 4 ECC bytes */

/* initialize interrupt count */

/* wait until all four sectors are transferred *//* set old IRQ14 #/

/* check status information and determine errorcode */

int_count++;

if (int_CQunt<4) { /* ignore interrupt at the beginning of result phase*/

for (word__count = 0; word_count < 256; word_count++, word_pointer++) {

outpw(0xlf0# *word_pointer); /* transfer 256 words = 512 data bytes */

}for (byte_count = 0; byte_count < 4; byte_count++, byte_pointer++) {outp(0xlf0# *byte__pointer); /* transfer 4 ECC bytes */

return;

}

In the example, the handler for IRQ14 serves only for transferring the data; a more extensivefunction, for example for determining the interrupt source, is not implemented. The 2048 databytes in 1024 data words as well as the 16 ECC bytes must be suitably initialized. This is notcarried out here because of the lack of space. Furthermore, the procedure status_check() forchecking the status information is not listed in detail

Upon the last interrupt the result phase is entered. Figure 31.22 shows the task file registers thatcontain valid status information after the command has been completed. The entries in the errorregister are only valid if the ERR bit in the status register is set and the BSY bit is cleared.

NDM:NTO:ABT:

NID:

UNC:BBK:DRV:

AT Task FileRegiste

ErrorSector Count

( i f ih)(1f2h)

Sector Number (1f3h)Cylinder LSBCylinder MSBDrive/HeadStatus

1 =data address mark not found

1=trackO not foundinstruction abort1 instruction aborted

1=ID mark not found1 =not-correctable data error1 =sector marked bad by host

drive1 =slave

(1f4h)(1f5h)(1f6h)(1f7h)

Bit7 | 6 I 5 4 | 3

NDM NTO ABT x NID2 1 ux UNCBBK

Number of Sectors Written

S7 S6 S5 S4 S3

C7 C6 C5 C4 C3

0 0 0 0 0

S2 SiC2 C10 C9

1 0 1 DRV HD3 HD2 HD1

SoCo

c8HDo

BSY RDY WFT SKC DRQ COR IDX ERR

0=no error

0=no error

O=instruction executed

0=no error0=no or correctable data error

0=no error

0=master

C9-C0, S7-S0, HD3-HD0: sector identification of last written sector

I

1111111

%wre 32.22: Result phase of «Write Sector» instruction.

According to the sector Identification, you can determine the last written sector or the sectorwMch gave rise to the command abortion. The sector count register specifies the number ofsectors still to be written, that is, a value of 0 If the command has been terminated without anyerror.

-;ard Disk Drives899

The main advantage of IDE over SCSI is the very simple structure oT the ';ost adapter for diskdrives using this interface. In fact the host adapter just switches the A i ous of the PC throughto the IDE drive controller. A complicated converting of the signals z he Independent per-forming of (SCSI) bus cycles, is not necessary. For this reason, IDE adapters and IDE disk drivesfor a while, dearly had a price advantage, and so kept their nose in front. Not surprisingly, thislias changed in the meantime. On the one hand, both SCSI disk drives and SCSI host adaptershave become much better value for money (the price advantage of many IDE boards is purelythe result of lower performance and, thus, cheaper drives). On the other hand, the integrationof an interface designed for an AT bus into an MCA or local bus system means Increased.complexity and, therefore, a higher price. So as not to give the advantage to SCSI, the specifi-cation has been expanded, and the result is enhanced IDE.

Enhanced IDE Is characterized by two essential points: the supporting of disk drives withremovable data volume devices; and a higher transfer rate between the host and the disk drive.The former is achieved with a few new Instructions such as medium exchange confirmation(Odbh), secure drive shutter (Odeh), release drive shutter (Odfh), and also the MC and MCR bitsin the cylinder registers (If4h/lf5h). In addition, a high-level protocol Is planned so that the hostadapter can communicate with the disk drive; the SCSI model Is easy to spot. Furthermore, itshould be possible to connect more than two disk drives to an IDE adapter. For this, a secondIDE task file Is provided at 170h-177h and 37611-37711, but which should only serve disk driveswith a removable data volume device.

The requirement for more performance affects not only the data transfer rate Itself (here, the PIOand DMA modes, If available, prove themselves to be bottlenecks), but also the maximumcapacity of the IDE hard disk. The most frequently used (and targeted at AT) CHS procedurefor addressing a sector (Cylinder Head Sector) limits the capacity to 504 Mbytes (cylinder 1024,head 16, sector 63). The IDE standard Itself (that Is, trie layout of the registers), with 255 sectorsper track and a maximum of 65 536 cylinders, would still permit 127.5 Gbytes. As a solution,enhanced IDE offers Logical Block Addressing (LBA), similar to SCSI. The disk drive thenappears as a continuous medium with sequential blocks. The quite laborious addressing of databy converting it Into cylinder, head and sector is no longer necessary as the disk drive controlleraccomplishes this automatically. This means no additional workload, because the controllermust convert the logical into a physical geometry anyway. To activate LBA for an access, youmust set the L bit in the disk drive/head register at If6h (Figure 31.17). From the 127.5 Gbytemaximum capacity of IDE, more than 7.8 Gbytes remain available for use by the BIOS. Duringbooting, the BIOS uses the Identify drive instruction to determine the capacity, but can onlycope with a maximum of 1024 cylinders (In place of the 65 536 offered by enhanced IDE). Onlyspecial drivers can bypass this limitation and allow the full 127.5 Gbytes to be used.With enhanced IDE, the transfer rate should be greatly Increased over that possible in currentEISA and local bus systems. For this, a new PIO mode #3 Is provided which should (theoreti-cally) perform a transfer in 120 ns. With a 16-bit data bus width to the disk drive, this producesa maximum transfer rate of 16.6Mbytes/s. The also accelerated DMA block mode #1 transfersa 16-bit data packet within 150 ns; the transfer rate achieved Is 13.3 Mbytes/s. Both values, as

-ontinuous transfer rates from hard disks, cannot yet be achieved, so there is still a little breath-jug space In the IDE standard for a few years yet to come.

31.7 SCSI

A very flexible and powerful option for connecting hard disks to a PC Is the SCSI {small computersystems interface). The term Itself Indicates that SCSI is intended for the PC and other smallsystems (for example, workstations or the Mac). However, the characterization of PCs andworkstations as «small» has changed, at least as far as MIPS numbers are concerned, since thePentium has been-on the market. SCSI was derived from the SASI of Shugart Associates (ShugartAssociates systems interface). SCSI comes with a somewhat older standard SCSI-1, which Is notstrict enough in some aspects, resulting in compatibility problems when Implementing SCSI-1The new standard SCSI-II determines the properties more precisely, and additionally definessome more commands and operation modes. SCSI follows a different philosophy to those harddisk interfaces already discussed; this section gives more Information on this subject.

31.7.1 SCSI Bus and Connection t© the PC

SCSI defines a bus between a maximum of eight units, as well as the protocol for data exchangeamong them. Such SCSI units may be hard disks, tape drives, optical drives, or any other devicethat fulfils the SCSI specification. Thus, SCSI drives are intelligent, as are the IDE hard disks; theunit's controller is always Integrated on the drive. For connection to the PC a SCSI host adapteris required, which establishes the connection to the PC's system bus similar to the IDE Interface.The host adapter Itself is also a SCSI unit, so that only seven «free» units remain. Unlike an IDEhost adapter, the SCSI host adapter Is thus rather complex, as it must recognize all the functionsof the- SCSI bus and be able to carry them out. But the advantage is that SCSI is not limited tothe AT bus. There are also host adapters for EISA or the Mac. The enormous data transfer rateas well as the high-end performance of the SCSI hard disks doesn't suggest its use in a PC/XT,however. With an accordingly adapted host adapter the same SCSI devices can also be inte-grated into workstations or an Apple. The Mac has a SCSI interface as standard to connect upto seven external SCSI devices. Apple thus elegantly bypasses Its lack of flexibility comparedwith the IBM-compatible PCs.

Thus the SCSI bus serves only for a data exchange among the SCSI units connected to the bus.A maximum of two units may be active and exchange data at any one time. The data exchangecan be carried out between host adapter and a drive, or (as a special feature of SCSI) alsobetween two other SCSI devices (for example, a tape drive and a hard disk). It is remarkable thatthis data exchange is carried out without the slightest intervention from the CPU; the SCSIdrives are intelligent enough to do this on their own. Figure 31.23 shows a scheme of the SCSIbus in the case of integrating a SCSI into a PC.

Every SCSI unit is assigned a SCSI address, which you can set by a jumper on the drive.Addresses in the range 0-7 are valid; according to the SCSI standard, address 7 Is reserved fora tape drive. The address Is formed by bytes where the least significant bit 0 corresponds to the