identify rtl debugger

Identify RTL Debugger Actel Edition

Quick Start Guide

August 2008

Synopsys, Inc.600 West California AvenueSunnyvale, CA 94086, USA

(U.S.) +1 408 215-6000 direct(U.S.) +1 408 990-0263 fax

www.synplicity.com

®

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Copyright and License Agreement

ii Identify RTL Debugger Actel Edition Quick Start Guide, August 2008


Disclaimer of WarrantySynopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this material, and shall not be liable for any implied warranties of merchantability or fitness for a particular purpose of for any indirect, special or consequential damages.

Copyright NoticeCopyright © 2008 Synopsys, Inc. All Rights Reserved.

Synopsys software products contain certain confidential information of Synopsys, Inc. Use of this copyright notice is precautionary and does not imply publication or disclosure. No part of this material may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the prior written permission of Synopsys, Inc. While every precaution has been taken in the preparation of this material, Synopsys, Inc. assumes no responsibility for errors or omissions. This material and the features described herein are subject to change without notice.

Trademarks

Registered Trademarks (®)Synopsys, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, Design Compiler, DesignWare, Formality, HDL Analyst, HSPICE, Identify, iN-Phase, Leda, MAST, ModelTools, NanoSim, OpenVera, PathMill, Physical Compiler, PrimeTime, SiVL, SCOPE, Simply Better Results, SNUG, SolvNet, Synplicity, the Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, VCS, Vera, and YIELDirector are registered trademarks of Synopsys, Inc.


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Trademarks (™)AFGen, Apollo, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Confirma, Cosmos, CosmosLE, CosmosScope, CRITIC, DC Expert, DC Professional, DC Ultra, Design Analyzer, Design Vision, Design-erHDL, DesignPower, Direct Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HAPS, HapsTrak, HDL Compiler, Hercules, Hierarchical Optimization Technology, High-performance ASIC Prototyping System, HSIM, HSIM

plus, i-Virtual Stepper, IICE, in-Sync, iN-Tandem, Jupiter, Jupiter-DP,

JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, Library Compiler, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, ModelSource, Module Compiler, MultiPoint, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Saturn, Scirocco, Scirocco-i, Star-RCXT, Star-SimXT, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are trademarks of Synopsys, Inc.

Service Marks (SM

)MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.

SystemC is a trademark of the Open SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners.

Restricted Rights LegendGovernment Users: Use, reproduction, release, modification, or disclosure of this commercial computer software, or of any related documentation of any kind, is restricted in accordance with FAR 12.212 and DFARS 227.7202, and further restricted by the Synopsys Software License and Maintenance Agreement. Synopsys, Inc., Synplicity Business Group, 600 West California Avenue, Sunnyvale, CA 94086, U. S. A.

August 2008

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iv Identify RTL Debugger Actel Edition Quick Start Guide, August 2008

Synopsys Software License and Maintenance AgreementSynplicity Software Products

This Software License and Maintenance Agreement (“Agreement’) is a legal agreement between you (“Licensee”) and the contracting Synopsys entity identified below (“Synopsys”). YOU MUST READ AND AGREE TO THE TERMS OF THIS AGREEMENT BEFORE ANY SOFTWARE CAN BE DOWNLOADED OR INSTALLED OR USED. BY CLICKING ON THE “ACCEPT” BUTTON OF THIS AGREEMENT, OR BY DOWNLOADING, INSTALLING OR USING SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS AND CONDITIONS OF THIS AGREEMENT. IF YOU DO NOT AGREE WITH THE TERMS AND CONDITIONS OF THIS AGREEMENT, THEN YOU SHOULD EXIT THIS PAGE AND NOT DOWNLOAD OR INSTALL OR USE ANY SOFTWARE. BY DOING SO YOU FOREGO ANY IMPLIED OR STATED RIGHTS TO DOWNLOAD OR INSTALL OR USE SOFTWARE AND YOU MAY RETURN IT TO THE PLACE YOU OBTAINED IT FOR A FULL REFUND (IF APPLI-CABLE).

Definition. “SOFTWARE” means the software product of Synopsys’s Synplicity business group that Licensee has acquired, including related documentation (whether in print or electronic form), any authorization keys, authorization codes, and license files, and any updates or upgrades of such software provided by Synopsys.

License Grant. Synopsys grants to Licensee a non-exclusive license to (a) install the SOFTWARE, (b) use or authorize use internally of the SOFTWARE by up to the number of nodes for which Licensee has a license and for which Licensee has the security key(s) or authorization code(s) provided by Synopsys or its agents for the purpose of creating and modifying Designs (as defined below), and (c) copy the SOFTWARE only as follows: (i) to directly support authorized use under the license, and (ii) in order to make a reasonable number of copies of the SOFTWARE for backup purposes only.

Documentation License. In addition, Synopsys grants to Licensee a non-exclusive license to copy and distribute internally the documentation portion of the SOFTWARE in support of its license to use the program portion of the SOFTWARE.

Node-Locked and Floating Licenses.

Node-Locked License. If Licensee has obtained the SOFTWARE under a node-locked license, then a “node” refers to a specific machine and the SOFTWARE may be installed only on the number of nodes indicated on the applicable Synopsys quote, must be used only on the node(s) on which it is installed,


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and may be accessed only by users who are physically present at that node. Further, a node-locked license may only be used by one user at a time running one (1) instance of the SOFTWARE at a time.

Floating License. If Licensee has obtained the SOFTWARE under a floating license, then a “session” refers to a concurrent user or session and the SOFTWARE may be used concurrently by up to the quantity of sessions or licenses indicated on the applicable Synopsys quote. All SOFTWARE must be used within the country for which the systems were licensed and at Licensee’s Site; however, if Licensee has a floating license then remote use is permitted by employees who work at Licensee’s Site but are temporarily telecommuting to that Licensee’s Site from less than fifty (50) miles away (for example, an employee who works at a home office on occasion) as long as such access is through a secure network that requires a secure ID card or other protective security measures, but the maximum number of concurrent sessions or nodes still applies. For purposes of this Agreement, the “Licensee’s Site” means a five (5) mile radius around (a) the location of the server on which the SOFTWARE resides, or (b) when a server is not required, the location of the client computer for which the license was issued, each as specified in the applicable Synopsys quote.

Evaluation License. If Licensee has obtained the SOFTWARE pursuant to an evaluation license, then, in addition to all other terms and conditions herein, the following restrictions apply: (a) the license to the SOFTWARE terminates after the period of time indicated on the SOFTWARE file (unless otherwise agreed to in writing by Synopsys); and (b) Licensee may use the SOFTWARE for the sole purpose of internal testing and evaluation to determine whether Licensee wishes to license the SOFTWARE on a commercial basis. Licensee shall not use the SOFTWARE to design any integrated circuits for production or pre-production purposes or any other commercial use including, but not limited to, for the benefit of Licensee’s customers. If Licensee breaches any of the foregoing restrictions, then Licensee shall pay to Synopsys a license fee equal to Synopsys’s perpetual list price plus maintenance for the commercial version of the SOFTWARE. Licensee agrees that damages for such a breach would be difficult to assess, and such payment represents a reasonable assessment of the potential damage to Synopsys. Licensee recognizes and agrees that this amount is a reasonable, liquidated amount and not a penalty. Evaluation licenses are provided “AS IS.” Therefore, the warranty and indemnification provisions of this Agreement do not apply to evaluation licenses.

Time-Based (Subscription) License. If Licensee has obtained a time-based license to the SOFTWARE, in addition to all other terms and conditions herein, the following restrictions apply: (a) Licensee is authorized to use the

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SOFTWARE only for a limited time (which time is indicated on the quotation or in the purchase confirmation documents); (b) Licensee’s right to use the SOFTWARE terminates on the date the license term expires as set forth in the quotation or the purchase confirmation documents, unless Licensee has renewed the license by paying the applicable fees.

SOFTWARE Delivery. Electronic Software Transfer (“EST”) where available, is Synopsys’ default method of delivery of the SOFTWARE. If Licensee does not wish to receive the SOFTWARE via EST, then Licensee must note this preference on Licensee’s purchase order. However, if Licensee was receiving a tax advantage based on EST delivery, and Licensee does not receive the same tax advantage when the SOFTWARE is delivered in tangible media, then Licensee shall be responsible for payment of all taxes associated with the receipt of the SOFTWARE in tangible form. Nothing herein is intended to modify or relieve Licensee’s obligation to bear or reimburse all transaction taxes, as provided herein. Licensee shall provide all information and documents reasonably requested by Synopsys for each Licensee location in order to effect delivery by EST. Upon the acceptance of an EST order by Synopsys, and the satisfaction of all Synopsys prerequisites prior to delivery, the SOFTWARE and Documentation will be made available to Licensee for electronic download from a Synopsys server. Synopsys or its authorized representative completes its obligation to deliver the SOFTWARE via EST at such time Synopsys or its authorized representative makes it available on a Synopsys or other authorized server and gives Licensee a method of accessing and downloading it. Licensee is responsible for: (i) notifying Synopsys of any change in the EST contact email address and (ii) obtaining access to the Internet and retrieving the fulfilled order from the Synopsys server. Delivery by EST is not available for any product which is “dongle” based. This includes all “Node-Locked” products as well as “Floating” licenses installed on a Windows NT or Linux operating system.

Copy Restrictions. SOFTWARE is protected by United States copyright laws and international treaty provisions and Licensee may only copy the SOFTWARE as explicitly set forth above. Any permitted copies must include all copyright and trademark notices.

Use Restrictions. This SOFTWARE is licensed to Licensee for internal use only. Licensee shall not (and shall not allow any third party to): (a) decompile, disassemble, reverse engineer or attempt to reconstruct, identify or discover any source code, underlying ideas, underlying user interface techniques or algorithms of the SOFTWARE by any means whatever, or disclose any of the foregoing; (b) host the SOFTWARE acquired under a node-locked license via the Internet or Intranet; (c) use the SOFTWARE for timesharing or service bureau purposes or otherwise circumvent the internal use restrictions;


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(d) modify, incorporate into or with other software, or create a derivative work of any part of the SOFTWARE; (e) disclose the results of any benchmarking of the SOFTWARE, or use such results for its own competing software devel-opment activities, without the prior written permission of Synopsys; (f) attempt to circumvent any user limits, maximum gate count limits or other license, timing or use restrictions that are built into the SOFTWARE; (g) use the SOFTWARE to create, modify, or simulate Designs for third parties; or (h) use the SOFTWARE in the development of any product if the failure or malfunction of that product could reasonably be expected to result in personal injury, death, or catastrophic loss.

Transfer Restrictions/No Assignment. The SOFTWARE may only be used under this license at Licensee’s Site and on designated equipment as set forth in the license grant above, and may not be moved to a location other than the Licensee’s Site or used on equipment other than the designated equipment or otherwise physically transferred without the prior written consent of Synopsys. Any permitted physical transfer of the SOFTWARE will require that Licensee executes a “Software Authorization Transfer Agreement” provided by Synopsys. Further, Licensee shall not sublicense, or assign (by operation of law, including change of control, merger, sale of assets, or otherwise) this Agreement or any of the rights or licenses granted under this Agreement, without the prior written consent of Synopsys. Any such unauthorized transfer will be ineffective, null, and void (and Licensee will be in breach of this Agreement).

Security. Licensee agrees to take all appropriate measures to safeguard the SOFTWARE and prevent unauthorized access or use thereof. Suggested ways to accomplish this include: (i) implementation of firewalls and other security applications, (ii) use of FLEXlm options file that restricts access to the SOFTWARE to identified users; (iii) maintaining and storing license infor-mation in paper format only; (iv) changing TCP port numbers every three (3) months; and (v) communicating to all authorized users that use of the SOFTWARE is subject to the restrictions set forth in this Agreement. Licensee shall monitor each end user’s use of the SOFTWARE to ensure that the end user abides by the terms of this Agreement.

Ownership of the SOFTWARE. Synopsys retains all right, title, and interest in the SOFTWARE (including all copies), and all worldwide intellectual property rights therein. Synopsys reserves all rights not expressly granted to Licensee. This license is not a sale of the original SOFTWARE or of any copy.

Ownership of Design Techniques. “Design” means the representation of an electronic circuit or device(s), derived or created by Licensee through the use of the SOFTWARE in its various formats, including, but not limited to,

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equations, truth tables, schematic diagrams, textual descriptions, hardware description languages, and netlists. “Design Techniques” means the data, circuit and logic elements, libraries, algorithms, search strategies, rule bases, techniques and technical information incorporated in the SOFTWARE and employed in the process of creating Designs. Synopsys retains all right, title and interest in and to Design Techniques incorporated in the SOFTWARE, including all intellectual property rights embodied therein, provided that to the extent any Design Techniques are included as part of or embedded within Designs created by Licensee, Synopsys grants Licensee a personal, nonex-clusive, nontransferable license to reproduce the Design Techniques and distribute such Design Techniques solely as incorporated into Licensee’s Designs and not on a standalone basis. Additionally, Licensee acknowledges that Synopsys has an unrestricted, royalty-free right to incorporate any Design Techniques disclosed by Licensee into its software, documentation and other products, and to sublicense third parties to use those incorporated Design Techniques.

Protection of Confidential Information. “Confidential Information” means (a) as to Synopsys, the terms and conditions of this Agreement, the SOFTWARE, in object and source code form, the documentation, any license keys, and any related technology, idea, algorithm or information contained therein, including without limitation Design Techniques, and any trade secrets related to any of the foregoing; (b) each party’s product plans, Designs, costs, prices and names; non-published financial information; marketing plans; business opportunities; personnel; research; development or know-how; and (c) any information designated by the disclosing party as confidential in writing or, if disclosed orally, designated as confidential at the time of disclosure and reduced to writing and designated as confidential in writing within thirty (30) days; provided, however that “Confidential Infor-mation” will not include information that: (i) is or becomes generally known or available by publication, commercial use or otherwise through no fault of the receiving party; (ii) is known and has been reduced to tangible form by the receiving party at the time of disclosure and is not subject to restriction; (iii) is independently developed by the receiving party without use of the disclosing party’s Confidential Information; (iv) is lawfully obtained from a third party who has the right to make such disclosure; (v) is released for publication by the disclosing party in writing; or (vi) is an idea or suggestion that Licensee voluntarily provides to Synopsys (in any manner, whether in writing or orally or otherwise) regarding the SOFTWARE, documentation, or Design Techniques, including possible enhancements or improvements (“Feedback”). Synopsys may freely use and disseminate any Feedback Licensee provides, and Licensee agrees not to claim that Synopsys owes it any compensation for its use or dissemination of such Feedback.


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Each party will protect the other party’s Confidential Information from unauthorized disclosure and use with the same degree of care that each such party uses to protect its own like information but in no case less than reasonable care. Neither party will use the other’s Confidential Information for purposes other than those necessary to directly further the purposes of this Agreement. Neither party will disclose to third parties the other’s Confi-dential Information without the prior written consent of the other party or unless such disclosure is necessary to comply with a valid court order or subpoena. If Licensee believes that it must disclose Synopsys’s Confidential Information to comply with a valid court order or subpoena, it must promptly notify Synopsys and cooperate with Synopsys if Synopsys chooses to contest the disclosure requirement, seek confidential treatment of the information to be disclosed, or to limit the nature or scope of the information to be disclosed. Synopsys will do the same if it believes it must disclose your Confidential Information under similar circumstances.

Open Source Software. The SOFTWARE may be delivered with software that is subject to open source licensing terms (“Open Source Software”) which are available at http://www.synopsys.com/sbgproducts_license_agreement/. If the Open Source Software license also requires source code to be made available, Licensee may reference http://www.synopsys.com/sbgproducts_license_agreement/ for information on how to obtain such source code. Licensee agrees that all Open Source Software shall be and shall remain subject to the terms and conditions under which it is provided. The Open Source Software is provided “AS IS,” WITHOUT ANY WARRANTY OF ANY KIND, AND SYNOPSYS FURTHER DISCLAIMS ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO OPEN SOURCE SOFTWARE, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. NEITHER SYNOPSYS NOR THE LICENSORS OF OPEN SOURCE SOFTWARE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AN ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OR DISTRI-BUTION OF THE ECLIPSE SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Copyrights to the Open Source Software are held by the copyright holders indicated in the copyright notices in the corresponding source files.

Audit Rights. With reasonable prior notice, Synopsys shall have the right to audit during Licensee’s normal business hours all records and accounts as may contain information regarding Licensee’s compliance with the terms of this Agreement. Synopsys shall keep in confidence all information gained as a

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result of any audit. In the event any audit discloses a breach of this Agreement, Synopsys reserves the right to terminate this Agreement and/or recover damages, attorney’s fees, and costs, including the cost of the audit.

Fees and Payment. The fees for the SOFTWARE will be identified in the appli-cable Synopsys sales quotation or other agreement (“Purchasing Agreement”) describing (among other things) the SOFTWARE Licensee has licensed, including pricing information. You agree to pay the fees according to the payment terms in the applicable Purchasing Agreement. If the applicable Purchasing Agreement does not contain specific payment terms for the fees in question, payment of those fees will be due within 30 days after the date of Synopsys’s invoice. If you do not pay an amount by the Purchasing Agreement due date, Synopsys will have the right to terminate this Agreement and/or the Purchasing Agreement and accelerate the due date of all remaining payments. In this event, you will owe the entire outstanding balance as soon as you receive written notice from Synopsys that your payment is due. All payments you make to Synopsys are non-refundable. You may not offset any amounts you believe Synopsys owes you against any payments you make to Synopsys under this Agreement. You must make payments in U.S. dollars. If you do not pay an amount by the due date, you must also pay a late payment charge of 1.5% per month or the highest rate permitted by law, whichever is less. If you become the subject of any bankruptcy, dissolution, liquidation, or similar proceedings or make a general assignment for the benefit of your creditors, Synopsys may apply any payments you have previously made to Synopsys for products or services not yet delivered by Synopsys against any amounts you owe Synopsys at that time for products or services that have been delivered by Synopsys (under this Agreement or otherwise).

Taxes. You will be solely responsible for paying all taxes (including sales, use, consumption, withholding, and value-added taxes and similar taxes), other than Synopsys’s income taxes, that are imposed on or result from your purchase, license, or use of Synopsys products and services. If Synopsys is required by law to collect and remit any such taxes, Synopsys may invoice you for such taxes and you agree to pay the invoiced amount to Synopsys. If you are required by the respective jurisdiction where the SOFTWARE is used, or where services are provided, to withhold taxes from payments to Synopsys, you may withhold from the total amount due to the respective Synopsys contracting entity the minimum amount required (but no more). You may only withhold taxes related to a payment at the time of such payment. You must then promptly pay that amount to the appropriate tax authority and provide Synopsys with an official receipt for the payment within 60 days of your payment.


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Termination. Synopsys may terminate this Agreement immediately if Licensee breaches any provision, including without limitation, failure by Licensee to implement adequate security measures as set forth above, provided that if the breach is curable, Synopsys will provide Licensee a fifteen (15) day period within which to cure the breach before terminating this Agreement. Upon notice of termination by Synopsys, all rights granted to Licensee under this Agreement will immediately terminate, and Licensee shall cease using the SOFTWARE and return or destroy all copies (and partial copies) of the SOFTWARE and documentation. The following provisions shall survive any termination or expiration of this Agreement: Ownership of SOFTWARE, Ownership of Design Techniques, Protection of Confidential Infor-mation, Audit Rights, Disclaimer, Limitation of Liability, Export and Miscella-neous, and shall certify in writing to Synopsys that Licensee has complied with these requirements. This Agreement expires upon expiration of the license granted herein. Licensee will remain obligated to pay any amounts it owes to Synopsys when this Agreement is terminated.

Maintenance Services. If you have purchased maintenance services, or your SOFTWARE license includes maintenance services (such as for certain time-based licenses), then you shall be entitled to the following (collectively, “Maintenance Services”): (a) Support: Synopsys will provide you with access to SolvNet and online Documentation, and will use commercially reasonable efforts to make available the Synopsys Support Center on Monday through Friday, between the hours of 9:00 AM and 5:00 PM Pacific time, excluding Synopsys’s Purchasing Agreement holidays; and (b) Software Updates: Synopsys will use commercially reasonable efforts to provide error corrections to the SOFTWARE, as well as minor improvements to the SOFTWARE, as such corrections and improvements become generally available. Any other upgrades or enhancements to the SOFTWARE are not made available by Synopsys as part of Maintenance Services and may be subject to additional charges.

Conditions for Maintenance Services. Synopsys may update its Mainte-nance Services terms on 60 days prior written notice, provided that these updates are applied generally to its Maintenance Service customers. In order to receive Maintenance Services for SOFTWARE, all of the following conditions must be met: (i) you must have purchased Maintenance Services for such SOFTWARE (unless it is licensed under a certain time-based license, in which case Maintenance Services are included); (ii) you must appoint a qualified contact person to interface with Synopsys regarding Maintenance Services, and identify such person to Synopsys in advance; (iii) such qualified contact person must be trained in the use of such SOFTWARE; (iv) you must provide Synopsys with access to the information and system facilities reasonably necessary to provide the Maintenance Services; (v) you must follow the direc-

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tions provided by the Synopsys Support Center to resolve technical problems; (vi) you must follow the operating instructions and procedures for the SOFTWARE as specified in the Documentation or provided by Synopsys; and (vii) you must notify Synopsys of any error or other problem in the SOFTWARE using Synopsys’s current problem reporting procedure. Synopsys will have no obligation to provide Maintenance Services for any SOFTWARE that is damaged, modified (by anyone other than Synopsys), incorporated into other software, or installed in any computing environment not supported by Synopsys, or for any version of SOFTWARE other than the latest and immedi-ately preceding version, or for any problems caused by your negligence, abuse, misuse, or by any causes beyond Synopsys’s reasonable control.

ViewConnect. If you wish to permit Synopsys to deliver Maintenance Services through the use of a shared customer desktop, you must download and install the ViewConnect Tool and related publicly-available, third-party software modules. You are not required to use the ViewConnect Tool, but if you choose to do so, you have the nonexclusive right to use the ViewConnect Tool only to enable Synopsys to remotely access your computer system for the purpose of providing Maintenance Services. Your rights to the third-party software modules are separately described in their accompanying license terms. Neither the limited warranty nor the intellectual property infringement provision of this Agreement applies to the ViewConnect Tool or to the third-party software modules. The ViewConnect Tool is licensed “as is,” and Synopsys makes no warranties, express, implied, statutory, or otherwise, regarding the ViewConnect Tool. Synopsys disclaims all liability of any kind in connection with such third-party software modules, and specifi-cally disclaims any implied warranties of noninfringement, title, merchantability, or fitness for a particular purpose, or arising from a course of dealing or usage of trade both with respect to the ViewConnect Tool and the third-party software modules.

Limited Warranty. Synopsys warrants that the program portion of the SOFTWARE will perform substantially in accordance with the accompanying documentation for a period of ninety (90) days from the date of delivery. Synopsys’s entire liability and Licensee’s exclusive remedy for a breach of the preceding limited warranty shall be, at Synopsys’s option, either (a) return of the license fee, or (b) providing a fix, patch, work-around, or replacement of the SOFTWARE. In either case, Licensee must return the SOFTWARE to Synopsys with a copy of the purchase receipt or similar document. Replace-ments are warranted for the remainder of the original warranty period or thirty (30) days, whichever is longer. Some states/jurisdictions do not allow such limitations, so the above limitation may not apply.


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Disclaimer. EXCEPT AS EXPRESSLY SET FORTH ABOVE, TO THE MAXIMUM EXTENT PERMITTED BY LAW, NO OTHER WARRANTIES OR CONDITIONS, EITHER EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, ARE MADE BY SYNOPSYS OR ITS LICENSORS WITH RESPECT TO THE SOFTWARE AND THE ACCOMPANYING DOCUMENTATION, AND SYNOPSYS EXPRESSLY DISCLAIMS ALL WARRANTIES AND CONDITIONS NOT EXPRESSLY STATED HEREIN, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR CONDITIONS OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, SATISFACTORY QUALITY, AND ANY WARRANTIES ARISING FROM A COURSE OF DEALING OR USAGE OF TRADE. WITHOUT LIMITING THE FOREGOING, SYNOPSYS AND ITS LICENSORS DO NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THE SOFTWARE WILL MEET LICENSEE’S REQUIREMENTS, BE UNINTERRUPTED OR ERROR FREE, OR THAT ALL DEFECTS IN THE PROGRAM WILL BE CORRECTED. Licensee assumes the entire risk as to the results and performance of the SOFTWARE.

Limitation of Liability. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL SYNOPSYS OR ITS LICENSORS OR THEIR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, CONSEQUENTIAL OR INCIDENTAL DAMAGES WHATSOEVER (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTIONS, LOSS OF BUSINESS INFOR-MATION, OR OTHER PECUNIARY LOSS) ARISING OUT OF THE USE OF OR INABILITY TO USE THE SOFTWARE, EVEN IF SYNOPSYS AND/OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. FURTHER, IN NO EVENT SHALL SYNOPSYS’S LICENSORS BE LIABLE FOR ANY DIRECT DAMAGES ARISING OUT OF LICENSEE’S USE OF THE SOFTWARE. IN NO EVENT WILL SYNOPSYS BE LIABLE TO LICENSEE FOR DAMAGES IN AN AMOUNT GREATER THAN THE FEES PAID FOR THE USE OF THE PARTICULAR SOFTWARE AT ISSUE. Without limiting the foregoing, the SOFTWARE may embody a method to protect the security of Designs; however, Synopsys does not warrant the effec-tiveness of such method and shall have no liability resulting from any failure thereof. Some states/jurisdictions do not allow the limitation or exclusion of incidental or consequential damages, so the above limitations or exclusions may not apply. The limitations of liability in this section are a fundamental part of this Agreement and enable Synopsys to provide products and services to Licensee at lower prices. These limitations of liability are intended to apply even if an exclusive remedy is found to have failed of its essential purpose.

Safe Operation. THE SOFTWARE IS NOT DESIGNED OR INTENDED FOR DESIGNING COMPONENTS FOR EQUIPMENT INTENDED FOR SURGICAL IMPLANT INTO THE BODY, OR OTHER APPLICATIONS INTENDED TO SUPPORT OR SUSTAIN LIFE, FOR USE IN FLIGHT CONTROL OR ENGINE CONTROL EQUIPMENT WITHIN AN AIRCRAFT, OR FOR ANY OTHER APPLICATION IN WHICH THE FAILURE

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THEREOF COULD CREATE A SITUATION IN WHICH PERSONAL INJURY OR DEATH MAY OCCUR, AND LICENSEE SHALL HAVE NO RIGHTS HEREUNDER FOR ANY SUCH APPLICATIONS.

Intellectual Property Right Infringement. Synopsys will, at its expense, defend or, at its option, settle any claim or action brought against Licensee to the extent it is based on a third party claim that the SOFTWARE as used pursuant to this Agreement infringes or violates any United States patent issued before the delivery date of the subject SOFTWARE, copyright, trade secret or trademark of any third party, and Synopsys will indemnify and hold Licensee harmless from and against any damages, costs and fees awarded in such claim or action; provided that Licensee provides Synopsys with (a) prompt written notification of the claim or action; (b) sole control and authority over the defense or settlement thereof (including all negotiations); and (c) at Synopsys’s expense, all available information, assistance and authority to settle and/or defend any such claim or action. Synopsys’s obliga-tions under this subsection do not apply to the extent that (i) such claim or action would have been avoided but for modifications of the SOFTWARE, or portions thereof, other than modifications made by Synopsys after delivery to Licensee; (ii) such claim or action would have been avoided but for the combi-nation or use of the SOFTWARE, or portions thereof, with other products, processes or materials not supplied or specified in writing by Synopsys; (iii) Licensee continues allegedly infringing activity after being notified thereof or after being informed of modifications that would have avoided the alleged infringement; or (iv) Licensee’s use of the SOFTWARE is not strictly in accor-dance with the terms of this Agreement. Licensee will be liable for all damages, costs, expenses, settlements and attorneys’ fees related to any claim of infringement arising as a result of (i)-(iv) above.

If the SOFTWARE becomes or, in the reasonable opinion of Synopsys is likely to become, the subject of an infringement claim or action, Synopsys may, at Synopsys’s option and at no charge to Licensee, (a) obtain a license so Licensee may continue use of the SOFTWARE; (b) modify the SOFTWARE to avoid the infringement; (c) replace the SOFTWARE with a compatible, functionally equivalent, and non-infringing product, or (d) terminate the licenses granted hereunder and refund to Licensee the amount paid for the SOFTWARE, as depreciated on a straight-line 5-year basis, or such other shorter period applicable to time-based licenses.


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THE FOREGOING PROVISIONS OF THIS SECTION STATE THE ENTIRE AND SOLE LIABILITY AND OBLIGATIONS OF SYNOPSYS, AND THE EXCLUSIVE REMEDY OF LICENSEE, WITH RESPECT TO ANY ACTUAL OR ALLEGED INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHTS BY THE SOFTWARE (INCLUDING DESIGN TECHNIQUES) AND DOCUMENTATION.

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xvi Identify RTL Debugger Actel Edition Quick Start Guide, August 2008

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Contents

Quick Start GuideBefore You Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Start the Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Design Flow with the Identify RTL Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Create a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Select Desired Instrumentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Configure the IICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Create the Instrumented Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Synthesize and Place and Route the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Open the Identify Project in the Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Set Trigger Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Run Debug Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19View Design Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Communication Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Debugging on a Different Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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Identify RTL Debugger Actel Edition Quick Start Guide, August 2008 1

Quick Start Guide

Before You StartBefore you can start to use the Identify® Instrumentor (and the Identify® Debugger), the Identify software must be installed and you must have a license to run the software. The Identify RTL Debugger uses a floating license based of the FLEXnet licensing technology. If you don’t have a license, you will be prompted to supply one when you attempt to start the Identify Instru-mentor. Please see the documents in the doc/licensing subdirectory where you installed the Identify RTL Debugger for licensing/configuration informa-tion.

Start the ToolThe Identify Instrumentor (and the Identify Debugger) can be started in the graphical mode, shell mode, or, when run in conjunction with the Synplify, Synplify Pro, Synplify Premier, or Certify synthesis tool, can be launched directly from the synthesis tool’s user interface.

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2 Identify RTL Debugger Actel Edition Quick Start Guide, August 2008

Synopsys FPGA Synthesis Tool LaunchThe Identify Instrumentor can be launched directly from the Synplify Pro or Synplify Premier graphical user interface or from the Certify graphical user interface in single-chip mode by selecting Run->Identify Instrumentor.

Note: For instructions on launching the Identify Instrumentor from the Synplify synthesis tool, see Launching from the Synplify Tool in the Synopsys FPGA Synthesis User Guide.

If your project currently does not include an Identify implementation, you are prompted to create one. Click OK.

When you launch the Identify Instrumentor, you are prompted for the location of the Identify Instrumentor executable and the vendor license type. After entering or verifying this information, clicking the OK button in the Launch Identify dialog box

• Brings up the Identify Instrumentor graphical interface.

• Automatically imports the project file (*.prj) for the open project in the Synopsys FPGA synthesis tool into the Identify Instrumentor tool and opens the project.

• Automatically compiles the project.

Quick Start Guide


Graphical ModeTo start the Identify Instrumentor or Identify Debugger in the graphical mode, do any of the following depending on your platform/operating system:

• In Windows, select Programs->Synplicity->Identify Instrumentor or Programs->Synplicity->Identify Debugger from the start menu or enter the appropriate command at the command prompt:

path_to_identify_install_directory/bin/identify_instrumentorpath_to_identify_install_directory/bin/identify_debugger

• In Solaris/Linux, enter the appropriate command at the command prompt:

path_to_identify_install_directory/bin/identify_instrumentorpath_to_identify_install_directory/bin/identify_debugger

Note that the Identify Debugger can only be run from the Linux (or Windows) operating system and that it is not supported by the Solaris operating system.

The Identify Instrumentor or Identify Debugger can also be run with a Tcl startup file. To start the tool with a Tcl script, enter the appropriate command:

path_to_identify_install_directory/bin/identify_instrumentor -f fileName.tclpath_to_identify_install_directory/bin/identify_debugger -f fileName.tcl

Shell ModeBoth the Identify Instrumentor and Identify Debugger can be started in a shell mode and controlled by Tcl commands. To start either tool in the shell mode, enter the appropriate command at the command prompt:

path_to_identify_install_directory/bin/identify_instrumentor_shellpath_to_identify_install_directory/bin/identify_debugger_shell

Note that the Identify Debugger can only be run from the Linux or Windows operating system and that it is not supported by the Solaris operating system.

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Quick Start Guide


Vendor LicensesWhen you initially start the Identify Instrumentor or Identify Debugger, you are prompted to select the license type from the licenses available for your configuration. The following figure shows the Select available license dialog box with a full complement of license types.

To select a license type, highlight (click on) the entry and then click the Select button. To avoid being prompted for the license type each time you start the Identify Instrumentor or Identify Debugger, check the Save as default license type box before clicking the Select button.

After opening the Identify Instrumentor or Identify Debugger, you can change the license type from within the tool by selecting Help->Preferred License Selec-tion from the menu to display the Preferred license selection dialog box and then selecting a new license type as described in the previous paragraph.

Quick Start Guide


Design Flow with the Identify RTL DebuggerBecause the Identify RTL Debugger produces an instrumented version of your design, using this tool should be considered a pre-processing step in your current design flow. This Quick Start guide assumes that you currently have a working FPGA design flow for your Actel device. If not, use a simple design (for example, the tutorial design counter_self) to establish a working flow that effectively moves an HDL design through synthesis, place and route, and programming of the chip. Only after this flow is established should you attempt to debug a design with the Identify RTL Debugger.

Before you begin, it is also helpful to note the amount of unused resources available in your original design. The Identify Instrumentor provides an estimate of the additional resources necessary for instrumentation in the target device which can help maximize the debugging visibility.

The following figure shows a typical design flow using the Identify RTL Debugger.

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Quick Start Guide


Figure 1: Identify RTL Debugger Design Flow

Working HDL

IdentifyInstrumentor

IdentifyDebugger

Create a New Project

SelectInstrumentation

Configure IICE

CreateInstrumented

Design

Synthesize

Place and Route

OpenIdentify Project

in Debugger

Set TriggerCondition

Run DebugHardware

ViewDesign Data

ImportProject

Quick Start Guide


Create a New ProjectYou can import an existing Synopsys FPGA project directly into the Identify Instrumentor or you can create a new project from HDL source.

Creating a New Project from an Existing Synopsys FPGA ProjectFor Synopsys FPGA synthesis tool users, an existing Synopsys FPGA project file (*.prj) can be imported into the Identify Instrumentor to automatically create a new Identify project.

To import a Synplify, Synplify Pro, Synplify Premier, or Certify (single-chip) project into the Identify Instrumentor, open the project in the corresponding Synopsys FPGA Project view and:

1. Right click on the project (Synplify) or implementation (Synplify Pro, Synplify Premier, or Certify) to be imported and select New Identify Implementation from the popup menu.

2. Verify or set the technology and device mapping options as required. Make sure that a Top Level Module is specified on the Verilog tab or that a Top Level Entity is specified on the VHDL tab (see the implementation option descriptions in the Synopsys FPGA Synthesis User Guide or Certify User Guide for more information). Click OK to close the dialog box; a new Identify implementation is added to the project view.

Note: Because multiple implementations are not supported in the Synplify synthesis tool, the existing implementation is replaced with the Identify implementation.

IdentifyImplementation

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Quick Start Guide


3. Right click on the Identify implementation and select Launch Identify from the popup menu (in Synplify, Synplify Pro, and Synplify Premier, you can also click the Launch Identify Instrumentor toolbar icon).

4. In the Launch Identify dialog box, make sure that the Locate Identify Installation field points to the Identify Instrumentor executable (use the browse button to the right of the field if necessary) and make sure that the proper License Type is selected.

5. Click OK. If prompted to save your changes, click Save.

Clicking the OK button (or the Save button):

• Brings up the Identify Instrumentor graphical interface.

• Automatically imports the corresponding project file (*.prj) into the Identify Instrumentor tool and opens the project.

• Automatically compiles the project which allows the Identify Instru-mentor to determine all of the potential locations for instrumenting breakpoints and watchpoints.

Creating a New Project from HDL SourceTo create a new project from HDL source using the Identify Instrumentor graphical user interface (GUI):

1. Open the Identify Instrumentor in the GUI.

2. Click the Add Files button to bring up the Add Design Files dialog box.

3. Navigate to the directory containing your HDL design files. All HDL files are listed in the dialog box.

4. Select (highlight) the design file or files to be added to the project and click Open to add the files to the project. Use the Control and Shift keys to add multiple files.

5. The order shown in the list of files is the order in which the files are compiled. Use drag and drop to correct any file-order dependencies.

6. In the Compile Options section of the project window, enter the name of the top-level module or entity into the Top level unit field.

7. Click the Compile button, select Actions->Compile from the menu, or click the Compile current project icon to compile your project.

Quick Start Guide


Note: Alternatively, you can create a TCL script to add the files to your design. For information on scripting and the compile add command, see the reference manual.

Select Desired InstrumentationWhen your design compiles successfully, your design with its possible instru-mentation is displayed in the instrumentation window. The hierarchy browser on the left shows the design hierarchy and is used to browse your design. Double clicking any hierarchy symbol takes you to its corresponding code location in the HDL source code display on the right.

In the source code display, each potential watchpoint is indicated by a glasses icon prefixing the signal name, and each potential breakpoint is indicated by a circle in the left margin of the source code.

Figure 2: Potential watchpoints and breakpoints

Watchpopint

Breakpoint

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Quick Start Guide


WatchpointsA watchpoint is instrumented by clicking the watchpoint icon adjacent to the signal name and selecting Sample Only, Trigger Only, or Sample and Trigger from the pop-up menu.

• Sample-only signals are sampled by the debug logic. You can view the data from a sample-only signal, but you cannot use the signal to trigger the hardware during runtime. The lenses of the watchpoint icon are blue for sample-only signals.

• Trigger-only signals are not sampled by the debug logic and have no visibility. These signals are used to create trigger conditions to trigger the debug logic (IICE) during runtime. The lenses of the watchpoint icon are pink for trigger-only signals

• Sample and trigger signals connect to both the sample logic and trigger logic of the IICE. These signals are visible and can be used to trigger the debug logic. The lenses of the watchpoint icon are green for sample and trigger signals

Note: A fourth selection is available with vectored (bus) signals for defining watchpoint types on partial buses; see the User Guide for more information.

BreakpointsBreakpoints are instrumented by clicking on the icon to the left of the break-point line. A breakpoint is essentially a control-flow trigger. It is used at runtime to trigger the debug logic based on the flow through case and if/then/else statements. During debug, a breakpoint triggers the IICE whenever the corresponding branch in the code becomes active.

Resource EstimatesAs you select each watchpoint and breakpoint, the resource usage is updated in the console window. The usage reported is an estimate of the resources on the target device required for the additional instrumentation logic. The estimate depends on the number of signals and breakpoints selected for the instrumentation, as well as other IICE settings such as device family and sample depth. Please see the next section, Configure the IICE, for information about these settings.

Quick Start Guide


Note: The Identify Instrumentor is not aware of the size of the target device and it is possible to add more instrumentation to the design than will fit on the device. Exceeding the device capacity causes errors during synthesis or place and route.

Configure the IICEConfiguring an IICE to match your debugging requirements involves the setting of a series of IICE parameters. The common IICE parameters are set in the project window and apply to all IICE units defined for the currently-active implementation; the IICE parameters unique to each IICE definition in a multi-IICE configuration are interactively set on one of two IICE Configuration dialog box tabs.

Common IICE ParametersThe common IICE parameters for the currently-active instrumentation are set in the project window after a design is successfully compiled. All IICE units in a multi-IICE configuration share these same parameter values. To redisplay the project window, click the project window tab at the bottom of the window.

• Device Family – select the appropriate device technology for your Actel-based design. Notice that when you change the device family, the report window in the IICE editor updates the area estimate for that device family and that the resources are reported in technology-specific terms.

• JTAG Port – make sure the JTAG port selection box is set to builtin. This setting configures the IICE to use the built-in JTAG resources of the device. If access to the built-in JTAG port is not available, you must use the soft JTAG scheme which inserts a JTAG controller into the design and connects it to four user-defined pins (see the User Guide for more information about the soft JTAG).

• Use skew resistant hardware – make sure that the Use skew resistant hardware option is not checked; this option is used with designs that have no global clock buffer available for the JTAG clock. For more information, see the User Guide.

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Individual IICE ParametersThe individual parameters for each IICE are defined on the two tabs of the Configure IICE dialog box. To display this dialog box, select Actions->Configure IICE from the menu or click on the Edit IICE settings icon. When setting parameters for an individual IICE in a multi-IICE configuration, use the Current IICE field to specify the target IICE.

IICE Sampler TabThe IICE Sampler tab controls the size and implementation of the IICE sample buffer and defines the sample clock.

When setting these parameters:

• Make sure that the Buffertype field is set to deviceram. This setting ensures that the sample buffer is efficiently built from technology-specific RAM cells.

• Select the desired depth of the sample buffer. This setting controls the size of the sample trace for each signal. Keep in mind that with Identify, you will be able to set very specific triggers and thus may be able to use a smaller trace than required by a logic analyzer. Changing this field also updates the IICE estimate at the bottom of the IICE editor dialog box. For information on using a logic/behavioral Buffertype or the advanced sampling modes, see the User Guide.

• The Allow qualified sampling check box, when checked, causes the Identify Instrumentor to build an IICE block that is capable or performing quali-fied sampling. When qualified sampling is enabled, one data value is sampled each time the trigger condition is true. With qualified sampling, you can follow the operation of the design over a longer period of time (for example, you can observe the addresses in a number of bus cycles by sampling only one value for each bus cycle instead of a full trace). Using qualified sampling includes a slight area and clock-speed penalty.

Quick Start Guide


• The Allow always-armed triggering check box, when checked, saves the sample buffer for the most recent trigger and waits for the next trigger or until interrupted. When always-armed sampling is enabled, a snapshot is taken each time the trigger condition becomes true. With always-armed triggering, you always acquire the data associated with the last trigger condition prior to the interrupt. This mode is helpful when analyzing a design that uses a repeated pattern as a trigger (for example, bus cycles) and then randomly freezes. You can retrieve the data corre-sponding to the last time the repeated pattern occurred prior to freezing. Using always-armed sampling includes a slight area and clock-speed penalty.

• The Sample clock determines when signal data is captured by the IICE. The sample clock can be any signal in the design that is a single-bit scalar type. Enter the complete hierarchical path of the signal as the parameter value.

Note: You can also specify the sample clock signal by right-clicking on the watchpoint icon (or signal name) and selecting Sample Clock from the popup menu.

Care must be taken when selecting a sample clock because signals are sampled on an edge of the clock. For the sample values to be valid, the signals being sampled must be stable when the specified edge of the sample clock occurs. Usually, the sample clock is either the same clock that the sampled signals are synchronous with or a multiple of that clock. The sample clock must use a global clock resource of the chip.

Note: If you need help determining the hierarchical path of your clock, try finding it in the HDL source viewer. You may then add and remove it for instrumentation. The full hierarchical path of the signal will be echoed to the TCL command line. Remember that a signal cannot be used as the sample clock if it is instrumented.

• The Clock edge radio buttons determine if samples are taken on the rising (positive) or falling (negative) edge of the sample clock. The default is the positive edge.

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Quick Start Guide


IICE Controller TabThe IICE Controller tab customizes the trigger logic available for triggering the sample buffer. Select the Complex counter option and set its size to 32 to instrument a 32-bit counter for use with the triggering logic. This setting will enable you to use advanced trigger operations such as counting the number of trigger events or delaying a trigger event by a set amount of clock cycles. The state machine setting can be used to create fully flexible trigger conditions including capturing samples based on sequences of trigger events. See the User Guide for more information on state machine triggering.

The Export IICE trigger signal option brings out the IICE’s global trigger signal to the top level of your design. This signal can then be used to trigger a logic analyzer or to trigger another IICE.

The Allow cross triggering in IICE option, when enabled, allows the current IICE unit to accept a cross-trigger from another IICE unit.

Quick Start Guide


Create the Instrumented DesignWhen you are satisfied with the instrumentation, generate the new instrumented design by either selecting File->Save Project from the Instrumentor menu bar or clicking on the Save and instrument current project icon on the toolbar. When you generate the new instrumented design:

• the Identify Instrumentor writes out your identify project file (project-Name.bsp) to the specified directory. This project contains the information about the design and the instrumentation that you have applied to that design; the project can be opened and saved by both the Identify Instru-mentor and the Identify Debugger.

• the Identify Instrumentor creates the instrumentation directory named projectName_instr. This directory is created in the same directory as the project file and contains the design database used by the Identify Debugger and the instr_sources subdirectory that holds the newly instru-mented sources created by the Identify Instrumentor.

Once you have instrumented your design, you will begin the process of imple-menting the design and then debugging it. Note that any changes to the Identify project, the design files, or the instrumentation can cause the current project to become invalid. Take care not to change the instrumentation or otherwise overwrite the current project. The Identify Debugger takes many precautions to ensure correct sample data, and does not allow debugging of a design that has been changed or the viewing of files that have been modified. These types of changes may require you to re-run synthesis and place and route.

The Identify RTL Debugger allows you to create multiple instrumentations for a single design using another target device as well as using different IICE configuration parameters. Also, you can make incremental changes to the instrumentation set during the debug phase and then only run a partial place and route flow which can drastically reduce the debug cycle time. For infor-mation on multiple instrumentations and the incremental flow, see the User Guide.

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Synthesize and Place and Route the Design

Repeat Original Design Flow with Instrumented DesignWhen you have successfully created an instrumented design, run the design through the Synopsys FPGA synthesis design flow. If you are using scripts to run synthesis, it may be necessary to modify the existing scripts to use the new instrumented sources created in the instr_sources subdirectory.

Note: Always synthesize and place and route your instrumented design using all of the original constraints and settings.

Read the Project into the Synopsys FPGA Synthesis ToolWhen you launch the Identify Instrumentor from a Synopsys FPGA synthesis tool, the project file is automatically updated to describe the resulting Identify directory/file structure for the instrumented design. When you synthesize the design, the additional instrumentation logic is automatically included in the design as displayed in the RTL and technology views.

When you run the Identify Instrumentor in stand-alone mode (i.e., when the tool is not launched from a Synopsys FPGA synthesis tool), the Identify Instrumentor creates a Tcl script file named synplify.tcl in the instrumentation directory projectName_instr. This file is then imported into the Synopsys FPGA synthesis tool (Run->Run Tcl Script) to create the synthesis project file and load the instrumented design into the synthesis tool.

Add JTAG Clock ConstraintsDuring synthesis, it is important that the JTAG clocks added by Identify are properly constrained (the JTAG clock runs at a very slow speed and must not be optimized to the speed of the design clocks). These clock constraints are handled automatically by the Identify Instrumentor by the syn_dics.sdc constraint file from the projectName_instr/instr_sources directory referenced in the project file.

Any signal with a name that includes identify_clk must be constrained to run at 25MHz (40ns) or less. For the place and route tools, the same precautions must be taken to constrain the JTAG clocks to run at 25MHz (40ns) or less.

Quick Start Guide


Program the Instrumented Bit File to the Target DeviceWhen all of the required project files are in place, program the instrumented bit file into the targeted device to load the design logic and the required instrumented logic.

Open the Identify Project in the DebuggerAny project (*.bsp) that has been instrumented by the Identify Instrumentor can be opened in the Identify Debugger. The Identify Debugger appears similar to the Identify Instrumentor except that only instrumented signals and breakpoints are displayed in the Identify Debugger. If the Identify Debugger is being run on a machine that is different from the host where the design was instrumented, see Debugging on a Different Machine on page 23 of this guide.

Set Trigger ConditionSetting the trigger condition involves setting breakpoints and/or watchpoints in the source code window to trigger the IICE when the associated condition occurs.

Setting BreakpointsPotential breakpoints are indicated by a green circle in the margin to the left of the source code. Clicking on a breakpoint activates the breakpoint and changes the color of the circle from green to red.

Setting WatchpointsWatchpoint triggers can be specified on any sampled signal. The watchpoint condition, which is any legal VHDL or Verilog expression that evaluates to a constant, is set through the user interface.

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To set a simple watchpoint:

1. Click on the signal

2. Select Set trigger expressions from the popup menu to display the Watchpoint Setup dialog box

3. In the First value field, enter a value for the watch expression.

4. Click OK

The setting of the watchpoint trigger is noted by the breakpoint icon next to the watched signal changing from green to red.

Multiple Breakpoints and WatchpointsWhen an instrumented design has more than one activated breakpoint, the breakpoint events are ORed together which effectively allows the breakpoints to operate independently – only one activated breakpoint must trigger to cause the sampling buffer to acquire its sample.

When an instrumented design has more than one activated watchpoint, the watchpoint events are ANDed together which effectively causes the watch-points to be dependent on each other – all activated watchpoint events must occur coincidently to cause the sampling buffer to acquire its sample.

When an instrumented design has one or more activated breakpoints and one or more activated watchpoints, the result of the OR of the breakpoint events and the result of the AND of the watchpoint events are ANDed together. The result of this AND operation is called the Master Trigger Signal. This ANDing effectively causes the breakpoints and watchpoints to be depen-dent on each other – one activated breakpoint and all activated watchpoint events must occur coincidently to cause the sampling buffer to acquire its sample.

Quick Start Guide


Run Debug HardwareThis guide assumes that the Identify Debugger communicates with the instrumentation through the same cable that was originally used to program the device. If another communications methodology is being used, see the Connecting to the Target System chapter in the user guide. Before running the debug hardware, test your communications setup with the com check command. This command:

• checks the cable connection

• auto-detects the devices on the JTAG chain

• auto-detects the device with instrumentation that matches the current project

If errors are reported, see Communication Errors on page 21 for possible explanations.

After all of the desired breakpoints and/or watchpoints have been activated, the IICE trigger circuits on the FPGA device are then armed and wait for the watchpointed condition to occur. To arm the IICE trigger circuits on the active IICE, click the Arm current IICE for triggering

icon. To arm more than one IICE in a multi-IICE configuration, open the project window in the Identify Debugger, check the individual IICE units to be armed, and then click the Run button. Either of these actions downloads the trigger information to the IICE. The IICE now waits for the trigger condition (watchpoint or breakpoint) to occur.

When a watchpoint or breakpoint trigger occurs, sampling is stopped (the hardware continues to run), and the sampled data is transferred back to the debugger where it is displayed in yellow adjacent to the sampled signals in the source code. A small arrow is displayed to the left of the breakpoint or watchpoint icon to indicate the condition that was responsible for the trigger (identifying the trigger condition is important when multiple breakpoints or watchpoints are active).

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Quick Start Guide


View Design DataThe sample buffer display can be varied by time. The Cycle display in the middle of the menu bar shows the value zero. This is the point in the sample data buffer where the trigger occurred. By clicking on the up-down arrows on the right, you can increase or decrease the cycle count to show sample buffer values before or after the trigger point.

You can change where the trigger point is in the buffer by selecting one of the Early, Middle, or Late buttons and then clicking on the Run button again. The trigger location changes the next time that the IICE triggers.

Figure 3: Trigger-location selection buttons

Waveform DisplayIn addition to displaying the sampled data for the selected signals, the Identify Debugger can export the sample buffer contents for display in a variety of waveform viewers (GTKWave, Aldec Active-HDL, Novas Debussy).

Select GTKWave PreferenceSelect Options->Debugger preferences from the menu bar. Verify that GTKWave is the selected choice in the Waveform Viewer Preferences dialog box.

Note: GTKWave is the freeware waveform viewer that is distributed with the Identify RTL Debugger.

Click “Waveform” ButtonSelect Window->Waveform or click the icon labeled Open Waveform Display in the Identify Debugger toolbar. A GTKWave waveform display is shown which displays all of the sampled data for each of the sampled signals. Identify adds two signals to this waveform:

• identify_cycle – an integer that shows the position in the sample buffer. A value of 0 indicates the cycle in which the trigger event occurred.

Early Middle Late

Quick Start Guide


• identify_sampleclock – a single-bit signal that shows the edges of the refer-ence clock.

Communication ErrorsThe following are common errors that you may encounter when setting up communications with the Identify Debugger.

" ERROR: Communication is stuck at one/zero. Please check the cable connection.The Identify Debugger is unable to communicate with the instrumented device. This error is usually attributed to a cable connection problem. Make sure that the cable is correctly connected between the parallel/USB port and the JTAG port of the board and verify that the cable type is set correctly in the project editor (select File->Edit Project or use the com cabletype TCL command).

Note: IMPORTANT – This error is often caused by an incorrect parallel port setting. Please try all choices for the communications port setting using either the command line or the selection box in the Identify Debugger project editor.

" ERROR: Cannot find valid instrumented design.This error indicates that the design on the programmable chip is NOT the instrumented version of the design. Verify that the bit file you are programming is actually created from the instrumented sources and that the debug logic (IICE) has not been removed during implementation. Verification can often be done by searching the intermediate place and route files for the word “identify.”

" ERROR: Instrumented design on FPGA differs from design loaded into Identify Debugger.

This error indicates that the Identify Debugger cannot find a device in the JTAG chain that has been instrumented by the Identify Instru-mentor. In this case, the ID of the instrumentation does not match the ID of the currently loaded project. Please verify that the correct project is loaded for the corresponding bit file. The error occurs when the project is re-instrumented without regenerating a bit file. If you have changed the design or its instrumentation, you must create a new bit file before debugging the design.

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Quick Start Guide


" ERROR: No hardware devices were found. Please check the cable connection.This error indicates that no devices are visible in the JTAG identification register chain. The error is usually caused by a bad cable connection or an incorrect cable type setting.

" ERROR: The hardware has not seen an active clock edge of the sample clock.This error usually indicates that the Identify hardware is functioning correctly and that the Identify Debugger is able to communicate with the device, but that the sample clock is not being toggled. This error can be caused if the wrong clock is chosen in the Identify Instrumentor. Please verify that the correct sample clock is selected using the iice clock command. Also check that the clock signal is using the global clock resources of the chip.

Note: This error often occurs when the clock signal is not assigned correctly to the clock pin on the board. Verify that, during place-ment, the clock signal (sample clock) is correctly assigned to the chip pin that is connected to the clock oscillator on the board.

" ERROR: Hardware driver failure.

This error usually indicates that the correct port driver is not installed on the debug system. Please see the release notes for help installing the port driver.

Clock SkewWhen the data returned from the Identify Debugger appears incorrect or does not properly relate to the given trigger condition, there may be an issue with clock skew on the JTAG clock. Make sure that the identify_clk signal is using the global clock resources on the chip. If there is no clock buffer available, you may have the Identify Instrumentor build skew-resistant hardware. Please see the user guide for more information on skew-free hardware.

Quick Start Guide


Debug ModeIf you are experiencing a communication error that is not listed above or if you have not been able to resolve the error, contact [email protected]. If may be helpful to run the Identify Debugger in “debug” mode as outlined below:

1. If open, close the Debugger.

2. Right-click the Identify Debugger shortcut on the desktop and select Properties from the popup menu to display the Properties dialog box.

3. Append the -debug flag to the path to the executable in the target field.

4. Restart the Identify Debugger and reopen the project.

5. Enter the following two commands at the command prompt in the Console window:

chain clearcom check

6. Make a copy of the log file and send it with any other important details about your particular setup/flow as well as the Identify project file (*.bsp) to [email protected].

Debugging on a Different MachineIt is not unusual for the instrumentation phase and the debugging phase to be performed on different machines. For example, the debug machine is often located in a hardware lab. When a different machine is used for debugging, you must copy both the Identify project file (projectName.bsp) and the instru-mentation directory (projectName_instr) to the lab machine.

Because the Identify RTL Debugger allows you to debug your design in the HDL, the Identify Debugger must have access to the original source files. Depending on the type of your network, the Identify Debugger may be able to access the original sources files directly from the lab machine. If this is not possible or if the two computers are not networked, you must also transfer the original sources to the debug machine. If the Identify Debugger cannot locate the original source files, it will open the project, but an error will be generated for each missing file, and the corresponding source code will not be visible in the source viewer.

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Quick Start Guide


Copying the source files to the debug machine can be done in two ways:

• Identify can automatically copy the original source files into the instru-mentation directory so that when you copy the instrumentation direc-tory (projectName_instr) to the lab machine, the original sources will be included. The Identify Debugger automatically looks in this directory for any missing source files. This preference can be set before instrumenta-tion by selecting Options->Instrumentation preference and making sure that Save original source in instrumentation directory is checked.

• The original source files can be manually copied to the lab machine or may already exist in a different location on this machine. In this case, it may be necessary to help Identify find the design files using the search-path command. Simply call this command from the command line before loading the Identify project file (*.bsp). The argument is a semi-colon-separated list of directories in which to find the original source files.

searchpath {d:/temp;c:/Documents and Settings/me/my_design/}

The Identify Debugger will only display files that match the CRC taken at the time of instrumentation.

Note: If there are security issues with having the original source files on the lab machine, the Identify Instrumentor can password-protect the original sources for use with the Identify Debugger (for information on file encryption, see the User Guide).