A Wideband CMOS Multiplier for UWB ApplicationYuan Gao("2 , Kaizhi Cai 2), Yuanjin Zheng(') and Ban-Leong Ooi(2)

(1) Institute of Microelectronics, #1 1 Science Park Rd, Science Park II, Singapore, 117685yuanjin@ ime. a- star.edu. sg

(2) Department of Electrical and Computer Engineering, National University of Singapore10 Kent Ridge Crescent, Singapore, 119260

Abstract - This paper describes a novel wideband CMOSdifferential four-quadrant analog multiplier which is part of aintegrated correlator aiming for application in Ultra-Wideband II. MULTIPLIER DESIGN(UJWB) transceiver. By combining a conventional Gilbert cell anda gate-source injection multiplier with flipped voltage followers . The proosed multler structure iS shown in Fig. 1. It iStogether, wide operation bandwidth is achieved with enhanced based on the transconductance multiplier structure reported inconversion gain. Simulation results show that the multiplier can [4]. This multiplier can be divided into two sub-circuits whichprovide a bandwidth of up to 9.2GHz and a conversion gain of 19 includes a gate-source injection multiplier and a conventionaldB. This multiplier is able to operate with a 0.2ns narrow Gilbert cell. Transistors M M M and M work as themonocycle pulse. The proposed circuit has been designed and 5, 67 7 8

simulated using commercial 0.18-jim CMOS process and the transistor pairs to form a classical gate-source injectionpower consumption is 10.8mW under a 1.8V DC voltage supply. multiplier. Transistors M1, M2, M3 and M4 form two FlippedIndex Terms - CMOS, Ultra-Wideband (UWB), multipliers, voltage followers (FVF) [5] to act as the inputs to the source

correlator. nodes of transistors M5-8. Transistors M9 and M1o are biased inthe linear region to improve the bandwidth of the multipliercircuit while M1l and M12 form a conventional Gilbert cell with

I. INTRODUCTION M58 The received RF signal is simultaneously connected toUltra-Wideband (UWB) is a short-range radio technology the input of gate-source injection multiplier and Gilbert cell.

that is able to provide power-efficient, wide bandwidth Since the output voltage of two multipliers has the samesolutions for short-range data transmission [1]. Since Federal polarization at the common output port, so that the overallCommunications Commission (FCC) approved the UWB conversion gain is enhanced.spectrum regulation in 2002, the design and implementation ofUWB systems have attracted great attentions. It has been VDD VDDproven that UWB communication system has the unique L Ladvantages of low system complexity, noise-like spectrumwhich is resistant to severe multi-path fading and excellenttime domain resolution that allowing for location and tracking RL RLapplications [2-3]. vo +±

In the UWB transceiver, wideband correlator is a keycomponent which can convert the received RF signal tobaseband for pulse detection. A correlator usually consists of a +X +x

linear multiplier and followed by an integrator. In the UWB VDD VDDcorrelator, the multiplier is required to provide wide M M6 M M8

bandwidth and large conversion gain, so that the transmittingsignal waveform can be recovered efficiently. These +y -yL Y

requirements raise a challenge in multiplier design especially mg

in the CMOS process.TIn this paper, a wideband CMOS differential four-quadrant |b

analog multiplier is presented. By combining a conventional Vb VbGilbert cell and a gate-source injection multiplier together, a -y M12 ±ywideband multiplier which can provide a 9.2 GHz bandwidthwithout load and a conversion gain of 19 dB is achieved.Flipped voltage followers and current reuse technique are both Fig. 1. Schematic diagram of the proposed multiplier. Common modeutilized to enhance the conversion gain and reduce the current voltages are not shown in the figure for simplicity.consumption.

1-4244-0521l-1/07/$20.00 ©2007 IEEE

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III. CIRCUIT ANALYSIS current multiplication. The output current Iou, of the Gilbert

The analysis of the proposed multiplier structure is based on cell alone is given below in Eq. (6) and (7) for completenessthe superposition of the gate-source injection multiplier with and quick reference.FVF and a Gilbert cell. Individual analysis of each circuit ispresented in the following sections.

A. Linear Transconductor V Ml rMTransistors M5, M6, M7 and M8 function as the

transcondctors which convert the input voltage signal to Vout Voutcurrent to implement the multiplication. Referring to the V VOUnotation in Fig. 1 and applying standard square-law model of M2MOS devices in the saturation region, the current flowingthrough each transistor is:

Fig. 2. (a) Common-drain amplifier (b) FVF.

Im = k- (W/ L) [C + (+X-y)]2 (1)

Im Il2k-(WIL)[C+(_Xy)]2 (2) F1.'m6=1 n

Im7 =I/ kn (W I L) [C + (_x + y)]2 (3) iout2 =2k5x A kl if-2 + 2y

/2 n 5~~~~~~~~~3)'ut

Im7 = kn (WIL)[C + (+x + y)] (4) ! (6)

Where C=X-Y-V -(k11 sTherefore, the gain of the source injection multiplier is given k5by:

out = (I6 + '8) - (15 + I7) = 4kn(W / L)xy (5) Assuming x and y are small signals, Eq. (6) can be written as

iout2 = 4,A2/ COxy (7)

B. Gate-Source Injection Implementation 2 L 5

The conventional common drain amplifier shown in Fig.2(a) is often used to provide the source voltage for the linear D. Combined Circuittransconductors. However, the drawback of this structure is In order to increase the conversion gain of the gate-sourcethat the current flowing through M1 depends on the output

wil 1 11injection multiplier, various methods can be utilized. Bycurrent. Hence, when the load is small, the voltage gain wcll. W. I . . vbe much smaller than unity. The FVF structure shown in Fig. . t

2(b) is able to solve this problem, since the current flowing gain of the multiplier. However, the increase of W/L ratio willthrough transistor Ml is fixed and independent of the output introduce parasitic capacitances, resulting in bandwidthcur*entvariation [5]. Hence, FVF has the advantage of using a reduction. A larger W/L ratio will also lead to higher currentmuch smaller current to bias the circuit and providing a much mption if the same biasing voltages X and Y are

higher gain at the same time. maintained. Using a larger output resistor will also improveThe gate-source injection multiplier consists of the the gain of the circuit but it will lower the circuit driving

transistors M10 shown in Fig. 1. Transistors M9 and M10 are capability and bandwidth as well. Hence, there are great. - . . 9 10 . demands for novel designs to improve the gain and bandwidthincluded to improve the bandwidth of the circuit by moving of the multiplier without the performance tradeoffs.

the non-dominant pole at the source node of M58 to a higher The main advantage of combining FVF and Gilbert cellfrequency. Moreover, the dominant pole of the circuit is together is the biasing current reduction due to the currentcancelled by the shunt peaking inductor L, which will further reuse. In order to illustrate the working mechanism, a halfexpand the circuit bandwidth. multiplier circuit, with and without the Gilbert cell is shown in

Fig. 3(a) and (b). The total biasing current of the circuit is 15 +C. Gilbert Cell Implementation 16, as shown in Fig. 4. In Fig. 3(a), the DC biasing current 15 +

16 flows into transistor M2. However, in Fig. 3(b), the DCThe conventional Gilbert cell has been extensively studied and biasing current 15 ± '6 flows into both transistors I2 and I11.its equations derivation process can be found in [6-7]. In the Both the FVF and transistor WI11 can work in the amplifyingproposed multiplier structure, transistor M11 and M12 are region with the same amount of biasing current 15 ± '6 if theemployed to form a Gilbert cell with transistors M58 to provide

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transistor biasing points are properly determined. By simulation of the two input pulses and Fig. 9 shows thesuperposition, the total output current Itot,, is: transient simulation results of the multiplier output. It shows

~- ,uC (W> that the multiplier has sufficient bandwidth and is able to workItotal = Ioutl + Iout2 = (2X2 +4) OX Xy (8) with the sub-nanosecond pulse input. The simulated DC

2 L 5 power consumption is 10.8 mW under a 1.8V DC powerHence, the gain of the overall circuit can be improved while supply. The overall multiplier performance summary is shownusing the same amount of current. in Table I.

15 16 i6

VDD + - =11

M M

15+16 '6 ipt

10;

Vb ~ ~~ ~~~~~~ ~I~~ES lE9 lEIO MEl

(b) Frequency 1z)Fig. 5. The simulated frequency response ofthe multiplier with x

Fig. 3. DC analysis ofthe halfMultiplier (a) without Ml11 (b) with input.M11.

IV. SIMULATION RESULTS

The wideband multiplier is designed under a commercial t

Agilent Advanced Design System (ADS) and based on the 00^t =device models provided by the foundry. Fig. 4 shows the ,frequency response of the multiplier with y input (RF input) _ 1 iand Fig. 5 shows the frequency response of the multiplier withIx input (LO input). The -3dB bandwidth of the multiplier iSabout 9.2 GHz with a conversion gain of 19 dB. The DC I'l4IIIpTe iThT VVTT1transfer characteristics of the multiplier with input from ports ~ 0AQ 4~Q O...OQ. 100 Q5 OiC0 Y0g150 0.20x andy are shown in Fig. 6 and Fig. 7 respectively. 2xV)

In order to test the time domain responses, two monocycle Fig. 6. Multiplier DC transfer characteristics versus input x.pulses with the same width of 0.2 ns are used. Fig. 8 shows the

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O.04 7 _T _V. CONCLUSION

A novel wideband four quadrant CMOS multiplier forWBapplication has been presented. The structure of the

multiplier is based on the superposition of gate-sourcet gg 4 D 0 injection multipliers with flipped voltage followers and the

conventional Gilbert cell. The simulation results show that the*0.2 < _ multiplier has a bandwidth of 9.2 GHz without the load and a

conversion gain of 19 dB. The multiplier is operated undersingle 1.8V voltage supply and it is a good candidate forimplementing the high performance correlator in UWB

2y (V) transceivers.

Fig. 7. Multiplier DC transfer characteristics versus input y.Table I. PERFORMANCE SUMMARY

0.2 -H Parameter ValueTechnology 0.18-pm CMOS

01 Voltage Supply 1.8 VBandwidth 9.2 GHz

00 _ . 4 . I . I 1 .IVoltage Conversion Gain 19 dBC ___I_I_I__I_I___I__I_I_ILinear input range ±0.15 V

-0.1 Power Consumption 10.8 mW

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