Design of an Optimized Electrothermal Filter for a Temperature-to-Frequency Converter

S. Xia and K.A.A. Makinwa Electronic Instrumentation Laboratory

Delft University of Technology Delft, The Netherlands

Abstract—In this paper, an analytical model of an electrothermal filter (ETF) is described. It is based on thermal impedance theory and employs several simplifying assumptions to model an ETF implemented in CMOS technology. A CMOS ETF’s phase-shift has a well-defined temperature dependence, and can be utilized to build temperature-to-frequency converters (TFC). However, the resolution of such converters is limited by the ETF’s SNR. The analytical model was used to design an optimized ETF with increased SNR in a standard 0.7-µm CMOS process. Compared to a previous design, a TFC employing this new ETF achieved 30% less output frequency jitter.

I. INTRODUCTION Most integrated temperature sensors make use of the

well-defined temperature dependence of bipolar transistors [1]. Due to process spread, however, such sensors are intrinsically inaccurate, with temperature measurement spread of a few degrees Celsius. By calibrating and trimming individual sensors, a much lower inaccuracy of less than ±0.1ºC (3σ) can be achieved [2]. However, this is at the expense of increased manufacturing costs. Another class of integrated temperature sensors utilizes the temperature dependence of an electrothermal filter (ETF) [3]-[6]. It has recently been shown that this class of temperature sensors has high intrinsic accuracy [6].

An ETF consists of a heater and a temperature sensor, both of which are available in most IC processes. Unlike conventional filters, the signal filtering of an ETF occurs in the thermal domain. Electrical power dissipated in the heater induces temperature variations in the substrate, which are then converted back to the electrical domain by the temperature sensor. Due to the substrate’s thermal inertia, this structure will behave like a low-pass filter. The phase-shift of such an ETF is determined by its geometry and by the thermal diffusion constant of the substrate. The former is defined by lithography and can be made very accurate by making the structure sufficiently large. The latter is essentially process-independent for IC-grade silicon, and has a well-defined temperature dependence [7]. As a result, the phase-shift of a properly designed ETF will be a well-defined function of temperature.

The phase-shift of an ETF can be measured by using it to define the operating frequency of an oscillator [4]-[6]. The frequency of the oscillator will then be a well-defined function of temperature. A temperature-to-frequency converter (TFC) utilizing this property has achieved an untrimmed inaccuracy of less than ±0.5ºC (3σ) over the temperature range from -40ºC to 105ºC [6], which is comparable with the inaccuracy of batch-calibrated bipolar-transistor-based temperature sensors [2].

The temperature sensing accuracy of an ETF-based temperature sensor depends on the geometry of the ETF, since the major source of phase-shift spread in a properly designed ETF is lithographic error. To mitigate this, the temperature sensor needs to be located sufficiently far away from the heater. However, because silicon is a good thermal conductor, the output of an ETF is rather small (at the millivolt level), and has a poor SNR. The resulting electrothermal oscillator may then suffer from excessive jitter [4]. Although the jitter problem can be circumvented by constructing a frequency-locked-loop around an ETF to reduce the noise bandwidth [5] [6], it is still desirable to have a more efficient ETF structure to be able to further reduce the necessary power dissipated in the heater. To this end, an accurate thermal model of an ETF is needed.

II. ETFS IN CMOS TECHNOLOGY An ETF can easily be realized in a standard CMOS

technology by integrating a heater and a temperature sensor in the substrate of a CMOS chip. The heater can be realized by a resistor. Among the various resistors in a CMOS process, diffusion resistors are favored because they are located in the substrate, and hence are in good thermal contact with it. The temperature sensor is realized with a thermopile made up of p+-diffusion/aluminum thermo-couples. Compared to other integrated temperature sensors such as transistors and resistors, thermocouples do not need biasing, and are free of offset and 1/f noise, which makes them suitable for measuring small on-chip temperature variations. Furthermore, the temperature sensing points of a thermocouple, being the contact points of the two materials that form it, can be made quite small (a few square microns). This will ensure a good definition of the distance s between

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the heater and the sensor, which will determine the ETF’s phase-shift. For the thermocouple, the p+-diffusion resistor/aluminum type is favored because it has a relatively high sensitivity (about 0.5mV/K) [8], and because it is realized in an n-well, which can act as a shield from noise in the substrate. The schematic layout of an ETF in CMOS is shown in Fig. 1.

Figure 1. Schematic layout of an electrothermal filter

III. MODELING THE ETF The input of an ETF is heat generated by electrical power,

while its output is a temperature rise with respect to ambient temperature. The transfer function that relates them is the thermal impedance, defined as:

( )( )( )th

TZQ

ωωω

∆= (1)

The thermal impedance Zth of an ETF is important for studying its frequency-domain characteristics. Since the generated heat spreads through the substrate mainly by means of conduction, Zth can be obtained by solving the heat diffusion equation in the frequency domain [9].

2 2( , ) ( , ) 0T r q T rω ω∇ − = (2)

In this formula, r is the distance from the heater center to the sensor, q2=jω/D, where D= k/ρcp is the thermal diffusivity of the substrate, k is the thermal conductivity, ρ is the density and cp is the specific heat.

The thermal impedance of a realizable heater in CMOS technology is often very difficult to calculate. In fact, closed-form solutions of equation (2) only exist for some elementary geometries with special boundary conditions. For example, the thermal impedance of a point source in an infinite homogenous heat conducting medium can be expressed as [9]:

1( , ) exp( )4

1 exp( ) exp( )4 2 2

thjZ r r

kr D

r j rkr D D

ωωπ

ω ωπ

= −

= − −i (3)

Alternatively, the thermal impedance of an arbitrary-shaped heater in an infinite homogenous heat conducting medium can be approximated by first dividing the heater into several heated bodies of elementary shape that have closed-form analytical solutions, and then adding their thermal impedances to obtain the total thermal impedance [9].

In CMOS technology, the heater is located at the surface of the substrate. The oxide layer on top of the substrate can be considered as ideal thermal insulator, since its thermal conductivity is nearly two orders of magnitude lower than that of the silicon substrate. Also, the size of a typical ETF is much smaller than the dimensions of the substrate (several tens of microns versus more than 500 microns). Therefore, it can be assumed that the heat generated by the heater diffuses in a semi-infinite medium. The thermal impedance solutions of a heater in an infinite medium can easily be used in a semi-infinite medium by using the mirror image technique, as shown in Fig. 2. The effect of the thermal insulating layer can be modeled by placing an image heater symmetrically above the surface [9]. Both the original heater and the image heater are now inside an infinite medium and the thermal impedance including the effect of the insulating surface equals the sum of the thermal impedance of the original heater and the image heater.

With the above mentioned simplifying assumptions, the thermal impedance of an ETF in CMOS technology can be approximated. Based on this, an analytical model can then be built to predict the properties of an ETF.

Figure 2. The effect of a thermal insulating layer

IV. DESIGN OF AN IMPROVED ETF The analytical thermal impedance model so obtained was

used to optimize the layout of the ETF described in [6]. As shown in Fig. 3. It consists of a thermopile whose 20 identical thermocouples are located on both sides of a long, bar-shaped heater. The distance between the heater central axis line and each hot junction (the thermocouple junction closest to the heater) is 20µm. The thermocouple length was chosen to be 40µm to ensure that the thermal response of the cold junctions is negligible compared with that of the hot junctions.

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Figure 3: Layout of the original ETF, with a bar heater and a thermopile that consists of 20 thermocouples

Figure 4: Layout of the new ETF, with a folded heater and a thermopile that consists of 32 thermocouples

The TFC is designed such that its output frequency corresponds to an ETF’s phase-shift of approximately 90º [6]; this frequency will be referred to as f90. To ensure a fair comparison, the new ETF is designed to have the same f90 as the old one, but with as large as possible output signal under the same heater power dissipation. The lengths of the various thermocouples must also be optimized, since they are related to the thermocouple’s resistance and hence to their thermal noise.

According to the simulation results, a more compact heater structure is better for the thermal efficiency of an ETF. Therefore, a folded ‘U’ shaped resistor with minimum width is used to implement the heater. The hot junctions of the thermopile should be placed symmetrically around the heater, such that each thermocouple contributes equally to the ETF output. In order to achieve a higher SNR, the lengths of the thermocouples are shortened and the thermal response of the cold junctions can no longer be considered negligible. The resulting ETF structure is shown in Fig. 4. It can be seen that the hot junctions and cold junctions are roughly located on two concentric circles around the heater. So the filter’s geometry can be expressed in terms of two radii, rhot and rcold. However, this is only an approximate

description as the exact positions of the thermopile junctions are influenced by the heater’s geometry and do not lie exactly on a circle. For the new ETF, rhot is roughly 25µm and rcold is roughly 45µm.

According to the model, the new ETF will have a slightly lower f90 than the old ETF (0.6% lower at 300K). Also, for the same heater power dissipation, the output signal amplitude of the new ETF will be 29% larger than that of the old ETF.

V. MEASUREMENT RESULTS To compare the performance of the two ETFs, both of

them were used to build TFCs. Each TFC is essentially a frequency-locked-loop (FLL), which is arranged such that its steady-state output frequency corresponds to a fixed phase-shift of approximately 90º in the ETF [6]. Both the old ETF and the new ETF, together with the front end of the TFC, were realized on a 2.2 mm2 chip fabricated in a standard 0.7-µm CMOS process. The rest of the TFC was implemented off-chip. Measurements were made on 20 samples from one batch over the temperature range from -55ºC to 120ºC.

The measured f90-temperature relationships of both ETFs at a heater power dissipation of 2.5 mW are shown in Fig. 5. It can be seen that the f90 of the new ETF is indeed very close to that of the old ETF. At 300K, the f90 of the new ETF is 101.3 kHz while that of the old ETF is 101.6 kHz, which is only 0.3% lower. Both curves show the expected 1/Tn dependence, where T is the absolute temperature. The fitting parameter n for both ETFs is approximately 1.8. However, the measured f90 is about 23% lower than the value predicted by the analytical model. The reason for this discrepancy is still under investigation.

At f90, the measured output signal level of the new ETF was 20% higher than that of the old ETF, which is lower than the 29% increase predicted by the model. The measured jitter at the output of the TFCs employing the two ETFs is shown in Fig. 6. The heater power dissipation for this measurement was 5 mW. It can be seen that with the new ETF, the TFC exhibited almost 30% less jitter, which is less than ±0.1% (3σ). This level of jitter corresponds to a temperature-sensing resolution of less than ±0.2ºC. The noise bandwidth for this measurement was approximately 4 Hz, as estimated from the system’s step response.

At 2.5 mW heater power dissipation, for both ETFs, the TFC has an inaccuracy of less than ±0.8ºC (3σ) over the temperature range from -55ºC to 120ºC (Fig. 7). Considering the larger sample size (20 samples versus 9 in [6]) and the larger temperature span (-55ºC to 120ºC versus -40ºC to 105ºC in [6]), this is in good agreement with earlier results.

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Figure 5. Measured f90-temperature relationships with the two ETFs

Figure 6. Measured TFC percentage frequency jitter (3σ) with the two ETFs

VI. CONCLUSIONS An analytical model of an electrothermal filter (ETF)

based on the thermal impedance theory has been described. It was then used to optimize the old ETF for higher thermal efficiency. The optimized ETF was designed to have the same f90 as the old ETF, but with a 29% higher output signal amplitude and a higher SNR.

Both ETFs were realized on a test chip fabricated in a standard 0.7-µm CMOS process, and their performance was compared. Measurements on 20 samples from one batch showed that although the measured values of f90 for both ETFs were lower than the value predicted by the analytical model, they were almost exactly the same, as was expected. A TFC employing the new ETF had 30% less output frequency jitter than a TFC employing the old ETF. The temperature measurement spread achieved with both ETFs was the same, and was less than ±0.8ºC (3σ) over the temperature range from -55ºC to 120ºC.

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Figure. 7: Temperature measurement spread with 3σ values obtained

with two ETFs

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