Low Voltage CMOS Fully Differential Current Feedback Amplifier with Controllable 3-dB Bandwidth

Ahmed H. Madian Electronics and Communications,

Faculty of Engineering, Cairo University

Giza, Egypt

Soliman A. Mahmoud Electrical Engineering dept., German University in Cairo

Cairo, Egypt

Ahmed M. Soliman Electronics and Communications,

Faculty of Engineering, Cairo University

Giza, EgyptAbstract— This paper presents a CMOS fully differential current feedback operational amplifier with controllable 3-dB bandwidth. The FDCFOA has the advantage of a wide range controllable 3-dB bandwidth (∼57MHz to 500MHz) without changing the feedback resistance. The FDCFOA has a standby current of 320µA. PSpice simulations of the FDCFOA block were given using 0.25µm CMOS technology from AMI MOSIS and dual supply voltages ±0.75V.

I. INTRODUCTION In recent years, great interest has been devoted to the

current-feedback integrated circuits operational amplifiers (CFOAs) [1]-[13]. The current feedback circuits exhibits better performance, particularly higher speed, high slew-rate, and better bandwidth [5], than classic voltage-mode op-amp, which are limited by a constant gain-bandwidth product. The CFOAs are typically built by cascading a positive current conveyor (CCII+) with a buffer [6]. There are two trends to use current feedback op-amp (CFOA), the first trend uses it as a conventional CFOAs with four terminals device [1]-[9], as shown in Fig. 1(a), while the second trend uses CFOAs to realize operational amplifier with the CFOA benefits of independent gain-bandwidth, as shown in Fig. 1(b) [11]-[13].

In this paper, a CMOS fully differential current feedback amplifier with controllable 3-dB bandwidth, whose block diagram shown in Fig. 2, has been presented. The FDCFOA combines the advantages of the CFOA over the op-amp, and the fully differential over the single-ended. Also, it gives a wide range of controllable 3-dB bandwidth without changing the feedback resistance Rf, this gives stability for the FDCFOA. Fully differential architectures improve the performance of analog and mixed analog/digital systems in terms of supply noise rejection, dynamic range, and harmonic distortion [9] – [10].

The FDCFOA is basically a fully differential device as shown in Fig. 2. The Y1 and Y2 terminals are the high input impedance terminals while the X1 and X2 terminals are low impedance ones. The differential input voltage Vin1 applied across Y1 and Y2 terminals is conveyed to a differential voltage Vin2 across the X1 and X2 terminals, (Vin1 = Vin2). The input current applied to the X1 and X2 terminals are

conveyed to the Z1 and Z2 terminals, (IX1 = IZ1 and IX2 = IZ2). The Z1 and Z2 are high impedance output nodes suitable for current outputs. The Z1 and Z2 terminals are connected to two equal resistances Rl, to convert the output current into input voltage for the fully differential op-amp. The differential voltage developed across Z1 and Z2 are applied to the input differential voltage of the fully differential op-amp. This moves the high voltage swing from the Z1 and Z2 terminals to the fully differential op-amp while it is operating in the open-loop configuration. This topology has the advantages of controlling the 3-dB bandwidth of the FDCFOA with fixed feedback resistance Rf this supports the stability of the CFOA. Also, it reduces the transimpedance required at the Z1 and Z2 terminals, which makes this topology more attractive for low-voltage applications. The paper is organized as follows; in Section II, the CMOS realization of the low-voltage class AB FDCFOA is presented. In Section II, the small signal analysis of the FDCFOA is given. In Section IV, the simulation results of the FDCFOA are demonstrated. Conclusion is given in section V.

X

Y

Z

+1 O

R ZC ZVF

C F

(a)

X

Y

ZC C II+ O

R ZC Z

+

-R l

R f

IX

(b)

Figure 1. CFOA trends (a) conventional, (b) op-amp[11]

978-1-4244-1847-3/07/$25.00 ©2007 IEEE IEEE ICM - December 2007

FDCCII

X1

X2

Y1

Y2

Z1

Z2

VB

Rl

Rl

FDOp-Amp

-+

+

-

+VO

-

Rf

Rf

+Vin1

-+

Vin2-

RxIX

IX

IY

IY

Figure 2. The FDCFOA block diagram.

II. CMOS RELAZIATION OF THE FDCFOA The CMOS realization of the fully differential current

feedback operational amplifier (FDCFOA) is shown in Fig. 3. The circuit consists of two matched differential pairs (MB1B, MB2B) and (MB3B, MB4B), two pairs of matched biasing transistors (MB5B, MB6B) and (MB7B, MB8B), class AB biasing stage (MB21B to MB23B), two class AB output stages (MB9B to MB14B) and (MB15B to MB20B). The op-amp consists of two matched differential pairs (MB24B, MB25B) and (MB33B, MB34B), two matched biasing transistors (MB26B, MB35B), two matched pairs of current mirrors (MB27B, MB28B) and (MB36B, MB37B), and two class AB output stages (MB29B to MB32B) and (MB38B to MB41B).All transistors are operating in saturation region MB5B and MB6B carry equal bias currents (IBBB) while the equal bias current flowing through MB7B and MB8B are set to IBBB/2.Therefore,

ΙΜ5 = ΙΜ6 (1)

ΙΜ2 = ΙΜ4 (2)

ΙΜ5 = ΙΜ3 + ΙΜ4 (3)

ΙΜ6 = ΙΜ1+ΙΜ2 (4)

From equations (3) and (4) into equation (1) yields

ΙΜ1 + ΙΜ2 = ΙΜ3 + ΙΜ4 (5)

From equations (2) and (5)

BΙΜ1 = ΙΜ3 (6)B

The matched differential pairs are carrying equal differential and common mode current values. Therefore,

VX+ - VX- = VY+ - VY- (7)

Similarly, the differential pairs of the op-amp are carrying equal differential and common mode current values. There fore,

VO+ − VO- = VZ+ - VZ- (8)

To maintain a good current drive capability with low output impedance outputs, class AB output stages are used. Transistors (MB11B, MB12B), (MB17B, MB18B), (MB19B, MB20B), (MB31B, MB32B), and (MB40B, MB41B) form the push pull output stage transistors. The level shift circuits formed by (MB9B, MB10B), (MB15B, MB16B), (MB29B, MB30B), and (MB38B, MB39B) are used to realize controlled floating voltage sources that controls the standby current through the output stage transistors. The standby current is adjusted by the biasing circuit formed of MB21B, MB22B, and MB23B. The class AB output stage enables the circuit to derive the heavy resistive and capacitive load with low standby power dissipation and no slewing.

To prevent the drift in the output common mode (CM) voltage, a common mode feedback (CMFB) circuit is needed. It determines the output CM voltage and controls it to a specified value Vcm is set to zero volt. The CMFB circuit consists of transistors Mcm1 to Mcm10 as shown in Fig. 3 in addition to two resistors (Rcm) and two capacitors (Ccm) which are used to control the CM voltage of the outputs (VO). Transistors Mcm1 and Mcm2 are employed to isolate the CMFB circuit from the basic circuit. This is essential to make the input current of the CMFB circuit equal to zero. The CMFB circuit generates the CM voltage of the output signals at node Voav via the two equal resistors (Rcm). This voltage is then compared to Vcm using differential amplifier Mcm3 and Mcm4 with negative feedback forcing Voav to follow Vcm. The operation of the CMFB circuit could be explained as follows. Assuming the ideal case of fully differential output signals; Voav = 0. Since Voav and Vcm are equal, the tail current of the differential pair formed of transistors Mcm3 and Mcm4 will be divided between two transistors. Therefore, a current will be passed via Mcm5, Mcm6, and Mcm7 to the output nodes and the current exhibits the proper biasing even when large differential signals are present. Next consider the case when the magnitude of VO+ is greater than VO- which results in a positive CM signal Voav. This voltage will cause the current in Mcm6 and Mcm7 to increases pulling down the voltages VO+ and VO- until Voav is brought back to zero. Similarly, in case of negative CM signal, the loop will adjust the Voav to be equal to VCM.

III. SMALL-SIGNAL ANALYSIS The small signal Analysis of the circuit shown in Fig.

1(b), the following relations could be obtained:

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

+++

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛

++

−=

t

tO

ZlZ

f

t

tO

ZlZ

f

i

O

sA

RRsC

R

sA

RRsC

R

IV

ωω

ωω

.11

1

.11

1. (9)

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CC

R2

CC

X- Y-

Z-

VB3

VB2M1 M2

M6

M7

M9

M10

M11

M12

M13

M14

M24 M25

M26

M27M28

M29

CC

R1

CC

VDD

X+Y+

Z+

VB2 M3M4

M5

M8

M15

M16

M17

M18

M19

M20

M33M34

M35

M36M37

M38

M39

M41

M40

VSS

VB1

M21

M22

M23

M30

M31

M32

+VO-

Rcm Rcm

Ccm Ccm

Mcm3 Mcm4

Mcm8

+VO-

Mcm9Mcm10

Mcm1Mcm2

Mcm5Mcm6Mcm7

VOAvVcm

VB4

Figure 3. FDCFOA CMOS realziation with CMFB.

where ABOB is the gain and ωBtB represents the 3-dB bandwidth of the op-amp. Assume that RBlB <<< RBZB so the parallel configuration between RBlB and RBZB will result in RBlB. Also, assume that the pole created by CBZB and RBlB is so high that it is outside the bandwidth and ABOB is very high so the term ABOBRBlB >> RBfB and hence equation (9) could be reduced to,

ltOf

tOlf

i

O

RAsRARR

IV

ωω

+−=

.. (10)

The transimpedance gain could be obtained from (10) as follows

fi

O RI

V−= (11)

Assume that the X terminal resistance is so low that the voltage of X terminal equals that at the Y terminal. BSo, equation (10) could be written as follows:

ltOf

tOl

i

f

i

O

RAsRAR

RR

VV

ωω

+−=

.. (12)

So, the closed loop gain and the 3-dB bandwidth could be obtained as follows:

iRfR

OA −= ,

fRlRtOA

dBω

ω =−3 (13)

Where ABO BωBtB is the op-amp gain-bandwidth product. Equation (13) shows that the ωB3-dBB could be controlled by load resistance RBlB with fixed feedback resistance RBfB. Also, RBl Bused to convert the Z terminal output current to voltage being amplified by the fully differential op-amp, this move the high voltage swing from the Z terminal to the fully differential op-amp while it is operating in the open-loop configuration. Clearly for a particular RBlB, once RBfB is set to RBiB can be changed to vary the gain without affecting the bandwidth. Hence, the amplifier achieves a gain-independent bandwidth. In order to avoid the high frequency poles of the op-amp and thereby ensure closed loop stability, the closed loop bandwidth of the CFOA must be less than the GBP of the op-amp. Hence from (13) it follows that RBlB must always be less than RBfB.

IV. SIMULATION RESULTS The performance of the FDCFOA circuit was verified by

performing PSpice simulations with supply voltages ±0.75V, the following biasing voltages VB1 = 0.7V, VB2 = 0.35V, VB3=0.71V, and using 0.25µm CMOS technology parameters.

Fig.4 (a, b, c) show the output differential voltage of VGA with different gains for an applied AC input voltage with value 1V. The input resistance Ri, which controls the gains, takes values 2, 1, 0.5, and 0.25KΩ respectively, feedback resistance

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Rf = 2KΩ while the bandwidth control resistance Rl takes the following values (a) Rl=0.2 KΩ, (b) Rl=0.5 KΩ, (c) Rl=1.5 KΩ. The bandwidths for different Rl values are (a) 57 MHz, (b) 320 MHz, (c) 530 MHz respectively.

Frequency

1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1GHz

vdb(8,9) vdb(14,15) vdb(20,21) vdb(26,27)

-40

-30

-20

-10

0

10

20

Gain=1

2

48

The

outp

ut d

iffer

entia

l vol

tage

Vou

t [dB

V]

(a)

+

-+

-

+

-

Vin

FDCFOA+

VO-

Rf = 2Kohm

Rf= 2Kohm

Ri=0.25to2Kohm

Ri=0.25to2Kohm

Rl= 0.2KohmRl= 0.2Kohm

Gain=1

2

4

8

The

outp

ut d

iffer

entia

l vol

tage

Vou

t [dB

V]

Frequency

1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz

vdb(8,9) vdb(14,15) vdb(20,21) vdb(26,27)

-40

-30

-20

-10

0

10

20

(b)

+

-+

-

+

-

Vin

FDCFOA+

VO-

Rf = 2Kohm

Rf= 2Kohm

Ri=0.25to2Kohm

Ri=0.25to2Kohm

Rl= 0.5Kohm Rl= 0.5Kohm

Gain=1

2

4

8

The

outp

ut d

iffer

entia

l vol

tage

Vou

t [dB

V]

Frequency

1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHzvdb(8,9) vdb(14,15) vdb(20,21) vdb(26,27)

-30

-20

-10

0

10

20

(c)

+

-+

-

+

-

Vin

FDCFOA+

VO-

Rf = 2Kohm

Rf= 2Kohm

Ri=0.25to2Kohm

Ri=0.25to2Kohm

Rl= 1.5Kohm Rl=1.5Kohm

Figure 4. (a) Fully differential voltage amplifier, Frequency response of the fully differential voltage amplifier with different gains with (b)Rl=0.2kohm,

(c) Rl=0.5kohm, (d) Rl = 1.5Kohm

It is clear that the VGA based on the FDCFOA experiences no loss in bandwidth when the gain is increased. From the simulations, Rl has been used to control the bandwidth of the FDCFOA block for a wide range (57 MHz - 530 MHz) without affecting its performance. The input and output referred noise voltages spectral densities (40 nV/ Hz ). For Vin step voltage with magnitude 500mV and frequency 1MHz applied to the FDCFOA block, the slew rate is 10 MV/sec.

V. CONCLUSION A low-voltage fully differential current feedback

operational amplifier circuit has been presented. The FDCFOA has the advantages of wide range of controllable 3-dB bandwidth (∼57MHz - 530MHz) and no need for large transimpedance in its current conveyor. Also, it combines between the advantages of the CFOA over the op-amp and the fully differential over single ended. Simulation results have been given.

REFERENCES [1] E. Bruun, “Feedback analysis of transimpedance operational amplifier

circuits,” IEEE Trans. Circuits Syst.-I, Fundam. Theory Appl., vol. 40, pp. 275-278, 1993.

[2] A. H. Madian, S. A. Mahmoud, and A. M. Soliman, “New 1.5-V CMOS Current Feedback Operational Amplifier,” 13th IEEE ICECS, pp. 600- 603, December 10-13, 2006, Nice, France.

[3] E. Bruun, “A dual current feedback op-amp in CMOS technology,” Anal. Integr. Circuits Signal Process., 1994; 5:213-217.

[4] R. Mita, G. Palumbo, and S. Pennisi, “Low-voltage high-drive CMOS current feedback op-amp,” IEEE Trans. Circuits Syst.-II, vol. 52, pp. 317-321, 2005.

[5] A. M. Ismail and A. M. Soliman, “Novel CMOS current feedback op-amp realization suitable for high frequency applications,” IEEE Trans. Circuits Syst.-I, Fundam. Theory Appl., vol. 47, pp. 918-921, 2000.

[6] S. A. Mahmoud and A. M. Soliman, “Low voltage rail to rail CMOS current feedback operational amplifier and its applications for analog VLSI,” Anal. Integr. Circuits Signal Process., vol. 25, pp.47-57, 2000.

[7] A. M. Soliman, “Applications of the current feedback operational amplifiers,” Anal. Integr. Circuits Signal Process., vol.11, pp. 256-302, 1996.

[8] S. A. Mahmoud and A. M. Soliman, “New MOS-C biquad filter using the current feedback operational amplifier ,” IEEE Trans. Circuits Syst.-I, Fundam. Theory Appl., vol. 46, pp.1510-1512, 1999.

[9] S. A. Mahmoud and I. A. Awad, “Fully differential CMOS current feedback operational amplifier,” Anal. Integr. Circuits Signal Process., vol. 43, pp. 61-69, 2005.

[10] H. Alzaher, H. O. Elwan, and M. Ismail, "A CMOS fully balalnced second-generation current conveyor," IEEE Trans. Circuits Syst.-II, vol. 50, pp. 278-287, 2003.

[11] B. J. Mundy, A. R. Sarkar, and S. J. Gift, “A new design topology for low-voltage CMOS current feedback amplifiers,” IEEE Trans. Circuits Syst.-II, vol. 53, pp. 34-38, 2006.

[12] A. Tammam, K. Hayatleh, and F. Lidgey, "Novel high performance current feedback op-amp," Proc. IEEE Int. Symp. Circuits and Systems, pp. 705 –708, 2002.

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