Characterization Program for Fast Early Yield Ramp of Memory Technology

Michael Hall2, Martin Hunt2, Rico Prescher1, Gabriel Sellier1, Holger Herzog1, Barry Mitchell3, Sudtida Lavangkul3,

Pratik Satasia2, Hery Susanto2

Qimonda Dresden1 Synopsys, Austin, TX2, Dallas, TX3, USA

Abstract- We report on a program to improve early yield ramp for a leading edge memory technology development. Two semi-custom, approximately 4Mb addressable arrays are used to characterize the random and systematic defectivity of FEOL and BEOL processes. Several examples of fault determination and correction are presented that highlight the efficiency of the combined characterization vehicle and analysis software.

I. INTRODUCTION

As time to market windows demand shorter and shorter product development cycles, early learning of yield detractors and process window latitude for design rules is critical in a technology development yield ramp. While it is tempting to simply use a memory product itself for yield ramp, a truly aggressive development cycle cannot afford to wait for sufficient product functional yield to begin defectivity characterization. Additionally, at advanced technology nodes, yield loss due to systematic issues such as lithography weakness in the periphery area, or pattern density changes from periphery to core memory array have become increasingly prevalent. We created two 3.5Mb addressable arrays with a combination of standard and memory specific test structures to enable characterization of FEOL and BEOL random and systematic issues for a stand-alone memory product. A highly aggressive experiment definition to GDSII tapeout timeframe was achieved to fit within the existing development schedule. Due to the robust nature of our design, data was available on first silicon to evaluate early process limiting failures. A combination of electrical test data and other available manufacturing data, e.g. WIP, metrology, and in-line defectivity, is available within the design aware analysis software to identify yield issues, speed up the root cause failure analysis, and predict D0 levels.

Several case studies of specific process related issues are presented that show how the addressable arrays are used for identification of the problem, root cause determination, and corrective action results.

II. CHARACTERIZATION VEHICLE

We deployed two addressable 3.5Mb TDROMTM (Technology Development ROM) arrays to complement traditional short flow yield test structures. The use of multiplexed technology characterization circuits is not a new development, they have been utilized as early as 1986 [1] and

regularly since then [2]-[5]. The main advantage of this method is providing high experiment area efficiency coupled with defect localization within 2um. In addition, the addressable test circuit provides a high wafer test throughput on a standard memory tester. Each circuit has a native test speed of up to 100 KHz due to the fact it is a true analog comparator measurement. Each array is able to be tested in less than 3 seconds per die, however the tester data write speeds limits the overall time to about 25 minutes per TDROM. With some of the latest tester designs, test times of about six minutes per wafer have been demonstrated with all wafer die coverage (no sampling).

Each of the 56 sub-arrays in the circuit is 64K, with the possibility of containing over 4000 unique experiments. The bit cells are in effect a 2-terminal continuity test structure which is referred to as a Device under Test (DUT). The schematic of a single TDROM column and complimenting reference column are shown below in Fig. 1. To perform a measurement, an off-chip comparator compares a DUT with a known reference, determining whether it is more or less resistive than the reference. This would detect whether an open test structure is shorted, or vice-versa. Also, due to the multiple reference resistances available, there is not only the capability to detect hard open/short fails but also soft or resistive via failures. Process defects in effect actually "program" the ROM.

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In order to ensure a robust design with very high circuit yields, the logic for accessing each bit is designed using relaxed design rules that utilize the available silicon area to create fault-tolerant devices, routing, and interconnect. This methodology ensures that the test structure array core will be most sensitive to process defects. For debug aid, analog access to each bit line allows coarse resistance measurements. In addition, each TDROM has row labeling on silicon for ease of failure analysis debug localization.

Out of the seven million total bits of experiments, approximately 90% of the DUTs contain random defect monitor structures. This allows sufficient critical area for sensitivity at target D0s. The critical area of every random defect monitor structures was extracted and used to calculate normalized defect densities. The structures included combs, serpentines, and single- and stacked-via chains designed to target both the memory core and periphery design rules. In addition to providing D0 tracking across multiple layers and failure modes, the small, simple bitcell area allows fast killer defect localization for PFA. This method proved to be a reliable tracker of defect levels. Table 1 shows the correlation between corresponding large area short flow test structures yield and the D0 of smaller array-based DUTs. The coefficients are negative because the correlation is between a defect count and yield. This baseline monitor of the defect level will quickly highlight process excursions which may be missed by traditional large area structures. In Fig. 2, a via chain experiment’s parts per billion via failure level spiked, which corresponded to an arcing event observed inline.

The remaining 10% of the experiments are a set of process window monitors which vary critical dimensions to detect systematic yield loss mechanisms. Most DUTs were Manhattan design rule style, but several DUTs were custom designed to product-specific topologies that were highlighted as processing challenges. The intent is to push the design rule under test step-by-step outside of minimum or maximum to indicate the manufacturing process margin. Considerable effort was taken during experiment definition to minimize the risk of poor product yield due to particles from resist or pattern collapse.

Fig. 2: Trend of via failures corresponding to arcing

TABLE 1: Correlation coefficients between conventional large area Short Loop (SL) comb test structure yield and TDROM addressable array (AA) comb test structure D0.

Test Met2 Met1 Met1 Met0 Met0 Core Structure AA AA AA AA AA

Met2 SL -0.846

Met1 SL -0.741 -0.943

Met1 SL2 -0.791 -0.911

Met1-M0 SL -0.616 -0.965 -0.94 -0.845

Met0 SL -0.82 -0.799

Met0 SL2 -0.806 -0.71

III. DATA ANALYSIS SOFTWARE ENVIRONMENT

To handle the large volume of test data, we utilized a custom yield management analysis software package TestChip Advantage™ (TCA). The software package is built on a relational database that is pre-loaded with the DUT design of experiment (DOE) information so that various types of manufacturing data can be combined in real time to form a holistic approach to root cause analysis. Fig. 3 highlights the data flow of experiment and test data for analysis. The software provides a framework for cross-sectioning the data generated from the test vehicle at increasing levels of detail based on spatial and temporal signatures observed at higher levels. This context-based drill down capability in combination with statistical analysis minimized learning times and led to several significant discoveries of process issues. Multiple Figure of Merits (FOM) were automatically extracted from the results for tracking specific layer process variations. This data set allows monitoring of any tool, wafer, lot, or die for variation. Proposed process changes could be evaluated by comparing FOM results with lot split data. A set of automated analysis templates were run regularly on new data sets to quickly identify process excursions for immediate actions. These templates generated a standard HTML report for internal posting enabling easier information sharing among the module owners and process development groups (Fig. 4). The report contains high level BIN test results, bit result data validation, high level paretos of worst performing experiments, and drill down details of all structures. Once a problem was identified, the characteristic failure locations were automatically output in logical and physical coordinates in KLARF format for efficient PFA.

Fig. 3: TCA experiment and test data flow

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Fig. 4. TCA generated HTML reports

Several levels of data validation were employed to ensure that the actionable data was reliable. As the characterization vehicle was being sorted, DC measurements as well as bit level tests were recorded and compared to acceptable ranges. Die that failed this first level validation were eliminated from the analysis data set as shown in Fig. 5 which plots the percentage of die passing BIN tests for each wafer in a lot. For this case, wafer 7 had a shorted power supply due to high defect counts, while wafer 2 exhibited an abnormally high Idd current around the wafer edge. In addition to the coarse first level validation, each block of the array included a check row that had a unique combination of known open, shorted, and known resistance structures that could be queried to validate all the active addressing and fundamental components of the addressable array. Finally, a bit pattern matching algorithm was applied to eliminate failed bits that should not be included in the calculations. The eliminated patterns, such as full row, column, or block failures would indicate a fault which does not allow for proper reading of a specific set of addresses thus skewing the final results. This data is not actually eliminated from the database; it is still available for use in analysis. The user can view eliminated bit statistics separately to determine if there is any pattern in the failure mechanisms.

Fig. 5. Die yield based on BIN data results, with failed die correlating to

inline defect data

IV. YIELD RAMP EXAMPLES

The initial yield ramp phase provided a number of instances where test data analysis led to actionable results and process improvements. Listed below are three representative examples that highlight different functional areas. A. Metal Comb Tool Correlation

In the first example, a distinct high-low pattern was observed in a top metal shorting comb D0 wafer trend (Fig. 6). A PFA of the failing bits showed hillock formations mainly localized around last via (Fig. 7). Based on this information, it was hypothesized that the extruded Al was caused by exceeding the thermal budget of some process(es) between Al deposition and Al etch [6]. Correlating the wafer level data to relevant equipment information identified a set of hard mask deposition chambers which resulted in the higher failures for specific lots. However, further investigation demonstrated that this set of chambers was not the only source of the defects. The high-low pattern was observed across all Carbon Hardmask deposition tools/chambers. Additionally, the first wafer effect was observed on multiple lots (Fig. 8). The key parameters of the deposition recipe were obtained and strong correlation between D0 and length of preheat step before hardmask deposition was discovered (Fig. 9). Subsequent experiments with preheat time and temperature confirmed the hypothesis, and provided the process engineers with actionable information leading to the tool supplier changing the scheduling for the preheat cycle and thus a more robust process.

Fig. 6. D0 trend of top metal shorting

Fig. 7. Observed top metal hillock formation near last via on high D0

wafers

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Fig. 8. First wafer effect

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Fig. 9: ML comb D0 vs. Length of Preheat

B. CMP Clean Split Lot In another example, a post oxide CMP clean split

experiment was applied to a lot evaluating the effect on contact patterning. After being loaded into the TCA database, the split data was evaluated along with the appropriate systematic contact experiment process window results. The process window (PW) value for each contact experiment is a FOM automatically computed from a fail rate chart. The fail rate charts plot contact width (or any other design rules under investigation) as the independent variable and the resulting percentage of DUT failures as the dependant variable. In a single sided fail rate chart, the process window is the difference between the target design rule and the intercept with a 5% failure percentage threshold. Fig. 10 shows a fail rate chart with a 25% delta between the average fail rate percentage at the 65nm contact for the POR wafers and the wafers with the additional clean step. This corresponded to a median process window increase of 4.5 nm. The box plot results in Fig. 11 also demonstrate the positive influence the new clean process had on the contact process window.

Fig. 10. Fail rate vs. design rule of a contact chain by lot split

Fig. 11. Box plot of contact process window vs. post CMP clean split

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C. Via Lithography Offset Correction In a final example, Via1 to Metal1 lithography alignment

experiments were performed on the process. We evaluated the corresponding TDROM via misalignment (MA) comb structures to observe the effect on via process window and asymmetry on lots before and after the offset correction. Asymmetry is a FOM extracted from a two-sided misalignment fail rate chart, measuring the off-centeredness of the curve from the nominal design rule or center zero misalignment line. In addition, for a two-sided misalignment fail rate chart, the process window is the difference between the two intercepts with the 5% failure threshold. Fig. 12 shows a fail rate chart process window comparison from a sampling of pre and post offset lots. One can see the larger process window after the offset and a pronounced asymmetry for both variations. This asymmetry was also observed in composite maps of 25 wafers from pre and post offset lots as shown in Fig. 13. The total sample consisted of 15 lots (331 wafers) without the correction and 5 lots (107 wafers) with the lithography correction. Although an across wafer asymmetry and process window variation was still observed post offset, on average the PW increased by 7nm for both vertical and horizontal misalignment experiments (Table 2). The PW variation can be observed by die Y coordinate in Fig. 14. The lithography correction reduced the vertical asymmetry by 1 nm, however the horizontal asymmetry increased by 3nm (Table 3).

Fig. 12. Vertical MA process window comparison in a fail rate chart

TABLE 2: Process window values (nm) of pre and post lithography correction lots

Misalignment Type Offset Mean Median Std Dev

Horizontal MA Pre 121.372 120.352 13.372

Horizontal MA Post 128.283 127.592 8.828

Vertical MA Pre 144.640 142.387 12.049

Vertical MA Post 151.430 150.511 8.011

Fig. 13. Die variation of Via1 to Metal 1 asymmetry

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Fig. 14. Wafer variation of vertical misalignment experiment by die Y

TABLE 3: Asymmetry values (nm) of pre and post lithography correction lots

Misalignment Type Offset Mean Median Std Dev

Horizontal MA Pre -10.388 -10.391 4.403

Horizontal MA Post -13.382 -12.982 3.523

Vertical MA Pre 1.452 1.324 2.286

Vertical MA Post 0.553 0.538 2.679

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V. CONCLUSIONS

We have presented several case studies demonstrating the use of yield learning test structure arrays linked with analysis software which were applied to a memory product yield ramp at an early technology phase. Targeting the periphery and core areas separately is especially crucial during this phase to ensure final product yield for continued development. The close coupling of the test structure DOE, the analysis software, and additional process information has shown to be a useful tool in finding early yield issues. Automatically calculated Figure of Merits introduces a data reduction methodology which allows for faster time to meaningful results. The FOM values at a die, wafer, or lot level provide insight into various process variations and excursions, such as experiment split evaluation or outlier wafer investigation. By combining the electrical test data FOM and other available manufacturing data the process owners are empowered to make faster decisions addressing current and future technology challenges, leading to an improved process yield in less time.

REFERENCES

[1] A. Nishimura et al., "Multiplexed test structure: A novel VLSI technology development tool", IEEE VLSI Workshop on Test Structures, Paper 30, 17-18th Feb 1986.

[2] M. Karthikeyan, S. Fox, A. Gasasira, G. Yeric, M. Hall, J. Garcia, B. Mitchell, E. Wolf, "Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Manufacturing," Proc. 2007 Int'l Conf Microelectronic Test Structures (ICMTS 2007), IEEE Press, pp. 135-139.

[3] G. Yeric, E. Cohen, J. Garcia, K. Davis, E. Salem, G. Green, “Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below”, IEEE Design and Test of Computers, May-June 2005, Vol.22, Issue 3, pp. 232-239.

[4] R.E. Newhart and E.J. Sprogis, “Defect diagnostic matrix: A defect learning vehicle for submicron technologies,” Proc. 1988 Int’l Conf. Microelectronic Test Structures (ICMTS 88), IEEE Press, pp. 103-106.

[5] M. Yamamoto, H. Endo, and H. Masuda, "Development of a large-scale TEG for evaluation and analysis of yield and variation," IEEE Trans. Semiconductor Manufacturing, vol. 17, no. 2, May 2004, pp. 111-122.

[6]. A. Oliva, A. El-sayed, A. Griffin and C. Montgomery, “Reflow of AlCu into Vias during CVD TiN Barrier Deposition”, the Ninth International Symposium on Semiconductor Manufacturing, pp. 419-422

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