Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

Sung-Taeg Kang, Jane Yater, CheongMin Hong, James Shen, Nicole Ellis, Matthew Herrick, Horacio Gasquet, Wendy Malloch, Gowrishankar Chindalore

Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, Texas, sung-taeg.kang@freescale.com Introduction Split gate flash memory architecture has gained a strong foot-hold in the embedded nonvolatile memory due to its over-erase immunity, enhanced array efficiency, and low power operation [1]. Furthermore, the silicon nanocrystal based split gate memory has been considered as one of the most promis-ing technologies due to its ability to scale beyond 90nm [2, 3]. However, in order for the silicon nanocrystal memory to re-place the conventional floating gate technology, it needs to demonstrate sufficient operating window throughout its life-time and also meet reliability requirements such as endurance and long term data retention [4]. We have systematically evaluated the effect of nanocrystal size on long-term reliabil-ity. In this paper, we present the performance characteristics of such a silicon nanocrystal split gate bitcell and report an optimal bitcell process and integration scheme for memory arrays. Results and Discussion Basic Bitcell Characteristics: The Si nanocrystal based split gate thin-film storage bitcell (SG-TFS) was fabricated with the 90nm CMOS technology (TEM cross-sections shown in Fig 1). The SG-TFS uses highly efficient source-side injection (SSI) programming and “dielectric-friendly” Fowler-Nordheim erase. Figure 2(a) shows typical program and erase behavior in achieving a 3V operating window. The program speed is under 5us with 9V control gate and 5V source bias; and the erase speed is less than 10ms with control gate bias of +14V. Control gate natural threshold voltage (VTH,CG_nat) is lowered to below 0V with channel counter-doping to reduce the read disturbance as has been reported previously [5]. However, as shown Figure 2(b), the drive current decreases with increasing counter-doping implant dose due to mobility degradation. Hence, the optimization of VTH,CG_nat is necessary to balance the conflicting requirements of read disturb and read current. Bitcell Optimization: Figure 3 shows the trap-up (Vt shift after 10k P/E cycles) as a function of nanocrystal size. There appears to be an optimal size range; above which the trap-up increases with the size of the nanocrystals. This is believed to be due to the inefficient erase caused by the lowering of the electric field between the control gate and the nanocrystals. Figure 4 shows the erase efficiency as a function of nanocrys-tal size and erase voltage polarity. It is clearly shown that, as the nanocrystal size increases, the discharge efficiency through the top oxide slows down. At the same time, the erase efficiency through the bottom oxide increases gradually. Be-low the optimal size range, however, the trap-up increases due to the reduced charge capturing cross-section of the nanocrys-

tals. This is also consistent with the effect of the nanocrystal area coverage on the trap-up as shown in Figure 5. For a given nanocrystal size, decreasing the nanocrystal area cover-age from 14.2% to 11.5% increased the trap-up by more than 140mV. Figure 6 shows a 10X improvement in endurance with the nanocrystal stack optimization compared to our pre-viously reported work [6]. Figure 7 shows the high tempera-ture (150oC) retention characteristics of fresh and 10k cycled bitcells. In both cases, the smallest Vt loss was for the same nanocrystal split “B”. This is in line with the expectation that the data retention is affected by the combined effects of cou-lomb blockade and charge confinement in nanocrytals besides dielectric thickness and its quality. We have since retargeted the nominal size. Array Fabrication and Evaluation: A low cost integration and process simplification is achieved by merging bitcell proc-ess with the baseline CMOS process for steps such as gate oxidation and well implants. The fabrication process flow of the proposed Si split gate flash embedded array is outlined in Figure 8. The bitcell is formed after the formation of HV, I/O, and core transistors in order to minimize the number of oxida-tion steps that the nanocrystals see during the processing. Figure 8 shows the program and erase distributions on a 1Mb sector from the memory array test vehicle built on the 90nm platform. The median Vt window is about 4V resulting in a product operating window of about 2V. Conclusion Optimization of bitcell such as Vt adjustment, nanocrystal size, and density control is critical to achieve high perform-ance and excellent reliability. Unlike continuous charge stor-age memory, the discontinuous nanocrystals caused more of oxide area to be exposed to charge transport during cycling leading to a higher level of trap-up. However, we have shown that the trap-up could be minimized by optimizing the nanocrystal size for maximum charge capture. The nanocrys-tal size optimization also results in improved data retention. The result successfully proves that nanocrystal split gate flash technology is indeed very promising to replace floating gate nonvolatile memories for 90nm and beyond. References [1] S. Saha, IEEE Trans. Electron Device, vol.54, pp. 3049-3055, 2007 [2] C.M. Hong, NVSMW, pp. 75-76, 2007. [3] T. Osabe et al, VLSI Symposium Tech. Dig., pp. 242-243, 2004. [4] S-H. Lim et al, VLSI Symposium Tech. Dig., pp.190-191, 2005 [5] C. Swift et al, NVSMW, pp. 56-57, 2006. [6] J. Yater et al., NVSMW, pp. 77-78, 2007.

59978-1-4244-1547-2/08/$25.00 (c)2008 IEEE

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Figure 2 (A) Typical program and erase behavior and (B) Cell Current versus natural control gate Vt. Excessive Sb counterdoping degrades cell current significantly.

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Figure 1 TEM image of split gate bitcell embedded with Si nanocrystals

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Figure 7 Typical retention characteristics at 150oC for both fresh and 10k cycled bitcells show sweet spot in terms of nanocrytals size.

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Figure 6 Endurance characteristics with various nanocrytals sizes with 2V controlled window.

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Figure 9 Threshold voltage distributions for both the erased and pro-grammed state of a 1Mb Si nanocrystal split gate memory array sector with dumb program and erase.

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Figure 8 Key Technology Process Modules in designing 1Mb nanocrystal split gate flash embedded array.

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