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Special Session 8: New Topics At-Speed Testing in the Face of Process Variations Organizer: Bernard Courtois CMP Presenter: Chandu Visweswariah IBM Thomas J. Watson Research Center Process variations complicate at-speed testing enormously. Different paths have different sensitivity signatures, and therefore each chip can potentially have a different critical path depending on the manufacturing parameters of that chip. This presentation will discuss how process variations can systematically be covered by exploiting statistical timing to select paths for at-speed structural test. Simultaneous coverage of process variations and satisfaction of sensitization conditions will be discussed. Due to increasing process variability in modern technologies, selection of optimal test margins is important to reduce pessimism while ensuring quality of shipped chips. Use of binning techniques to increase yield in the face of wide process variations is becoming more prevalent. Timing closure, margining and testing for binned chips can also take advantage of statistical timing to improve yield and quality. Contributors: Chandu Visweswariah, Vladimir Zolotov, Jinjun Xiong IBM Thomas J. Watson Research Center Yorktown Heights, NY, USA Email: {chandu,zolotov,jinjun}@us.ibm.com 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00 © 2009 IEEE DOI 10.1109/VTS.2009.72 244 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00 © 2009 IEEE DOI 10.1109/VTS.2009.72 244 2009 27th IEEE VLSI Test Symposium Unrecognized Copyright Information DOI 10.1109/VTS.2009.72 244 2009 27th IEEE VLSI Test Symposium Unrecognized Copyright Information DOI 10.1109/VTS.2009.72 244 2009 27th IEEE VLSI Test Symposium Unrecognized Copyright Information DOI 10.1109/VTS.2009.72 244 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00 © 2009 IEEE DOI 10.1109/VTS.2009.72 237 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00 © 2009 IEEE DOI 10.1109/VTS.2009.72 237 2009 27th IEEE VLSI Test Symposium 1093-0167/09 $25.00 © 2009 IEEE DOI 10.1109/VTS.2009.72 237

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Page 1: [IEEE 2009 27th IEEE VLSI Test Symposium (VTS) - Santa Cruz, CA, USA (2009.05.3-2009.05.7)] 2009 27th IEEE VLSI Test Symposium - Special Session 8: New Topics: At-Speed Testing in

Special Session 8: New Topics At-Speed Testing in the Face of Process Variations

Organizer: Bernard Courtois

CMP

Presenter: Chandu Visweswariah IBM Thomas J. Watson Research Center

Process variations complicate at-speed testing enormously. Different paths have different sensitivity signatures, and therefore each chip can potentially have a different critical path depending on the manufacturing parameters of that chip. This presentation will discuss how process variations can systematically be covered by exploiting statistical timing to select paths for at-speed structural test. Simultaneous coverage of process variations and satisfaction of sensitization conditions will be discussed. Due to increasing process variability in modern technologies, selection of optimal test margins is important to reduce pessimism while ensuring quality of shipped chips. Use of binning techniques to increase yield in the face of wide process variations is becoming more prevalent. Timing closure, margining and testing for binned chips can also take advantage of statistical timing to improve yield and quality. Contributors: Chandu Visweswariah, Vladimir Zolotov, Jinjun Xiong IBM Thomas J. Watson Research Center Yorktown Heights, NY, USA Email: {chandu,zolotov,jinjun}@us.ibm.com

2009 27th IEEE VLSI Test Symposium

1093-0167/09 $25.00 © 2009 IEEEDOI 10.1109/VTS.2009.72

244

2009 27th IEEE VLSI Test Symposium

1093-0167/09 $25.00 © 2009 IEEEDOI 10.1109/VTS.2009.72

244

2009 27th IEEE VLSI Test Symposium

Unrecognized Copyright InformationDOI 10.1109/VTS.2009.72

244

2009 27th IEEE VLSI Test Symposium

Unrecognized Copyright InformationDOI 10.1109/VTS.2009.72

244

2009 27th IEEE VLSI Test Symposium

Unrecognized Copyright InformationDOI 10.1109/VTS.2009.72

244

2009 27th IEEE VLSI Test Symposium

1093-0167/09 $25.00 © 2009 IEEEDOI 10.1109/VTS.2009.72

237

2009 27th IEEE VLSI Test Symposium

1093-0167/09 $25.00 © 2009 IEEEDOI 10.1109/VTS.2009.72

237

2009 27th IEEE VLSI Test Symposium

1093-0167/09 $25.00 © 2009 IEEEDOI 10.1109/VTS.2009.72

237

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