VLSI Implemen

Prashant Gurjar, Rashmi SolaPooja Kansliwal UG Scholar, Dept. EC, GGITM, Email: prashantgurjar84@gmail. ABSTRACT This paper is primarily deals the constructioadder circuit using Hardware Description Lin the platform Xilinx ISE 9.2i and implField Programmable Gate Arrays (FPGAsdesign parameters. The motivation behind tis that an adder is a very basic building blocLogic Unit (ALU) and would be a limperformance of Central Processing Unit (CP In the past, thorough examialgorithms with the respect to particular only been partially done. The merit of the is to be evaluated by its ability to efficientlcomputational algorithms. In the othtechnology is developed with the aim to ethe computation. The reverse path; evaluatthe algorithms should also be taken. Timportant to develop computational structuinto the execution model of the processor anfor the current technology. In such a case,the algorithms is performed globally acrossof its implementation. In this research article, we havesynthesized the various adders like full addadder, carry-look ahead adder, carry-skipselect adder and carry-save adder by usXilinx ISE 9.2i. The simulated results are functionality of high speed adders and thearea and speed is analyzed. Finally this pthat the carry-save adder is the more efficiearea consumption.

KEYWORDS: High Speed Adder, FieldGate Array, Carry Skip Adder, Carry SeleSave Adder.

1. INTRODUCTION Digital computer ALU is an aspect of logicobjective of developing appropriate algoritachieve an efficient utilization of the avaiThe hardware can only perform a relativprimitive set of Boolean operations anoperations are based on a hierarchy of opebuilt by using algorithms against the hultimately, speed, power and utilization omost often used measures of the efficiency o

1.1 WHAT IS AN ADDER In digital electronics, adder is a diperforms addition of two numbers. In many

tation of Adders for High Speed

nki Mahendra Vucha

Bhopal, India Asst. Prof, Dept. EC, GGIT.com Email: Mahendra.1548@gm

on of high speed Language (HDL) lement them on ) to analyze the

this investigation ck of Arithmetic

miting factor in PU). ination of the technology has new technology y implement the er words, the efficiently serve ting the merit of Therefore, it is ures that fit well nd are optimized optimization of

s the critical path

e simulated and der, ripple carry

p adder, carry –ing VHDL and verified and the parameters like paper concludes ent in speed and

d Programmable ect Adder, Carry

c design with the thms in order to ilable hardware. vely simple and ndthe arithmetic erations that are

hardware. Since, of ALU are the of an algorithm.

igital circuit that y computers and

other kinds of processors, adders the ALU(s), but also in other parts othey are used to calculate addressmany more. 1.2 CONCEPT OF ADDERS Consider two binary variables x anddenoted by x+y, such that 0+0 = 0 0+1 = 1 1+0 = 1 1+Here, the result in the last case is a b10). The sum of two numbers can be digits in binary set. This, of courseconcept of a carry out. In the binary is viewed as a 0 with a 1 shifted to thout is 1”.

1.3 HALF ADDER A half adder is a logic circuit thaddition. It requires two inputs, and th

Figure 1. Half adder the inputs. The logic diagram of HA i

A HA adds two one-bit binarhas two outputs, S and C (the value on to the next addition).The simplshown in figure 1, incorporates aan AND gate for C. The Boolean eqof half adder is shown bellow.

S = A XOR B …… C = A AND B ……

Table 1. Truth table fo

Input

A B C

0 0 0

0 1 0

1 0 0

1 1 1

d ALU

M, Bhopal, India mail.com

are used not only in of the processor, where es, table indices, and

d y. the binary sum is

+1 = 10 binary 10(i.e., 2 inbase out of the range of the

e, is the origin of the sum 1+1, the result 10

he left to give a “carry-

hat performs one-digit he output is the sum of

r

is shown in figure 1.

ry numbers A and B. It C theoretically carried lest half-adder design, an XOR gate for S and quation and Truth table

…(i) …(ii)

or half adder

Output

S

0

1

1

0

1.4 FULL ADDER A Full Adder (FA) is a logical circuit thaddition operation on three binary digits.produces a sum and a carry value, which digits. The logical diagram of full adder is 2.

Figure 2. Full adder

A FA adds binary numbers and accounts foin as well as out. A one-bit full adder adnumbers, often written as A, B, and Ci heoperands, and Ci is a bit carried in (in theaddition). The circuit produces a two-btypically represented by the signals Co (Carthe Boolean equation and truth table is show S = A XOR B XOR Ci Co = (A AND B) OR (B AND Ci) O……(iv)

Table 2. Truth table for full ad

A B Cin Cout

0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1

A FA can be constructed by cascading A and B are connected to the input of first Hof first HA is connected as one input alsecond HA and it give SUM output. The loand second HAs carry outputs a gives CAFA. 2. COMPLEX ADDERS: The reference to eve of adding extend it to adding binary words. In generabit words yields an n-bit sum and a carrycarry is carried from lower bit adder to hBased on carry transfer from LSB to MSBclassified. 2.1 RIPPLE CARRY ADDER: A ripple carry adder for N-bimplemented by concatenating N full addeFigure 3. At the i-th bit position, the i-th bitand B and a carry signal from the preceding

hat performs an The full adder are both binary shown in figure

or values carried dds three one-bit ere A, B are the

eory from a past bit output sum rry) and S(Sum). wn bellow.

……(iii)

OR (CiAND A)

dder

Sum 0 1 1 0 1 0 0 1

of two HA.The HA and the sum long with Ci to gical OR of first

ARRY output of

single bits, let’s al, adding two n-y-out bit Cn.The higher bit adder. B, the adders are

bit numbers is ers as shown on ts of operands A g adder stage are

used to generate the i-th bit of the ci+1, to the next adder stage. This isAdder (RCA), since the carry signal significant bit position to the most sof a ripple carry adder is simple, whtime. However, the ripple carry addsince each full adder must wait for coming from the previous full adder.figure. 3.

Figure 3. Ripple carry

2.2 CARRY - LOOK AHEAD AA significant speed improvement in a parallel adder was introduced by Adder (CLA). The CLA adder is thfastest schemes used for the additionthe delay to add two numbers depenthe size of the operands. Carry lookconcepts of generating (G) and propwork is based on two signals calledposition. The P and G are shown bell Ci+1 = Gi + Pi.Ci Here, Gi = Ai.Bi

Si = Ai ⊕ Bi ⊕ Ci = Pi⊕ CThe Si and Ci+1 represent the sum adder respectively.The carry-lookabroken up in two modules: (1) The Pawhich generates Si, Pi and Gi. (2) TLogic, which generates the carry-outCLA for 4-bit adderis shown in

Figure 4: Carry Lookah

sum, si, and a carry, s called a Ripple Carry “ripple” from the least significant. The layout hich allows fast design der is relatively slow, the carry bit which is

. The RCA is shown in

y adder

ADDER the implementation of a Carry-Look ahead-

heoretically one of the n of two numbers, since nds on the logarithm of k ahead logic uses the

pagating (P) carries. Its d P and G for each bit ow. and Pi = (Ai⊕ Bi)

Ci. and carry from ith full ahead adder can be artial Full Adder, PFA, The Carry Look-ahead t bits. The structure of figure 4.

head adder

3. IMPLEMENTATION OF HSA: The alternate approaches for Speed Adders (HSA) have been designed [1], [2], [3], [4]. All of them have thdecreasing the computation time and diffThis paper examines few of them bellow.

3.1 CARRY – SKIP ADDER Since the Cin-to-Cout represents the longripple-carry-adder an obvious attempt is to propagation through the adder. This is ausing Carry-Propagate pi signals within a all the pi signals within the group are pi = exist for the carry to bypass the entire group P(i,i+3) = Pi+3. Pi+2.Pi+1.Pi Using the individual propagate values, the AND gate is ORed with Ci+4 to produce a st

Carry = Ci+4 + P(i,i+3). Ci

Figure 5. Carry skip adder

As shown in the figure 5, if P(i,i+3) = 0, thenthe group is determined by the value of CP(i,i+3) = 1, then the carry-in bit is Ci= 1,carry-in is automatically send to the next gThe name “carry-skip” is due to the fcondition P(i,i+3). Ci is true and then the carryblock entirely. 3.2 CARRY – SELECT ADDER The Carry Select Adder (CSLwords to be added into blocks and forms twblock in parallel (one with a carry in of ZERwith a carry in of ONE) The carry out is the equation for the carry out of the group,propagate signal Pi is the carry out of an adinput of ONE and the group generate Gi siout of an adder with a carry input of ZEROthe computation of the carry signal necessain the next block. The upper 8-bits conditionally using two CSLAs. A multipthen used to select the valid result. The figblock diagram of CSA. As a concrete example, considerthat is split into two 4-bit groups. The lowea1 a0 and b3 b2 b1 b0 are fed into the 4-bit athe sum bits S3 S2 S1S0 and a carry-out bit C

designing High in the literature

he objective of fferent tradeoffs.

gest path in the accelerate carry

accomplished by group of bits. If 1, the condition

p.

output from the tage output of i

n the carry-out of Ci+4. However, if

then the group group of adders. fact that if the y-in bit skips the

LA) divides the wo sums for each RO and the other computed using

, since the group dder with a carry gnal is the carry

O. This speeds-up ary for selection

are computed plexer (MUX) is gure 6 shows the

r an 8-bit adder er order bits a3 a2 adder to produce C4 as shown.

Figure 6. Carry Select

The higher order bits a7 a6 a5 a4 and two 4-bit adders. Adder calculates thof C=0, while the other adder does carry-in value of C=1. Both sets oinputs to an array of 2:1 MUXs. Thefirst adder is used as the select signthen the result of C=0 adder are sentvalue of C4=1 selects the result of C=The carry-out bit C8 is also selected bdesign speeds up the addition of theupper and lower portions of the simultaneously. The price paid isadditional word adder, a set of multiinterconnect wiring. The design becomore important than area consumptio

3.3 CARRY – SAVE ADDECarry – save adder are based on the

Figure7.Carry Sav really has three inputs and produces While it is usually associates ta carry in, it could equally well bvalue. The full adder is used as 3where it starts with bits from 3 bits then has an output that is 2-bits widadder can be build by using n separ‘carry-save’ arises from the fact thatwords instead of using it immediatelsum. Carry-save adders are useful ineed to add more than two numbautomatically avoids the delay in the

t Adder

b7b6 b5 b4 are used as he sum with a carry in the same only it has a of results are used as e carry bit C4 from the al to MUX. If C4 = 0, t to the output, while a =1 adder for S7 S6 S5 S4. by the MUX array.The

e word by allowing the sum to be calculated s that it requires an iplexers and associated omes viable if speed is on.

ER e idea that a full adder

ve Adder

two outputs as shown. the third input with e used as a “regular” 3:2 reduction network words, adds them and

de. An n-bit carry save rate adders. The name t we save the carry out ly to calculate the final in situations where we bers. Since the design

carry-out bits.

4 RESULT AND DISCUSSIONS The design of high speed adders is necessary to increase the computation speed of ALU and it supports to design of high speed processor. In this research, the hardware implementation of various adders has been done to analyze the speed and area. The RTL code has been written in VHDL, Xilinx ISE 9.2i is used to simulate and synthesize the design. The simulation helps to verify the design and the synthesis report gives the speed and area of the design. Finally, the VLSI implemented designs are targeted to the

FPGA device xc3s500e-5-ft256 and captured the real time speed and area of the designs. The comparison table is shown in bellow. The table 3, 4, 5 and Figure 8 shows synthesis report of 32 –bit adder, synthesis report of 16 –bit adder, synthesis report of 8 – bit adder and speed comparison of various adders respectively.The figure 8 represents the comparison chart by taking speed in MHz on Y axis and various adders on X axis.

COMPARISON OF ADDERS: 32-bit adders:

Table 3: synthesis report of 32-bit adders

S.No. Parameter Ripple carry Carry-look ahead Carry-skip Carry-select Carry-Save 1. XOR (1-bit) 32 64 64 48 31 2. No. of Slices 37/960 37/960 42/960 51/768 19/768 3. Levels of Logic 34 34 27 20 3 4. CPU Processing Time 4.68 s 4.59 s 4.34 s 3.40 s 2.71 s 5. Memory Usage 174924 KB 174988 KB 175948 KB 134356 KB 167716 KB

6 Logic Delay 23.859 ns 23.859 ns 17.440 ns 14.081 ns 6.103ns Route Delay 14.806 ns 14.806 ns 9.402 ns 15.774 ns 1.721ns Total Delay 38.665 ns 38.665 ns 26.842 ns 29.855 ns 7.824ns

16-bit adders:

Table 4: synthesis report of 16-bit adders

S.No. Parameter Ripple carry Carry-look ahead Carry-skip Carry-select Carry-Save 1. XOR (1-bit) 16 32 32 24 31 2. No. of Slices 18/960 18/960 21/960 22/768 10/768 3. Levels of Logic 18 18 15 16 3 4. CPU Processing Time 3.77 s 3.555 s 4.67 s 3.66 s 3.97s 5. Memory Usage 140796 KB 140796 KB 141820 KB 134356 KB 133404 KB

6 Logic Delay 14.067 ns 14.067 ns 11.316 ns 12 ns 6.103ns Route Delay 7.623 ns 7.623 ns 5.326 ns 11.163 ns 1.721ns Total Delay 21.69 ns 21.69 ns 16.642 ns 23.163 ns 7.824ns

5.3.2 8-bit adders:

Table 5: Synthesis report of 8-bit adders

S.No. Parameter Ripple carry Carry-look ahead Carry-skip Carry-select Carry-Save 1. XOR (1-bit) 8 16 16 12 15 2. No. of Slices 9/960 9/960 11/960 11/768 5/768

3. Levels of Logic 10 10 9 9 3 4. CPU Processing Time 3.453 s 3.44 s 3.44 s 2.945 s 3.70 5. Memory Usage 139772 Kb 139772 Kb 140796 Kb 134356 Kb 133404KB

6

Logic Delay 9.171 ns 9.171 ns 8.254 ns 8.977 ns 6.103ns

Route Delay 4.032 ns 4.032 ns 3.286 ns 6.945 ns 1.721ns

Total Delay 13.203 ns 13.203 ns 11.54 ns 15.922 ns 7.824ns

Figure 8. Speed (in MHz) comparison chart of adders 5. CONCLUSION The research article describes about the hardware implementation of high speed adders. In this paper, the various adders like full adder, ripple carry adder, carry-look ahead adder, carry-skip adder, carry –select adder and carry- save adeer have been simulated and synthesized on Xilinx ISE 9.2i platform and their parameters are captured. Finally, the captured parameters like speed and area are compared for 8 –bit, 16-bit adders and 32-bit adders. From the table 5, this paper concludes that the carry-save adder is the efficient adder in speed and area consumption. The analysis in table 6 for 32 – bit adder is shown below. Table 6: Speed & Area analysis for 32 – bit adder

Adder Speed ( MHz) Area ( XOR gate) Ripple Carry

Adder 25.8 32

Carry-look ahead adder

25.8 64

Carry-skip adder 37.2 64 Carry-select

adder 33.4 48

Carry-save adder 127.8 63

6. REFERENCES [1]Bruce Shriver and Bennett Smith, The Anatomy of a

High- Performance Microprocessor, IEEE Computer society Press, Los Alamitos, CA, 1998.

[2] James M. Feldman and Charles T. Retter, Computer Architecture, McGraw-Hill, New York, 1994.

[3] Ken Martin, Digital Integrated Circuit Design, Oxford University Press, New York, 2000.

[4] BehroozParhami, Computer Arithmetic, Oxford University Press, New York, 2000. A comprehensive, in depth treatment of the subject.

[5] David A. Patterson and John L. Hennessy, Computer Organization & Design, 2nd edition, Morgan-Koufmann Publishers, San Fransisco, 1998.

[6] Jan M.Rabaey, Digital Integrated Circuits, Prentice Hall, Upper Saddle River, NJ, 1996.

[7] AbdellatifBellaouar and Mohamed I.Elmasry, Low-power Digital VLSI Design, Kluwer Academic Publishers, Norwell, MA, 1995.

[8] William Stallings, Computer Design and Architecture, 4th Edition, Prentice Hall, Upper Saddle River, NJ, 1996.

[9] John P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publishers, Norwell, MA, 1999.

0

20

40

60

80

100

8 - Bit adder 16 - Bit adder 32-Bit adder

Ripple carry

Carry-look ahead

Carry-skip

Carry-select

Carry-save

[10] Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, 2nd edition, Addision-Wesley, Reading, MA, 1993.

[11] Wayne Wolf, Modern VLSI Design, 2nd edition, Prentice Hall PTR, Upper Saddle River, NJ, 1998. 7. ACKNOWLEDGEMENT The authors would like to express my gratitude to the following people for their support in the work leading to this report: Dr. P.S. Venkataramu, Principal, GGITM, who has been the driving force behind this paper. Mrs. VibhaTiwari, HOD, EC Dept., GGITM, Bhopal, India, for her academic support. Mr. Mahendra Vucha, Asst. professor, EC Dept. &project guide, provided much inspiration to usthrough out of this paper. AshutoshAgrawal, my classmate and friend, never seemed to lose faith that the paper would be eventually completed. 8. AUTHORS BIOGRAPHY PrashantGurjarworkingfor hisB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M. P), India.. His areas of interest are Embedded System Design and VLSI Technologies. RashmiSolankiworkingfor herB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M.

P), India.. Her areas of interest are Embedded System Design. PoojaKansliwalworkingfor herB.E degree at Gyan Ganga Institute of Technology and Management, Dept. of Electronics and communication Engineering, Bhopal (M. P), India.. Her areas of interest are Embedded System Design. Mahendra Vucha received his B. Tech in Electronics & Communication Engineering from JNTU, Hyderabad in 2007 and M. Tech degree in VLSI and Embedded System Design from MANIT, Bhopal in 2009. He is currently working for his Ph. D degree at MANIT and also working as Asst. Prof in Gyan Ganga Institute of Tech & Mgmt, Dept. of Electronics and Communication Engineering, Bhopal (M.P), India. His areas of interest are Hardware Software Co-Design, Analog Circuit design, Digital System Design and Embedded System Design.