VOLTAGE AND CURRENT TRACKING CONTROL FOR THE PARALLEL CONNECTION OF VSC H-BRIDGE CONVERTERS WITHOUT

TRANSFORMER

Lourenço Matakas Junior1, Antonio Ricardo Giaretta1,2;

1Polytechnic School of the University of Sao Paulo- Departament of Electrical Energy and Automation Av. Prof. Luciano Gualberto trav. 3 , no 158, 05508-900, São Paulo- SP, Brazil, matakas@pea.usp.br

2ABB Ltda, Av. dos Autonomistas, no 1496, 06020-902, Osasco, SP, Brazil, antonio.giaretta@br.abb.com

Abstract - Paralleled H-bridge converter can be used for interfaces between alternative energy and the mains, for DVRs, FACTs and UPSs. Two strategies for paralleling H-bridge VSC converters without transformer are analyzed. The first case uses separate DC sources and the second one uses a common DC bus. To cope with the coupling between converters in the second case, this paper proposes a current controller with a slack variable. The frequency and phase of the individual PWM carriers, and the ZOH samplers for the individual controllers (voltage and current) are discussed. Experimental results are shown.

Index Terms— multiconverter; parallel connected converters, current tracking, multilevel converter

I. INTRODUCTION Transformeless series connected H-bridge converters

with separate DC supplies are used for high power applications[1,2,3,4,5] . Reference [6] described parallel association with transformer. Paralleled H-Bridge converters can have isolated or common DC supplies according to figure I. Electrical Isolation at the AC side, if required, can be achieved by means of a conventional transformer at their AC output. In this case, no specially designed transformer is required.

Common DC supply Isolated DC supply Figure 1 Parallel Connection of H-Bridge converters

One phase, paralleled H-bridge converters are suitable for

interfaces between alternative energy and the mains, for DVRs, FACTs and UPSs.

This paper presents the modeling for the two cases and proposes control strategies for: a) tracking the individual converter internal currents and the total current; b) tracking the output AC voltage (if required) and c) to minimize the output current ripple.

The frequency and phase of the individual PWM carriers, and ZOH samplers for individual controllers (voltage and current) are discussed. Experimental results are shown.

The case of N H-bridge converters with common DC source presents a strong coupling between converters, which is adequately solved with 2 1N − current controllers, and a slack variable. The common bus also creates circulating ripple currents that depend on the choice of the phase angle of the individual PWM carriers. Simulation and experimental results are presented.

II. MODELING THE PARALLEL TRANSFORMERLESS CONNECTION

Figure 2 shows that the individual H-bridges (basic cell) will operate with two carrier based PWM blocks, using the same carrier waveform and reference signals _A REFv and

_B REFv ( _B REFv is pre multiplied by -1 before being applied to the PWM block). The triangular carrier has amplitude equal to one.

Figure 2 Basic Cell: H-Bridge with three-level PWM

The PWM reference signal _INV REFv is divided by dV2 to cancel the disturbance provided by the DC side voltage. This assures that the averaged gain of the set ‘PWM+H-Bridge’ is instantaneously equal to one, eliminating the disturbance caused by dV . The DC voltage 2 dV can produce an output voltage INVv in the range 2 dV± . The acceptable range of the general reference _INV REFv is also 2 dV± . The internal

references _A REFv and _ _B REF A REFv v= − are in the range 1± ,

resulting in converter voltages AXv and BXv with locally

978-1-4577-1646-1/11/$26.00 ©2011 IEEE 1087

averaged values equal to _A REFv and _B REFv , respectively, in the range dV± .

The voltage source v in figure 2 represents the mains voltage source in applications where the converter is connected to the AC power supply, the counter emf in drive systems or the capacitor voltage at the output LC filter of an UPS, DVR, FACTS, etc.

The circuit in figure 2 provides three level PWM. All the harmonic groups centered around the odd multiples of the carrier frequency CF , for the output voltage INVV are cancelled [7]

The two half bridge can be modeled as two ideal voltage source as indicated in figure 3.

Figure 3 H-Bridge – simplified model.

The current behavior is dictated by eq. 1: A B AX XBdi di v v

dt dt L−

= = (1)

The association of converters will be at first be explained for the connection of N=2 ‘H-Bridge’ converters and then extended to an arbitrary N. For the parallel cases, each converter half bridge cell (‘A1+A1-’, ‘B1+ B1-’, ‘A2+ A2-’, ‘B2+ B2-’) (figure 4 and 5) is modeled as a voltage source

)(tvαβ ( 2121 ;;; BBAA=α and XXX ,; 21=β ) connected to

the virtual nodes X1, X2 (fig. 4) or X (fig. 5). The behavior of the individual currents is presented in items A and B.

A. Parallel connection with isolated DC supplies The behavior of the individual currents is described by eq. 2.

1 1 1

2 2 2

1 1 1

2 2 2

( ) ( )1 0 1 0 1( ) ( )0 1 0 1 11 ( )( ) ( )1 0 1 0 12 2( ) ( )0 1 0 1 1

A A X

A A X

B B X

B B X

i t v ti t v td v ti t v tdt L Li t v t

−⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥= ⋅ ⋅ − ⋅⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎣ ⎦ ⎣ ⎦⎣ ⎦ ⎣ ⎦

(2)

The rank of the controllability matrix of the system described by eq. 2 is 2. As 11 BA ii = and 22 BA ii = , and considering that

1 1 1 1 1inv A X B Xv v v= − and 2 2 2 2 2inv A X B Xv v v= − , the final model can be simplified to :

1 1 1 1 1

2 2 2 2 2

1

2

( ) 1 0 11 ( )( ) 0 1 12 2

1 0 11 ( )0 1 12 2

A A X B X

A A X B X

inv

inv

i t v vd v ti t v vdt L L

v v tvL L

−⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤= ⋅ − =⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎣ ⎦ ⎣ ⎦⎣ ⎦ ⎣ ⎦

⎡ ⎤⎡ ⎤ ⎡ ⎤⋅ −⎢ ⎥⎢ ⎥ ⎢ ⎥

⎣ ⎦ ⎣ ⎦⎣ ⎦

(3)

Eq.(3) shows that 1Ai and 2Ai are fully decoupled. Also the rank of its controllability matrix is equal to 2, indicating that the use of two current controllers (see fig. 6) can impose

any value for 1Ai and 2Ai . The total current Ti is given by:

( )

( )

1 21 2

1 1 1 1 2 2 2 2

( ) 1 ( )2

( ) ( ) 1 ( )2

inv invT A A

A X B X A X B X

v vdi d i i v tdt dt L L

v v v v v tL L

++= = − =

+ − + + −= −

(4)

Eq. (4) shows that the Thevenin Equivalent voltage source is proportional to the sum of the individual half bridge converters, indicating that the use of displaced carriers results in a multilevel equivalent voltage, with harmonics groups concentrated around the multiples of 2N times the carrier frequency [7].

Considering the locally averaged behavior of the converter and 1_ 1_B REF A REFV V= − and 2_ 2 _B REF A REFV V= − , eq.3 can be rewritten as eq.5.( 1_ 1_,A REF B REFV V , 2 _ 2_,A REF B REFV V are the reference signals for the half bridge voltages

1 1 1 1 2 2 2 2, , ,A X B X X A X Bv v v v , respectively).

1_ 1_1

2 _ 2 _2

1_

2 _

ˆ ( ) 1 0 11 ( )ˆ 0 1 12 2( )

1 0 11 ( )0 1 12 2

A REF B REFA

A REF B REFA

INV REF

INV REF

v vi td v tv vdt L Li t

v v tvL L

⎡ ⎤ +⎡ ⎤⎡ ⎤ ⎡ ⎤= ⋅ − ⋅=⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥+⎢ ⎥⎢ ⎥ ⎣ ⎦ ⎣ ⎦⎣ ⎦⎣ ⎦

⎡ ⎤⎡ ⎤ ⎡ ⎤⋅ −⎢ ⎥⎢ ⎥ ⎢ ⎥⎢ ⎥⎣ ⎦ ⎣ ⎦⎣ ⎦

(5)

N converters will behave like N decoupled units.

B. Parallel connection with isolated DC supplies For the two paralleled H-bridge converters, with common

DC bus, shown in fig. 5 with its simplified model, the complete equation is shown in (6).

1 1

2 2

1 1

2 2

( ) ( )3 1 1 1 1( ) ( )1 3 1 1 11 ( )( ) ( )1 1 3 1 14 2( ) ( )1 1 1 3 1

A A X

A A X

B B X

B B X

i t v ti t v td v ti t v tdt L Li t v t

− − −⎡ ⎤ ⎡ ⎤⎡ ⎤ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥− − −⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥= ⋅ ⋅ − ⋅⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥−⎣ ⎦ ⎣ ⎦⎣ ⎦ ⎣ ⎦

(6)

For N converters, each one with two filter inductances with value L, eq.6 becomes:

1 1

2 2

1 1

22

2 1 1 ... 1 11 2 1 ... 1 1

... ... .. ... ...1 1 ... 2 1 11 1 ... 1 2 1

( ) ( )( ) ( )

..... ....( ) ( )

12

( ) ( )( )

.....( )

A A X

A A X

AN ANX

B B X

B XB

BN

NN

NN

i t v ti t v t

i t v tddt NL

i t v tvi t

i t

− − − −− − − −

− +− +

⎡ ⎤⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥= ⋅ ⋅− − − − − −⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥⎣ ⎦⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎣ ⎦

11( )11

( ).....

( )BNX

v tNL

t

v t

⎡ ⎤⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥ ⎡ ⎤⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥− ⋅⎢ ⎥ ⎢ ⎥⎢ ⎥ ⎢ ⎥

⎣ ⎦⎢ ⎥⎢ ⎥⎢ ⎥⎢ ⎥⎣ ⎦

(7)

Both equations present a strong coupling between the converters voltages and currents. Differential Mode voltages among the voltages with index A (or B) will produce high circulating ripple currents, limited by the filter inductance 2L.

The total current is defined by 2121 BBAAT iiiii +=+= , and can be calculated by imposing this condition to eq. 7. It must be noted that 11 BA ii ≠ and 22 BA ii ≠ . The total current Ti for N converters, is given by:

[ ]1, 1,

1 ( )( ) ( ) ( )2T A X B X

N N

d v ti t v t v tdt L Lδ δ

δ δ= =

⎛ ⎞⎛ ⎞= ⋅ + − −⎜ ⎟⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠

∑ ∑ (8)

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In spite of the internal circulating currents, the behavior of the total current is identical to the previous case with separate DC sources, according to eq. 4 (for N=2). In other words, the derivative of total current is proportional to the sum of the individual half-bridge voltages, suggesting the use of displaced carriers to minimize the switching harmonics in the total current.

(7)

Con

verte

r Eq

uiva

lent

Circ

uit

Figure 4 Parallel connection of N=2 converters with isolated DC supply and its simplified model.

Con

verte

r Eq

uiva

lent

Circ

uit

Figure 5 Parallel connection of N=2 converters with common DC supply and its simplified model.

The rank of the controllability matrix of the system in eq.6

is equal to 3 (rank is equal to 2 1N − for N converters). This means that only 2 1N − currents can be tracked, by using 2 1N − controllers. This is further discussed in the next item.

III. CONTROL LOOPS FOR AC CURRENT AND VOLTAGE TRACKING

Based on the two models above presented, this item will show the block diagrams of the control strategies for tracking the inductor current and output capacitor voltage (if it exists, for example for UPS, DVRs aplications). This paper focuses on the structure of the inner current loop, and on the use of displaced carrier PWM to minimize waveforms harmonic content, presenting in figures 6 and 7 the data sampling, and carrier displacement requirements. The basic idea is to displace carriers to achieve ripple minimization at the total and individual currents, and to sample the currents at the peaks of the carriers [11]. The individual current controllers can be, for example, a proportional integral, a resonant or a dead beat one [12]. If the multiconverter output current is conveniently tracked, there are many well known solutions for the outer voltage loop such as the resonant controller and the PI.

All the solutions will use N equally displaced triangular carriers, with asimetrically sampled PWM [11]. The current controllers will sample the waveforms at the peaks of their corresponding carrier. Figure 6 and 7 present the block diagram for the two studied cases, for N=2 [11]. The converters 1 and 2 operate with carrier phases of 0 ( 0∠Cf ) and 90o ( o

Cf 90∠ ) respectively. The voltage loop operates with a sampling frequency af , four times higher than the switching frequency Cf . For the current loops Ca ff 2= . The carriers’ and samplers’ frequencies and phases are presented in fig.6 and 7 for N=2 [11].

Eq. 2 (and 3) presents rank=2. Only two currents can be imposed by the two current loops shown in figure 6. Eq. 6 presents rank =3, requiring 3 ( 2 1N − ) current controllers, shown in figure 7. As will be shown in the next item, any attempt to impose the 4 currents can result in momentary loss of control, even if the sum of the four reference currents is null. In a practical application, gain errors and offsets in the current transducers, amplifiers, A/D converters and filters, result in a measured set of currents, whose sum is not null. The controllers will individually try to force the sum to zero, with no success. Integral part of PI controllers will saturate, even if anti-windup strategies are used, producing momentary loss of control and low frequency oscillations (shown in next item).

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Figure 6 Voltage and Current Control loops for the parallel connection of N=2 converters – separated DC sources

Figure 7 Voltage and Current Control loops for the parallel connection of N=2 converters – common DC source

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One question remains open. If only three current controller are used to calculate the PWM reference voltages

1_ ( )A REFv t , 1_ ( )B REFv t , and 2 _ ( )B REFv t , how to obtain the instantaneous value of 2 _ ( )A REFv t ? As rank=3, for a given solution [ 1_ ( )A REFv t ; 1_ ( )B REFv t ; 2 _ ( )B REFv t ; 2 _ ( )A REFv t ], other solutions can be obtained by summing a signal 0 ( )v t to the original solution, without affecting the individual currents. The three controllers will try to track the currents 421 ,, LLL iii . If they succeed, the slack current 3Li will be naturally tracked, because 1 2 3 4 0L L L Li i i i− + − = .

Theoretically, if the converter maximum output voltage is not considered, any value can be imposed for 2 _ ( )A REFv t . One initial choice is 2 _ ( ) 0A REFv t = . For a real converter, imposing 2 _ ( ) 0A REFv t = will probably require higher voltage amplitudes for the other three converter arms. This will saturate the other PWM modulators. One solution is to choose 0v , to force the sum of the new reference voltages equal to zero, resulting in :

1_ 1_ 2 _0

0( )

4A REF B REF B REFv v v

v t+ + +

= − (7)

Another possibility is to choose 0v to force the absolute values of the maximum and minimum PWM reference voltages to have same value. This reduces the chance of occurrence of individual PWM saturation, and short pulses. In this case 0v is given by:

0

1_ 1_ 2 _

max( ) min( )( )

2: [ , ,0, ]

REF REF

REF A REF B REF B REF

V Vv t

where V v v v

−= −

= (8)

Both strategies work well, and present similar performance. The second case was used in the simulations and experiments presented in the next item.

IV. EXPERIMENTAL AND SIMULATION RESULTS The two H-bridges use IGBTs (IRG4PC50UD). The DSP

is a TMS320LF2407A. A PI controller with anti-windup [8][12], was digitally implemented and used for the current loops (see figure 8). Converter and controller parameters are shown in table I. The choice of controller gains was done based on references [9],[10], to have the minimum amplitude and phase error, and present the maximum disturbance rejection for the chosen switching frequency, keeping the damping factor below 0.7.

Figure 8 PI controller with anti-windup [8].

Table I converter and controller parameters

Symbol parameter value 2Vd1 2Vd2 DC bus voltage 24V

FC Switching frequency 2520Hz FA Sampling frequency 5040Hz

LF1, LF2 Inductor filter 2.5mH CF Capacitor filter 20µF R Resistive load 10Ω Kp Proportional gain 30 Ω KI Integral gain 0.8 Ω/s

Fig. 9 and 10 show the simulated and experimental results,

respectively, for the case with separate DC sources.

Figure 9 simulated waveforms for separated DC sources, considering the switches voltage drop.

Figure 10 experimental waveforms for isolated DC supplies

Total current tracking is reasonable and current ripple is low, even for 2520Hz switching frequency. In these previous experimental results, at extremely low DC bus voltage (24V), the effect of the IGBT (1.65V) and the reverse diode (1.3V) voltage drops seriously affects the tracking performance of the simple PI current controllers. It happens because of the PI low capability to reject the voltage disturbances, specially for

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low switching frequencies [9],[10]. Figure 17 shows that neglecting the switches voltage drops, what is equivalent to e increase of the DC voltage amplitude, substantially reduces this problem. Figures 11 and 12 present the simulated and experimental spectra for the individual and total currents. The individual currents present ripple at 5040Hz, and the total current at 10080Hz, as expected.

Figure 11 simulated spectra for separated DC sources.

Figure 12 experimental spectra for separated DC sources. Figure 13 presents the simulated individual and total

currents for the case of a common DC source, employing four current controllers. In this case, the switches voltage drop and the sensor errors where not considered. Good tracking is achieved. Unfortunately, this condition does not happen in practical converters. If a small gain error of 1% and an offset error of 1% is introduced in the transducers that measure the currents 1Ai and 2Ai , the converters will behave like shown in figure 14, as explained in last item. It shows periods where the controllers loose their tracking capability.

Figure 13 – Simulated waveforms for common DC source, 4 current controllers, ideal case (no sensor errors, ideal switches)

Figure 14 – Simulated waveforms for common DC source, 4 current controllers, non ideal case (1% gain error, and 1% offset error in the

measured currents of converters with index A)

Figure 15 uses the control strategy proposed in figure 7 [11]. It works well even in the presence of errors in the current sensors, and switches voltage drop. The slack current

3Li accumulates all the errors of the 2N-1 remaining controllers. This is clear in figure 15, where 3Li presents a phase error. Even with these errors, the total current harmonics minimization is achieved. Figure 15 shows that the individual currents present ripple at 2520 Hz, which circulates between converters.

Figure 16 shows the experimental results for this case, which are similar to the simulated ones. Here again the effect of he switches voltage drops is visible. Figure 17, shows the same converter, simulated with ideal switches, what is similar to operating at higher DC voltage amplitude. This problem is negligible for the operation near the transistors nominal voltage, as confirmed by simulation. Good tracking is achieved for the individual and total currents, and excellent harmonic reduction is achieved for the total current, even in this example that uses simple PI controllers and only two H-bridges.

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Figure 15 – Simulated waveforms for common DC source, 3 current controllers, non ideal case (1% gain error, and 1% offset error in the measured

currents of converters with index A; switch voltage drop)

Figure 16 – Experimental waveforms for common DC source, 3 current controllers,

Figure 17 Simulated waveforms for common DC source, 3 current controllers, transducer error (1% gain error, and 1% offset error in the measured currents of

converters with index A); ideal switches.

V. CONCLUSION This paper has shown two strategies to track the individual

and total currents of paralleled H-bridge converters, with separate and common DC sources. The case with separated DC sources is adequate for applications where no active power flows through the converter (FACTS, STATCOMs, etc). The N current loops are fully decoupled, and ripple minimization is achieved by equally displacing the PWM triangular carriers.

The second case, with a common DC source, is adequate for the applications where active power flows through the converter (DVRs, rectifiers, UPSs, etc.). The common DC bus provides a coupling between the individual H-bridges, that can disturb the control loops performance, by causing periods where the controller looses their tracking capability. Also, circulating currents appear between converters, which must be minimized. A control strategy with 2N-1 current controllers, and a slack variable was proposed. In this case, the carriers are also equally displaced to minimize the circulating high frequency currents and the total current ripple.

Simulation and experimental results validate the two proposed control strategies. Good tracking is achieved for the individual and total currents, and excellent harmonic reduction is achieved for the total current, even in this example that uses simple PI controllers and only two H-bridges.

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