6-pulse Controlled Rectifier Synchronisation Method

Bhaba Priyo Das, Neville Watson Department of Electrical and Computer Engineering

University of Canterbury Christchurch, New Zealand

E-mail: bhaba.das@pg.canterbury.ac.nz

Yonghe Liu School of Information Engineering

Inner Mongolia University of Technology Hohhot, China

Abstract— The 6-pulse controlled rectifier circuit is very well known. For proper operation of the 6-pulse rectifier, it is necessary to synchronise the firing signals with the mains voltage, else the operation of the rectifier is affected. A firing angle controller, without using any phase lock loop (PLL), is described here. This scheme employs the dq-reference frame to estimate the magnitude and phase angle of the fundamental component of the mains voltage. This method offers structural simplicity and immunity to mains voltage unbalance, harmonics and voltage sag etc.

Keywords- Phase Angle estimation, Rotating Reference Frame, Synchronisation .

I. INTRODUCTION The 6-pulse controlled rectifier (Fig. 1) has a wide range of

applications, from small rectifiers to large high voltage direct current (HVDC) transmission systems, FACTS devices -STATCOM, motor speed control and frequency converters etc. For proper operation of the 6-pulse rectifier, it is necessary to synchronise the gate signals with the mains voltage. Since low quality mains voltage is a common occurrence due to proliferation of power electronic devices, this poses a serious problem to correct mains synchronisation.

Synchronisation is usually carried out by detecting the phase angle of mains voltage and firing each thyristor with respect to a particular point of the phase angle. The signal used for synchronisation is not an ideal sine wave but is distorted by voltage unbalance, harmonics, sags, notches, phase angle and frequency step.

Figure 1. General scheme of 6-pulse rectifier with synchronisation control.

Phase Lock Loops (PLL) has been widely used for synchronisation [1]-[2]. To deal with distortion of the mains voltage, various schemes have been proposed so far using modified PLLs [3]-[10]. Some schemes results in reducing the loop bandwidth, much lower than the frequency of the mains [11]. This leads to slower tracking. Although some other schemes achieve precision phase and frequency tracking, they result in highly complicated structures and practical realisation may become difficult [12]. Several other schemes have also been proposed apart from using PLLs. In [13], sinusoidal voltage at the mains is reconstructed in real time by measuring the distorted waveform at the load end. A neural network based approach is proposed in [14]. In [15] reference frame transformation is used and it drives a PLL. The requirement of 90° all-pass phase shifters prevents the use of this method if there is mains frequency variation. Adaptive filtering techniques use a specific "filtering" technique in order to obtain an un-distorted voltage signal [16].

In this paper, an alternative synchronisation scheme based on transforming the mains voltage into rotating reference (dq-reference) frame and generating the fundamental positive and negative sequence components is described. This scheme can operate under unbalanced, distorted and variable-frequency conditions of the mains voltage. This method offers structural simplicity which can be easily implemented both in hardware and software environments.

II. PROPOSED METHOD OF SYNCHRONISATION Since higher order harmonics like 9th, 11th etc are

insignificant for industrial power systems, this method is considered only upto the 7th harmonic. The DQ transformation is a transformation of coordinates from the three-phase (abc) reference frame to dq-reference frame. The transformation is given by:

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

⎥⎥⎥⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢⎢⎢⎢

⎣

⎡

+−

+−

=

⎥⎥⎥⎥

⎦

⎤

⎢⎢⎢⎢

⎣

⎡

c

b

a

q

d

VVV

ttt

ttt

V

VV

21

21

21

)3

2cos()3

2cos()cos(

)3

2sin()3

2sin()sin(

32

000

000

0

πωπωω

πωπωω

(1)

where Va,b,c: three phase mains voltage.

2011 IEEE Applied Power Electronics Colloquium (IAPEC)

978-1-4577-0008-8/11/$26.00 ©2011 IEEE 40

d

q

VV1tan −

)sin( ppa tVV αω +=

)3

2sin( ppb tVV απω +−=

)3

2sin( ppc tVV απω ++=

22++ += qdp VVV

pα

Figure 2. Proposed synchronisation scheme.

θ = ω0t, ω0: fundamental angular frequency.

In the dq-reference the mains voltage is transformed into DC signals. Under the different corrupting sources abc to dq mapping is given as in Table I [1]:

TABLE I. COMPONENT MAPPING ABC AND DQ-REFERENCE FRAME

Components in ABC reference frame

Mapping into DQ reference frame

Any offset voltage, 3rd or multiple of 3rd harmonic present in all the

three phases.

Harmonics having same frequency

only in zero sequence.

Voltage unbalance in any or all the three phases

2nd harmonic in both d and q

signal.

5th and 7th in all the three phases.

6th harmonic in both d and q

signal.

The fundamental positive and negative sequence components are extracted from the dq-reference frame signal using Yao’s method [17]. If Vdq(t) represents the voltages in dq-reference frame, the dq signal is delayed by a time period (τ) equal to ¼ of the fundamental cycle. Vdq(t-τ) is obtained which has same amplitude as the original signal but is exactly 180° out of phase. Thus, by adding the delayed signal to the original signal cancellation of negative sequence, 5th harmonic, 7th harmonic in dq-reference frame is obtained. The amplitude is doubled which is divided by 2 to get the original amplitude. This is a very simple and fast method by which DC components in the dq-reference frame can be obtained. Once the magnitude of the positive sequence voltage and phase angle is obtained, a set of balanced three phase voltages which are in phase with the positive sequence of the mains voltage can be easily calculated by adding or subtracting 2π/3 radians. Once the three sets of voltages are obtained, the first firing pulse is

obtained at the zero crossing of Vca, where Vca is the phase to phase synchronised mains voltage. The remaining firing pulses are delayed by 60° from each other.

III. FUNDAMENTAL EXTRACTION This section shows the results of fundamental extraction

under various corrupting sources such as voltage harmonics, unbalance, sags, phase outage, frequency jump and phase jump.

A. Voltages in ABC reference frame are unbalanced.

Figure 3. Fundamental extraction under voltage unbalance.

Fig. 3 shows the fundamental extraction under unbalanced mains voltage. The dq-reference consists of a DC + AC signal at twice the mains frequency. Using the method described in section II, the positive and negative sequence components are extracted after a delay of 5ms.

B. Voltages in ABC reference frame are unbalanced with 5th and 7th harmonic. Fig. 4 shows addition of 5th and 7th harmonic to the

unbalanced mains signal. Figs. 5 and 6 show that an additional 6th harmonic component is present in Vd and Vq along with the DC + AC (2nd harmonic) due to unbalance.

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0 5 10 15 200

10

20

30

40

50

60

70

Harmonic order

Fundamental (50Hz) = 325.3 , THD= 24.58%

Mag

(%

of

Fun

dam

enta

l)

Figure 4. Harmonic content of one phase.

Figure 5. Fundamental extraction under voltage harmonics and unbalance.

0 100 200 300 400 500 6000

20

40

60

80

Frequency (Hz)

Fundamental (100Hz) = 88.74 , THD= 20.94%

Mag

(%

of

Fun

dam

enta

l)

Figure 6. Harmonic content of Vd.

Again, the positive and negative sequence components are extracted after a delay of 5ms.

C. Voltages in ABC reference frame are balanced with 5th and 7th harmonic.

In this case, there is only DC + AC (6th harmonic) in Vd and Vq. Fig. 7 shows the extraction of the DC components as Vd΄ and Vq΄.

Figure 7. Fundamental extraction under voltage harmonics.

D. Voltages in ABC reference with loss of phase A voltage at 0.1s.

Figure 8. Fundamental extraction under loss of phase A.

In this case, there is a sudden loss of phase A voltage from 0.10s until 0.16s. Due to loss of one phase, the fundamental positive sequence component Vd decreases, whereas the 2nd harmonic component appears in Vq. Fig. 8, again shows the extraction of the DC components as Vd΄ and Vq΄ within 5ms.

E. Voltages in ABC reference with 50% voltage sag at 0.1s. With voltage sag of 50 % at 0.1s, the fundamental positive

sequence component Vd decreases. Fig. 9 shows that within 5ms, Vd΄ and Vq΄ are extracted.

F. Voltages in ABC reference with phase shift of 20° at 0.1s. Sudden phase change in mains voltage may occur if a large

load is disconnected. This is assumed by applying a step change of 20° in the phase angle. As seen in Fig. 10, this step change is, again, tracked within 5ms with Vd΄ and Vq΄ settling to new DC values within the same timeframe.

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G. Voltages in ABC reference with frequency shift of 1 Hz at 0.1s.

Figure 9. Fundamental extraction under voltage sag.

Figure 10. Fundamental extraction under phase shift of 20°.

Figure 11. Fundamental extraction under frequency shift of 1Hz.

Permitted frequency variation involves a change in frequency of ±1.5 % from the normally stable mains frequency of 50 Hz. To test the response to frequency variation, a step change of 1Hz is applied at 0.1s in the mains voltages. This is tracked by this synchronisation scheme within 17ms. This time is entirely dependent on the real time frequency estimation

principle used. Frequency estimation plays a critical role in this scheme.

H. Voltages in ABC reference has an offset of 10V.

Figure 12. Fundamental extraction under voltage offset.

For digital implementation of such synchronisation schemes, all mains voltage measurements must be made after adding an offset in order to acquire bipolar signals for the analog-to-digital converter. Fig. 12 shows the results obtained after adding a 10V offset to the mains voltage. There is no effect of offset voltage in dq-reference frame as an offset voltage is mapped as zero sequence in dq-reference frame.

IV. PULSE GENERATOR As shown in section III, this scheme tracks the magnitude

and phase angle of the positive sequence component (Vp and αp) correctly in spite of corrupting sources of the mains voltage. Now a set of balanced three phase voltages, in phase with the positive sequence of the mains voltage, can be easily calculated by adding or subtracting 2π/3 radians, as shown in Fig. 13.

Figure 13. Line-to-neutral and line-line generation using proposed synchronisation method.

Loss of phase voltage or voltage sags usually have a phase-jump associated with it. This is quickly tracked as shown in Fig. 13.

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Figure 14. Phase angle determination using the proposed synchronisation method.

Once Vab, bc, ca is synthesized, a ramp starting at the falling zero crossing of Vca is generated. Fig. 14 shows that correct phase angle is obtained even if there is a loss of phase A. This ramp is then compared with the desired firing angle delay to get the first firing pulse. Subsequently, the other 5 pulses are delayed by 60° from each other.

Figure 15. Firing pulses for S1 to S6 for α = 0°

Figure 16. Firing pulses for S1 to S6 for α = 45°

V. COMPARISION WITH OTHER SCHEMES This section provides a comparison of the proposed method

with the existing synchronisation methods such as Low Pass Filter (LPF) based method, Space Vector (SV) based method, Extended Kalman Filter (EKF) based method, Least Squares (LS) based method, PLL based method and Enhanced PLL (EPLL) based method. The range of comparison is divided as:

Not applicable – 0 Poor – 1 Average – 2

Good – 3 Very good – 4 Excellent – 5

TABLE II. COMPARISION BETWEEN DIFFERENT SYNCHRONISATION METHODS

LPF SV EKF LS PLL EPLL Proposed

Harmonics 2 4 1 4 0 5 5

Unbalance 1 1 1 0 0 5 5

Phase step 5 5 5 5 5 5 5

Frequency step

0 1 2 5 5 5 5

Structure 5 4 3 3 4 3 5

Total 13 15 12 17 14 23 25

The LPF-based method is not capable of adjusting to frequency variations. Mains voltage unbalance affects its performance. The SV-based method performs better with respect to mains harmonics but frequency variation limits its operation. The EKF-based method cannot cope with mains harmonics and voltage unbalance. The main drawback of the three phase PLL method is that it cannot provide correct phase angle estimation under harmonics and unbalances. There is a trade-off between PLL bandwidth and response time. EPLL solves most of the problems but is complicated in structure.

VI. CONCLUSIONS The simulation results obtained confirm that the proposed

synchronisation method works very fast for fixed frequency applications. For variable frequency application, the response time depends on the real-time frequency detector. This method offers structural simplicity and immunity to voltage unbalance, mains harmonics, voltage sag, phase and frequency step and voltage offset. This scheme can easily be digitally implemented. This method generates correct firing pulses for the 6-pulse controlled rectifiers. The firing angle can be controlled precisely.

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