Efficient Voltage Feed-Forward Algorithms forSwitched Mode Power Supplies

Magnus KarlssonR&D Ericsson Power Modules

Kalmar, SwedenEmail: magnus.karlsson@ericsson.com

Fredrik WahledowR&D Ericsson Power Modules

Kalmar, SwedenEmail: fredrik.wahledow@ericsson.com

Matz LenellsSchool of Computer Science,

Physics, and MathematicsLinnæus University, Vaxjo, Sweden

Email:matz.lenells@lnu.se

Abstract—We present a number of approximation algorithmsfor voltage feedforward compensation of Switch Mode PowerSupplies. The complexity of the algorithms differs, as well as theirability to suppress input voltage transients. The compensationis attained by manipulating the integral part of the feedbackcontrol law reducing the computation requirements and makes itsuitable for firmware realization in standard Digital Pulse WidthModulation Integrated Circuits or as resource and power efficientimplementations in ASICs.

I. INTRODUCTION

In most Switch Mode Power Supplies, SMPS, topologies,the output voltage, Vout, is directly proportional to the inputvoltage Vin,

Vout ∝ DVin, (1)

where D is the switch duty cycle. When a transient occurson the input voltage, the output voltage will change almostimmediately. The control feedback loop is not fast enoughto neutralize the effect of the transient, only the inertia ofthe output filter of the SMPS will hinder the change of theoutput voltage. The usual solution is to cascade a VoltageFeedForward compensation, VFF, as shown in Fig. 1, see [1],[2], [3], and [4]. In a buck converter the ideal duty cycle is

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Fig. 1. Standard input voltage feedforward compensation.

equal to D = Vout/Vin. When the input voltage changes theduty cycle should be scaled so the output voltage is constant,

Vout = DoldVin−old = DnewVin−new. (2)

Solving (2) for the new duty cycle Dnew yields

Dnew =Vin−old

Vin−newDold. (3)

The computations in (3) consist of a division followed bya multiplication. Since the division is a far more complexoperation than a multiplication, it is in many cases preferableto perform the division by a look-up-table operation [5]. A

mixed signal solution avoiding the division was presented in[6], and [7].

This paper proposes several approximations for VFF com-pensation, with different requirements on computing resources,which yield different levels of suppression of the input voltagetransient. The proposed algorithms can with preference beused in digital power controller ICs, which do not havehardware support for VFF compensation, or do not allowto manipulate the output signal from the controller withthe embedded microcomputer before it is sent to the PWMcircuit, e.g., UCD 3020 from Texas Instruments [8]. Hence,we have to manipulate the controller signals directly. The VFFapproximation algorithms will also work in the normal cascadeconfiguration for reducing the hardware complexity when usedin Application Specific Integrated Circuits, ASICs.

II. VFF COMPENSATION MERGED WITH INTEGRAL

The main idea is to identify an input voltage transient andonly perform the VFF compensation during a transient. Wedefine the change in input voltage as

∆V = Vin−old − Vin−new. (4)

In steady state the value of the integrator in the controller isproportional to or even equal to the duty cycle. Hence, we cancorrect the duty cycle inside the controller instead of outside.By incorporating the VFF compensation with the integraloperation as shown in Fig. 2, the control law remembers thefeedforward compensation until next input voltage change. Thetransient detection block calculates (4) and checks if two con-secutive input voltage samples are different, i.e., set the logicsignal Trans = true. If they are different the compensationcalculation is performed and updates the integral part, Dold, ofthe feedback control law with Dnew. Hence, the computationrequirements are reduced compared to the cascade feedforwardcompensation in Fig. 1, [5], which performs the table look-upand multiplication even when a transient has not occurred.

A. Division less VFF

Solving (4) for Vin−old and replace it in (3) we obtain,

Dnew = Dold(1 +∆V

Vin−new). (5)

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Fig. 2. Input VFF compensation by manipulating the integral part of thefeedback control law.

A division less approximation of the VFF in (3) is obtained byreplacing the division with Vin−new by a multiplication witha constant G,

Dnew = Dold(1 + ∆V G). (6)

Hence, the constant G should be

G ≈ 1

Vin−new. (7)

In order to find the best constant G we define the workingrange for the input voltage Vin as,

Vmin ≤ Vin ≤ Vmax. (8)

The error ε in the approximation in (7) is defined as

ε =

∣∣∣∣ 1

Vmin−G

∣∣∣∣ . (9)

The error ε is minimized when using identical amplitudes withopposite signs at the limits of the input voltage range (8),

εmax =1

Vmin−Gopt = Gopt −

1

Vmax. (10)

Solving for Gopt yields

Gopt =Vmin + Vmax

2VminVmax. (11)

Using Gopt the maximum error εmax in the approximation of(7) becomes

ε =

∣∣∣∣ 1

Vin−Gopt

∣∣∣∣ ≤ Vmax − Vmin

2VmaxVmin= εmax. (12)

The division less VFF algorithm is illustrated in Fig. 3. Tominimize the computation requirements the calculation of thenew duty cycle Dnew is only performed when a transienthas occurred. However, sometimes it can be more efficientto omit the transient detection and always perform the VFFeven when ∆V = 0 yielding a data independent algorithm.This simplified algorithm is shown in Fig. 4.

B. Multiplier less VFF

Using (5) and replacing Dold with the ideal duty cycle inthe last term we obtain

Dnew = Dold +Vout

Vin−oldVin−new∆V = Dold +K∆V, (13)

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Fig. 3. Division less VFF compensation included in integral.

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Fig. 4. Division less VFF compensation included in integral with no transientdetection.

where K is the constant

K ≈ VoutVin−oldVin−new

. (14)

Assuming steady state, i.e., Vin−old = Vin−new = Vin, andusing the same strategy as when defining (10) we obtain

VoutV 2min

−Kopt = Kopt −VoutV 2max

. (15)

Solving for Kopt yields

Kopt =Vout

(V 2min + V 2

max

)2V 2

minV2max

. (16)

Using Kopt the maximum error in the approximation of (14)becomes

ε =

∣∣∣∣VoutV 2in

−Kopt

∣∣∣∣ ≤ Vout(V 2max − V 2

min

)2V 2

maxV2min

= εmax. (17)

A multiplier less realization can be obtained by implementingthe multiplication with K as an arithmetic shift operation, i.e.,approximating the constant as K ≈ 2N , where

N = blog2(Kopt) + 0.5c. (18)

This is commonly referred to as a multiplier less realization[9]. A more exact approximation to the ideal factor Kopt canbe obtained by using several shifts and additions/subtractionsusing Canonic Sign Digit Code [9], which minimizes thenumber add/sub operations. The multiplier less VFF algorithmis shown in Fig. 5. Here the data dependence requires thesame amount of hardware resources or CPU cycles as the VFF

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itself. A simplified multiplier less VFF without the transientdetection is shown in Fig. 6.

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Fig. 6. Multiplication less VFF compensation included in integral with notransient detection.

III. IMPLEMENTING IN HARDWARE

In many standard digital power controller IC’s the PIDcontroller is implemented as a second order Direct form I orII digital filter, [9], also known as a biquad filter, shown inFig. 7, which realize the following transfer function

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Fig. 7. Second Order Direct form I digital filter for implementing the PIDcontroler.

H(z) =b0 + b1z

−1 + b2z−2

1 + a1z−1 + a2z−2. (19)

The industry de-facto standard PID controller requires onlyone second order digital filter, where b1 and b2 realize thePD part of the regulator by placing two zeros at appropriateplaces, and a1 = −1 realize the Integral part. The a2 is keptto zero since it is not needed. The VFF can be incorporated byusing (6), and in case of a transient update the a1 coefficientas

a1 = −(1 + ∆V Gopt). (20)

The digital power controller IC from Texas Instrument, UCD3020, [8], has an embedded ARM-7 processor and dedicatedhardware for realization of (19). The ARM-7 processor hasaccess to the registers in the digital filter and can switchbetween two sets of coefficients. Due to the limited processorcapability of the ARM-7 the calculation of the constant (20)is stored in a look-up table. An alternative realization is to usethe multiplier less approach and calculate the new coefficienta1 as

a1 = −(1 + ∆V Gopt) ≈ 2N . (21)

where N is a suitable integer. The ARM-7 calculates (4) anduse the result as the address to the look-up table and thevalue is shifted into the coefficient register a1. If ∆V = 0no change of the coefficient is performed, which saves CPUcycles. The algorithms are tested on an isolated full-bridgeDC/DC converter with a nominal output voltage of 12 V andinput voltage range of 35-75 V and maximum output currentof 33 A.

A. Transient detection

One problem with digital VFF, even with the originalcascade VFF [5], is when the input voltage is located neara quantization level Q in the input voltage Analog to DigitalConverter, ADC. Measurement noise will sometimes make|∆V | = Q and the VFF will introduce transients on theoutput voltage even when the input voltage is nearly constant.Another case is when the input voltage changes slowly and thevoltage feedback loop compensates for the changes. When theinput voltage changes from one quantization level to the next,the VFF will add additional compensation which introducestransients on the output voltage. This can be avoided usinga minimum threshold Th on the input voltage gradient asshown in Fig. 8. The simplest solution is to make the thresholdequal to 2Q. The same input voltage transient suppression canbe obtained at the cost of one extra bit in the input voltageADC. Noise on the measured input voltage signal can requirea larger threshold, e.g., ≥ 3Q. A third problem was observed

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in the isolated SMPS during light load conditions, i.e., whenthe energy is transfered from the output back to the inputcausing the input voltage to rise, which triggered the transientdetection.

The problems mentioned in the last paragraph may besolved by a more elaborated transient detection circuit andsuch one will be described here. We define that a positive ornegative transient has occurred if one of the four followingconditions are fulfilled:

• One ∆V that is larger than or equal to b1Q.• One ∆V that is smaller or than or equal to −b2Q.• At least X1 samples out of N1 + 2 consecutive samples

that equals Q ≤ ∆V ≤ a1Q.• At least X2 samples out of N2 + 2 consecutive samples

that equals −a2Q ≤ ∆V ≤ −Q.

The corresponding logic schematic is shown in Fig. 9. Whereai ≤ bi, Ni ≥ 0 are suitable integer parameters designed foreach application, and i is 1 or 2 that correspond to positiveand negative ∆V , respectively.

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Fig. 9. A generic transient detection circuit.

The minimum slew-rate of the input voltage transient thatcould be compensated using the transient detector in Fig. 9 isgiven by

slewmin =XQ

(N + 2)Ts, (22)

where Ts is the sampling period. Hence, the minimum slew-rate for voltage feedforward compensation can be designed foreach application by choosing the appropriate quantization stepin the ADC, the sampling period, and the coefficients X,N .Input voltage transients with a slew rate lower than slewmin

must be handled by the feedback loop. The maximum slew-rate the VFF can handle is limited by the delay from the inputvoltage measurement to the actual scaling of the duty cycle.

IV. SIMULATION AND EXPERIMENTAL RESULTS

Results from simulations in Simulink of a buck converterwith 3.3 V output voltage and input voltage of 12 V areshown in the Table I. For comparison a simulation is madefor a controller without any VFF. The simulations show thatthe VFF algorithms reduce the transient over/undershoot verywell. The original cascade VFF algorithm performs best.However, all the other perform almost as good but use muchless computation resources. Since we have quantization effectsof the input voltage and delays in the calculations of the newduty cycle, the transient deviation depend on when in theswitch cycle the transient occurs.

TABLE ICOMPARISON OF SIMULINK SIMULATION RESULTS

VFF Scheme Max overshoot [V] Max undershoot [V]

Without VFF 3.952 -2.373VFF in cascade 0.228 -0.131

VFF inside integrator 0.480 -0.192VFF division less 0.480 -0.131

VFF multiplier less 0.521 -0.253

The performance of the division less VFF algorithm withthe improved transient detection circuit is proven with mea-surements and is illustrated with oscilloscope screen-shots inFig. 10. The input voltage step shown in the lower trace isfrom 40V to 75V during 0.5ms yielding a slew rate of 0.07V/µs. The upper trace shows the output voltage, which has amaximum deviation of 1V and the nominal output voltage isrecovered within 0.5ms.

As comparison, measurement without any feedforward isshown in Fig. 11. Without the voltage feedforward the output(upper trace) rises from 12V to over 22V and the over voltageprotection shuts down the converter. The output voltage staysat this high level due to that the converter output becomes ahigh impedance node. Hence, the VFF attenuates the voltagetransient with a factor of 10.

V. CONCLUSION

We have presented a set of approximation algorithms forvoltage feedforward compensation of Switch Mode PowerSupplies. The compensation is merged with the integral partof the controller reducing the computation requirements. Thealgorithms require different computing resources and havedifferent performance. This makes it easier to find a suitable al-gorithm for a firmware realization in a given standard DC/DCcontrol-IC or an efficient implementations in an ASIC for a

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Fig. 10. Output voltage transient with division less VFF and the improvedtransient detection. Upper trace: output voltage 2V/div, lower trace: inputvoltage 20V/div, timebase 0.5 ms/div.

Fig. 11. Output voltage transient without VFF. Upper trace: output voltage5V/div, lower trace: input voltage 20V/div, timebase 0.5ms/div.

given transient performance. The input voltage transient sup-pression capability is compared by use of simulations. Somesimulation results are verified by experiments, implementingthe division less VFF algorithm in a standard digital powercontroller IC, which suppresses a voltage transient deviationfrom 10V down to 1V at the nominal output voltage of 12Vand a recovery time of 0.5ms.

REFERENCES

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[2] B. Arbetter, and D. Marksimovic, Feedforward Pulse Width Modulatorsfor Switching Power Converters, IEEE trans. Power Electron., vol.12,No.2, pp.361-368, Mar. 1997.

[3] M. K. Kazimierczuk, and A. J. Edstrom, Open-loop peak voltage feedfor-ward control of PWM Buck converter, IEEE trans. Circuits and SystemsI, vol.47, No. 5, pp.740-746, May 2000.

[4] J.-P. Sjoroos, T. Suntio, J. Kyyra, and K. Kostov, Dynamic performanceof buck converter with input voltage feedforward control, EuropeanConference on Power Electronics and Applications, 2005.

[5] M. A. Alexander, D. E. Heineman, K. W. Fernald, and S. K. Herrington,Hardware efficient digital control loop architecture for a power converter,US Patent 7239257, Jul 3, 2007.

[6] A. Syed, E. Ahmed, and D. Maksimovic, Digital PWM controller withfeed-forward compensation, in Proc. IEEE Appl. Power Electron. Conf.,2004, pp.60-66.

[7] X. Zhang, and D. Maksimovic, Digital PWM/PFM Controller with InputVoltage Feed-Forward for Synchronous Buck Converters, in Proc. IEEEAppl. Power Electron. Conf. Expo. , Feb. 2008, pp. 523-528.

[8] Digital Power Controller, UCD 3020, Texas Instruments, http://focus.ti.com/docs/prod/folders/print/ucd3020.html

[9] L. Wanhammar, DSP Integrated Circuits, Academic Press, ISBN 0-12-734530-2, 1999.

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