Specifications-Driven Design Space Boundaries for Point-of-Load Converters

Aleksandar Bjeletić, Luca Corradini, Dragan Maksimović, Regan Zane

Colorado Power Electronics Center University of Colorado at Boulder

{bjeletic, corradin, maksimov, zane}@colorado.edu Abstract - This paper derives physical constraints for the output filter of a Point-of-Load (POL) converter. Time-optimal control theory is employed to translate the POL static and dynamic specifications into boundaries in the L-C design space, ultimately defining a set Σ of L and C values compatible with the application requirements. Outside the identified set Σ, no controller is capable of meeting the POL specifications; inside the identified set Σ, various degrees of approximation of the time-optimal response are possible, depending on the specific control approach in the field application. The identified set shows the minimum possible values of L and C such that the specifications can be met, which allows the designer to evaluate the impact of a practical controller implementation on the size of the output filter. The design space and boundaries for a digital PID controller are derived, leading to a combined L-C filter and controller design approach. Experimental results validating the design space boundaries are presented for a 12V-to-1 V, 20 A POL converter.

I. INTRODUCTION In Point-of-Load (POL) voltage regulators typically

based on the synchronous buck converter shown in Fig. 1(a), the key design objectives are to meet static and dynamic voltage regulation specifications and to maximize efficiency, while at the same time minimizing cost and size, which in turn are closely related to the values of the output filter passive components L and C. It is therefore of significant practical interest to find the L-C design space boundaries, i.e. bounds on the values of L and C such that static and dynamic voltage regulation specifications can be met. For example, motivated by the efficiency versus size trade-offs, an upper bound for L (called “critical inductance”) has been determined in [1], and linked to an upper bound on the controller bandwidth (called “critical bandwidth”) [2]. In the cases when a high slew rate step-load transient response is dominated by the capacitor ESR, normalized critical output filter parameters have been found in [3]. Acceptability boundary curves found in [4] allow selection of a minimum required C assuming a sufficiently high bandwidth controller.

In state-of-the-art POL converters with low-ESR ceramic capacitors, transient responses depend very strongly on the controller architecture and performance, which significantly complicates determination of L-C design space boundaries,

Vref

Controller+

−

C

L

VinBuck Converter

voModulator

S iload

(a)

0 200 400 600 800 10000

500

1000

1500

2000

2500

3000

L(nH)

C(μ F

) Σ

Δvo < Δvo,max

ΔiL < ΔiL,max tr < tr,max

Minimum L and C

Δvripple < Δvripple,max

(b)

Figure 1. (a) Synchronous buck converter for POL regulation, and (b) example of design space boundaries in the L-C plane for the output voltage

ripple Δvripple,max, inductor current ripple ΔiL,max, recovery time tr,max and output voltage deviation Δvo,max after a high slew-rate step-load transient

but also opens opportunities for various controller-based or configuration-based improvements (e.g. [5]-[20]). The objectives of this paper are to derive absolute specifications-driven design space boundaries, as illustrated by an example in Fig. 1(b), which can be used to determine the smallest possible L and C values, and also to evaluate the effectiveness of various available control approaches. Section II derives the ultimate L and C bounds based on the application static and dynamic specifications. The L-C design space boundaries are derived for a digital PID controller in Section III. In Section IV a combined power-stage and controller design approach is implemented to concurrently find a design for the output filter of the POL regulator and for the controller parameters. Simulation and experimental verification results are presented in Section V.

978-1-4244-8085-2/11/$26.00 ©2011 IEEE 1166

II. DESIGN SPACE BOUNDARIES BASED ON POL SPECIFICATIONS

The static and dynamic specifications considered in this paper are: input voltage Vin, output voltage VO, step load current amplitude ΔIload, recovery time tr,max, and output voltage deviation Δvo,max for a worst case step load, and steady-state output voltage and inductor current ripples Δvripple,max and ΔiL,max. For definiteness, specific values considered throughout this paper are Vin = 12 V, VO = 1 V, ΔIload = 10A, tr,max = 12 μs, Δvo,max = 50 mV, Δvripple,max = 10 mV, ΔiL,max = 6A and fs = 780 kHz.

As mentioned in the introduction, many works found in recent literature analyze the transient response capabilities of the POL regulator assuming a sufficiently high bandwidth controller, such that the initial part of the converter response to a step load is duty-cycle saturated [1]-[4]. In this Section, this concept is further developed assuming that an ideal time-optimal controller (TOC) [5]-[11] is regulating the output voltage during a transient response. By constraining the TOC response to the application specifications, the largest possible set Σ of L and C values compatible with the system specifications is derived. Outside Σ, no controller can meet the application requirements; inside Σ, various degrees of approximation of the time-optimal response are possible, depending on the specific control approach implemented in the field application. Most important, Σ contains the minimal output filter compatible with the application requirements as pointed in Fig. 1(b), setting an ultimate limit to the POL design and performance.

The TOC transient response of the output voltage vo(t), inductor current iL(t) and switching signal S are shown in Fig. 2(a) for the case of a step-down event and in Fig. 2(b) for the case of a step-up event. Note that the worst case situation has been considered in both cases, in which the step load occurs at the inductor current peak or valley.

Equations for the TOC design boundaries in the L-C space are presented in Table I, where M = VO/Vin and fs is the switching frequency. Note that the boundaries imposed by the dynamic specifications depend on the step-down or step-up nature of the load disturbance.

The minimum and maximum value of the output filter inductance L are dependent only on the inductor current ripple and the recovery time specifications, respectively.

The L-C design space boundaries are presented graphically in Fig. 3(a) and (b). Two sets Σd and Σu are determined for the step-down and step-up transients respectively.

The arrows on top of each boundary are pointing towards the direction in which each specification is met in the L-C plane, while the shaded area represents the set of values Σ for L and C that are able to meet all the POL specifications.

Δvripple

t

Δvo

tr

vo(t)

ΔIload tΔiL

iL(t)

Vo

St

(a)

Δvripple

tΔvo

tr

vo(t)

ΔIload t

ΔiL

iL(t)

Vo

St

(b)

Figure 2. Waveforms for the output voltage vo(t), inductor current iL(t) and switching signal S during: (a) step-down transient, (b) step-up transient

The absolute boundaries for the L-C design space is the intersection of the two sets Σd and Σu, forming the set Σ presented in Fig. 4. As expected in a POL application, the step-down load event imposes the most dominant constraints in the L-C design space. For this reason, the analysis presented here focuses on the step-down case only.

From Fig. 4, the minimal LC filter for the specifications considered in this paper assuming ideal TOC are L = 196 nH, C = 376 μF.

III. DESIGN SPACE BOUNDARIES FOR DIGITAL PID

A. Design Space Exploration for a Digital PID In a practical POL converter implementation it is not

possible to reproduce an ideal time-optimal response. The transient response and performance depend on the controller architecture and the output filter of the POL converter. The set Σ derived in the previous section serves as a reference to compare the design space boundaries for different control architectures. A digital PID is selected as the control architecture due to its simplicity and popularity.

1167

0 500 1000 1500 2000 2500 30000

500

1000

1500

2000

2500

3000

L(nH)

C(μ

F)

tr,down < 12 μsΔiL < 6 A

ΣdΔvo,down < 50 mV

Δvripple < 10 mV

(a)

0 400 800 1200 1600 2000 2400 28000

500

1000

1500

2000

2500

3000

C(μF

)

L(nH)

tr,down < 12 μsΔiL < 6 A

Δvo,down < 50 mVΔvripple < 10 mV

Σu

(b)

Figure 3. Design space boundaries for an example of POL specifications: Vin = 12 V, VO = 1 V, ΔIload = 10A, tr,max = 12 μs, Δvo,max = 50 mV, Δvripple,max

= 10 mV, ΔiL,max = 6A, fs = 780 kHz

In a standard, frequency-domain based design approach, the proportional, integral and derivative gains of the PID are selected to achieve a desired control bandwidth fBW (i.e. cross-over frequency), and phase margin ϕm. The recovery time specification is substituted by a ±1 % settling time.

The purpose of the following analysis is to derive approximate design boundaries for a voltage-mode controlled POL based on a PID compensator. Since static specifications result in design space boundaries which are independent of the controller, the discussion here focuses on the dynamic specifications only.

During a load step-down transient the PID controller can have two operating behaviors:

- Linear operation, i.e. the duty cycle command never saturates during the transient response.

- Saturated or nonlinear operation, i.e. the duty cycle command saturates at zero for at least one switching cycle during the transient response.

The conditions that define the behavior of the digital PID can be derived by relating the step load ΔIload and the duty cycle command by means of the output current-to-control transfer function Giod:

TABLE I CONSTRAINTS FOR THE OUTPUT FILTER COMPONENTS FOR IDEAL TIME-OPTIMAL CONTROL

Specification Boundary in the L–C design space

Output voltage ripple (Δvripple) ( )

max,21

81

ripples

Oripple v

LCfVM

v Δ<⋅−

=Δ max,

28-1

ripple

O

s vV

fMLC

Δ⋅>

Inductor current ripple (ΔiL) max,1

LO

sL i

LV

fMi Δ<⋅−=Δ

max,

1

L

O

s iV

fML

Δ⋅−>

Recovery time (tr)

(STEP-DOWN)

( )max,

111

2r

O

Lloadr t

ML

ViI

t <⎟⎟⎠

⎞⎜⎜⎝

⎛

−+

Δ+Δ= ( )( ) M

MiI

tVL

Lload

rO

−+−⋅

Δ+Δ⋅

<11

12

max,

Output voltage deviation (Δvo)

(STEP-DOWN)

( )( )max,

2

22

oO

Lloado v

CL

ViI

v Δ<Δ+Δ

=Δ ( )( )2

22

max,

Lload

oO

iI

vVCL

Δ+Δ

Δ⋅<

Recovery time (tr)

(STEP-UP)

( )max,1

2r

O

Lloadr t

MMML

ViIt <⎟

⎟⎠

⎞⎜⎜⎝

⎛

−+Δ+Δ= ( )( ) MM

MiI

tVL

Lload

rO

+−⋅

Δ+Δ⋅

< 12

max,

Output voltage deviation (Δvo)

(STEP-UP)

( )( )max,

2

122

oO

Lloado v

MM

CL

ViI

v Δ<−

⋅⋅Δ+Δ

=Δ ( )( )1

2

22

max,

MM

iI

vVCL

Lload

oO −⋅Δ+Δ

Δ⋅<

1168

0 200 400 600 8000

500

1000

1500

2000

2500

3000

L(nH)

C(μF

) Σ

ΔiL < 6 A tr < 12 μs

Δvripple < 10 mVΔvo < 50 mV

Figure 4. Absolute space boundaries of the considered POL converter.

( ) ( )( ) ( ) ( )sPIDsZsisdsG clout

oiod ⋅== _ , (1)

where Zout_cl represents the closed-loop output impedance of the POL converter. The largest change in the duty cycle command occurs right after the step load is applied. Using the initial value theorem, the initial duty cycle step ΔD can be determined as:

( ) loadDload

iodsI

CK

sI

ssGD Δ=⎥⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛ Δ=Δ

∞→lim (2)

When the control bandwidth fBW is much higher than the resonant frequency of the output filter f0 the derivative gain can be approximated as:

loadin

BWD I

VLCf

K Δ⋅⋅π

≅2

. (3)

The initial duty cycle step ΔD is therefore found:

loadin

BW IV

LfD Δ

⋅⋅π≅Δ

2 (4)

If ΔD < D the PID controller always operates in its linear region; however, if ΔD > D the controller exhibits a saturated behavior for at least one switching period. Such inequalities define a boundary in the LC design space which separates the linear and saturated responses of the system. Observe that, for a given bandwidth fBW, such boundary is essentially determined by the output filter inductance L.

The output voltage deviation Δvo can be treated analytically in both the linear and saturated case with the assumption of a linear variation of the inductor current during the initial part of the transient. The approximation is exemplified in Fig. 5(a) and 5(b) for the linear and saturated response respectively.

The inductor current slope expression for the linear operation is

loadBwinL IfL

DVdtid

Δ⋅⋅π=Δ

= 2 , (5)

while the corresponding expression for the saturated case is

L

Vdtid OL = . (6)

By means of the foregoing approximation, the expression for the voltage deviation Δvo is found to be:

( ) ( )

Cdt

idiI

IDT

vL

Lloadloads

o

⎟⎟⎟⎟

⎠

⎞

⎜⎜⎜⎜

⎝

⎛Δ+Δ

+Δ

=Δ

2

21

(7)

Note that this approximation also assumes a negligible capacitor equivalent series resistance (ESR); such hypothesis is well verified in recent POL designs employing low-ESR ceramic capacitor banks.

loadBW Ifm Δ⋅⋅π= 22

ΔIload

iL(t)

t

ΔiL

Δvripple Δvo

vo(t)

Vo

t

Linear

dtid L

(a)

ΔIload

iL(t)

tSaturated

ΔiL

Δvripple Δvo

vo(t)

Vo

t

dtid L

(b)

Figure 5. Waveforms of the output voltage vo(t) and inductor current iL(t) for the analysis of the output voltage deviation when the PID exhibits: (a)

linear operation, (b) saturated operation

1169

Gvd(z): Control to output transfer function

Zout_ol(z): Open-loop Output Impedance

PID(z)

Step load: 10A

Figure 6. Simulink model used for the design space exploration in case of

digital PID compensation

From the foregoing expressions and for a given bandwidth fBW, Δvo is expected to be dependent on the value of C and have almost no dependence on the system inductance L as long as the controller operates in its linear region, while a linear dependence on L and C arises in the saturated response. In both cases, the capacitance C is seen to limit the overall voltage deviation.

As far as the settling time is concerned, note that in the linear region the value of the inductance L is expected to have little influence on the duration of the transient. This duration will be dependent on the value of C and the control bandwidth. On the other hand, the performance of the saturated response is limited by the inductor current slew rate and therefore by the inductance, as seen in Fig. 5(b). Larger values of C are therefore expected to be needed in order to limit the overall settling time once the controller enters the saturated region.

Although analytical expressions could be derived for the settling time, such expressions would necessarily have limited accuracy due to the approximations involved. Therefore, validation of the foregoing qualitative considerations is performed with the aid of computer simulations. Such simulations also have the purpose of validating the analytical models for the linear/saturated boundary and output voltage deviation Δvo.

To this end, a Simulink model was developed as shown in Fig. 6. This model can analyze both linear and saturated operation of the PID controller, and was employed to generate the L−C design space boundaries according the following approach:

1. The (L, C) design space was swept, simulating the dynamic response at each (L, C) point;

2. Control bandwidth fBW and phase margin ϕm were kept constant throughout the sweep: at each (L, C) point the PID controller was recalculated for the selected bandwidth and phase margin;

3. Static and dynamic performances of the converter were checked against the system specifications at each (L, C) point of the sweep.

0 200 400 600 8000

500

1000

1500

2000

2500

3000

L(nH)

C(μ F

)

fbw = 50 kHz, ϕm = 43ºΔiL < 6 A

SaturatedLinear

Δvripple < 10 mV

ΣPIDtsett < 12μs

Δvo < 50 mV

TOCExp. 1

(a)

0 200 400 600 8000

500

1000

1500

2000

2500

3000

L(nH)

C(μ F

)

fbw = 60 kHz, ϕm = 43ºΔiL < 6 A

SaturatedLinear

Δvripple < 10 mV

ΣPIDtsett < 12μs

Δvo < 50 mV

TOCExp. 2

(b)

0 200 400 600 8000

500

1000

1500

2000

2500

3000

L(nH)

C(μ F

)

fbw = 45 kHz, ϕm = 43ºΔiL < 6 A

SaturatedLinear

Δvripple < 10 mV

ΣPIDtsett < 12μs

Δvo < 50 mV

TOCExp. 3

(c)

Figure 7. Design space using a digital PID compensator for different controller specifications: (a) fBW = 50 kHz, ϕm = 43º, (b) fBW = 60 kHz, ϕm =

43º, (c) fBW = 45 kHz, ϕm = 43º

Fig. 7 (a), (b) and (c) report simulation results for three different control bandwidths. From these figures it can be observed that the settling time in the linear region is dependent on C and the control bandwidth fBW, where in the saturated region it is strongly dependent of L, C and fBW. Also, as predicted by (5), (6) and (7) the output voltage deviation in the linear case is independent of L. For the saturated case there is a dependence on L and C, but no dependence at all on the value of the control bandwidth fBW.

B. Discussion These different design space examples presented in

Fig. 7(a), (b) and (c), and many others that can be derived by changing the controller parameters, give the designer multiple choices for the design of the POL converter. In order to reduce ambiguities in the design decisions, and motivated by the goals of meeting the specifications with L-C filter size and required controller bandwidth in mind, a

1170

combined power-stage and controller design approach is proposed. This approach consists of obtaining a good tradeoff between the values of the output filter and the controller parameters. In Fig. 7(b) low values of L and C are obtained but the control bandwidth is the largest. Meanwhile, in Fig. 7 (c) the control bandwidth is low but the output filter components have larger values. A good compromise between component size and required bandwidth is observed at the point labeled as Exp. 1 in Fig. 7(a). The output voltage transient response corresponding to such point is shown in Fig. 8, and presents the following characteristics: the output voltage deviation is equal to the specification, the settling time is the maximum allowed, the output voltage undershoot is just at the ±1% settling band and the PID controller operates at the boundary between linear and saturated operation. Such design corresponds, with the system specifications given in Section II, to L = 314 nH, C = 538 μF, fBW = 50 kHz and ϕm = 43º.

IV. COMBINED POWER-STAGE AND CONTROLLER DESIGN APPROACH USING A

DIGITAL PID Motivated by the foregoing considerations, the approach

presented in this section designs a POL converter that has an output voltage response as shown in Fig. 8. This approach is implemented using a nonlinear constrained optimization (function fmincon in MATLAB), which allows the designer to constrain a function according to a set of desired boundaries.

The design is done in the following manner: the inductance L is chosen such that the PID is always at the boundary of linear and saturated operation, then the MATLAB algorithm solves for the bandwidth, phase margin and C corresponding to the sought output voltage waveform. The algorithm employs the closed loop output impedance Zout_cl and (4) to predict the behavior of the output voltage transient response.

By using this approach any arbitrary choice regarding the output filter components and controller parameters (especially phase margin) has been eliminated, since control bandwidth and phase margin are now determined from the system specifications. The solution provided with this design approach is validated with simulation and experimental results.

V. SIMULATION AND EXPERIMENTAL RESULTS

The experimental prototype employed to validate the foregoing design approach consists of a 12 V-to-1 V, 20 A, 780 kHz synchronous buck converter interfaced to a Xilinx Virtex-4 FPGA development board, which implements a time-optimal response and a digital PID controller depending on the desired control approach. Due to the limited choices in the values of real capacitors and inductors, the values used for the experimental results are slightly different that the ones found and used in simulation results. The values used for the experimental results are shown in the figures.

0 5 10 15 20 25 30 35 40 45 50-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

Time (μs)

Out

put

Vol

tage

(V

)

tsett = tsett,max

Undershoot = ± 1% settling band

Δvo = Δvo,max

Figure 8. Desired output voltage transient response used by the combined

power-stage and controller design approach.

0 2 4 6 8 10 120.980.99

11.011.021.031.041.051.06

Out

put V

olta

ge (V

)Time (μs)

L = 196 nH, C = 336 μF

Figure 9. Simulated time-optimal response for minimum L and C

vo

iL

Load enable

S

2 μs/div5 A/div

50 mV/div

L = 215 nH, C = 376 μF

Figure 10. Experimental result for the minimum L and C (time-optimal response)

A simulated time-optimal response as shown in Fig. 9 validates the minimum possible capacitance and inductance found in Section II. The values of the output filter components found are: L = 196 nH and C = 336 μF. Experimental results of the time-optimal response with L and C values close to those predicted are presented in Fig. 10.

1171

0 5 10 15 20 25 30 35 400.98

1

1.02

1.04

1.06

1.08

Time (μs)

Out

put V

olta

ge (V

)L = 314 nH, C = 538 μF

Figure 11. Simulated step-down transient response corresponding to point

Exp. 1: L=314nH, C=538μF, fBW=50kHz, ϕm=43º.

vo

iL

Load enable

S

4 μs/div

5 A/div

20 mV/div

L = 316 nH, C = 564 μF

Figure 12. Experimental (Exp. 1) transient response to a 20-10 A load step;

vo : 20 mV/div, iL: 5 A/div, time scale: 20 μs/div

0 5 10 15 20 25 30 35 400.98

1

1.02

1.04

1.06

1.08

Time (μs)

Out

put V

olta

ge (V

)

L = 266 nH, C = 484 μF

Figure 13. Simulated step-down transient response corresponding to point Exp. 2: L=266nH, C=484μF, fBW=60kHz, ϕm=43º.

The test is done in an open loop setup with a fixed duty cycle command used before and after the transient during steady-state operation.

The timing of the transient is known in advance and the duration of the low and high switching action of S are calculated and preprogrammed in the FPGA. As predicted by the design space in Fig. 4 the inductor current ripple and output voltage deviation are just met, while the recovery time

and output voltage ripple specifications are met with margins.

vo

iL

Load enable

S

4 μs/div

5 A/div

20 mV/div

L = 264 nH, C = 517 μF

Figure 14. Experimental (Exp. 2) transient response to a 20-10 A load step; vo : 20 mV/div, iL: 5 A/div, time scale: 20 μs/div

0 5 10 15 20 25 30 35 400.98

1

1.02

1.04

1.06

1.08

Time (μs)

Out

put V

olta

ge (V

)L = 362 nH, C = 656 μF

Figure 15. Simulated step-down transient response corresponding to point

Exp. 3: L=362nH, C=656μF, fBW=45kHz, ϕm=43º.

vo

iL

Load enable

S

4 μs/div

5 A/div

20 mV/div

L = 365 nH, C = 658 μF

Figure 16. Experimental (Exp. 3) transient response to a 20-10 A load step; vo : 20 mV/div, iL: 5 A/div, time scale: 20 μs/div

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Simulated and experimental results for the case of closed-loop digital PID compensation are shown in Fig. 11 and Fig. 12 for Exp. 1. The following parameters are used: L = 314 nH, C = 538 μF, A/D quantization qA/D = 1 mV and DPWM resolution qDPWM = 11 mV. The PID controller is designed for a control bandwidth fBW = 50 kHz with 43º of phase margin as determined by the combined power stage/controller design approach discussed in Section IV.

The second set of simulations and experiments, illustrated in Fig. 13 and 14 and corresponding to Exp. 2, presents the design from Fig. 7 (b). L = 266 nH, C = 484 μF, fBW = 60 kHz, ϕm = 43º. As expected the settling time is smaller than the maximum allowed by the specifications and the output voltage deviation is the maximum allowed.

Fig. 15 and 16 report simulation and experimental tests for Exp. 3, i.e. the point in Fig. 7(c). This design refers to the following values: L = 362 nH, C = 656 μF, fBW = 45 kHz, ϕm = 43º. These results validate are assumption that the output voltage deviation exceeds the specification and the settling time is equal to required maximum.

It is worth observing how the proposed design approach, by coupling the design of the compensator with the design of the power stage, results in an LC output filter which is very close to the ideal TOC limit requirements.

VI. CONCLUSIONS This paper derives physical constraints for the output

filter of Point-of-Load (POL) converters. Time-optimal control theory is employed to translate the POL converter static and dynamic specifications into boundaries in the L-C design space, defining a set Σ of output filter LC values compatible with the application requirements. Outside the identified set Σ, no controller is capable of meeting the POL specifications; inside the identified set Σ, various degrees of approximation of the time-optimal response are possible, depending on the specific control approach implemented in the field application. The identified set allows the designer to evaluate the impact of a practical controller implementation on the size of the output filter relative to minimum possible, including tolerances. A similar analysis is also presented for the case of digital PID compensation, defining a subset ΣPID. This subset varies depending on controller parameters. A combined power stage and controller design approach is proposed that simultaneously determines the output filter parameter and the controller bandwidth and phase margin, providing a good tradeoff between size of the output filter and required control bandwidth. Experimental results verifying the design space boundaries are presented for a 12V-to-1V, 10A POL converter.

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