Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects

1Madhumanti Datta, 2Susmita Sahoo, 3Rajib Kar Department of Electronics and Communication Engineering

National Institute of Technology, Durgapur, West Bengal, INDIA 1madhumanti_datta@rediffmail.com, 2 susmitas1987@gmail.com , 3 rajibkarece@gmail.com

Abstract— With the increase in the levels of on-chip integration, the number of functional units integrated onto a single chip is rapidly increasing and as a result, the logic delays are decreasing due to faster transistors. At the same time, the local interconnect delays improve because the physical size of the circuit blocks decrease and the local interconnect spans shorter distances. On the other hand, the global interconnect delay increases with the technology scaling. Multiple design criteria are considered during the interconnect design process, such as delay, power, bandwidth and noise. Performance of any VLSI circuit depends on the bandwidth, as it decreases with the increase in the length of interconnects. Depending on the frequency range of operation, on-chip interconnect can be modelled as lumped and/or distributed RC line for low frequency and as a distributed RLC segments for high frequency. At even higher frequency, of the order of above 10GHz, the shunt conductance needs to be considered for accurate interconnect modelling. In this paper, on-chip interconnect has been modelled as distributed RLCG transmission lines, based on which a crosstalk aware bandwidth estimation method has been proposed in the transform domain in the presence of both inductive as well as capacitive coupling. First, the amount of crosstalk noise that would be induced on the victim line due to the transiting aggressor line has been analytically derived and then from the crosstalk noise voltage, a closed form expression for bandwidth has been proposed for distributed RLCG VLSI interconnects. The calculated bandwidth has been compared with the results obtained from that of SPICE simulation. The simulation shows that the proposed model could result an average error of as low as 15% when compared to the SPICE simulation.

Keywords- Distributed RLCG Segments; On-Chip Interconnect; Crosstalk; Bandwidth Estimation; VLSI

I. INTRODUCTION With the increase in signal frequency and decrease in the

transistor sizes, the effect of interconnect has become a dominant factor in determining the circuit performance in deep submicron technology. At low frequencies, interconnect lines can be modelled as lumped and/or distributed RC circuit model. But in today’s technology, as the signal frequency is rapidly increasing, the effects of the inductance can no longer be ignored. Also at high signal speed, the electrical length becomes a significant fraction of the operating wavelength. So at high frequency, conventional lumped models are inadequate to capture the dynamic characteristics of the circuit. At even higher frequency, of the order of above 10GHz, the shunt conductance needs to be considered for accurate interconnect

modelling. In sub-micron technologies, as the pitch between interconnects is very small, the effect of coupling between these interconnects becomes a significant performance limiting factor [1]. Indeed, the order of coupling between interconnects becomes so high that one can’t ignore the noise due to this coupling [2]. As the integrated circuits feature size continues to scale well below 0.18 microns, active devices counts are reaching hundreds of millions [3]. The amount of interconnects among the devices tend to grow super linearly with the transistor counts and the chip area is limited by the physical interconnect area. Hence, one should consider the effects of mutual inductance and coupling capacitance between the parallel interconnects. Bandwidth has a key role to define the performance of any circuit basically used for data transmission application. A higher bandwidth reduces the total time required to transmit a certain amount of data and hence increases the performance of the system. Several factors bound to the technology contribute to the bandwidth problems. Among all these problems, capacitive and inductive coupling induced crosstalk is the most severe issue to be properly addressed. Crosstalk is any phenomenon by which a signal transmitted on one circuit or channel of a transmission system creates an undesired effect in another circuit or channel. It happens between the adjacent wires when their mutual inductance and cross coupling capacitance are large enough to affect each other’s electrical properties. Several factors are responsible to increase the crosstalk problem: i) The increase in the number of metal layers [5]; ii) The increase of the line thickness; iii) The density of integration and iv) The reduction of the spacing between lines. Among all of these factors, capacitive and inductive coupling induced crosstalk is the severe issue. For an on-chip bus, crosstalk noise is a serious problem in VLSI design. In this paper, the effect of mutual inductance as well as cross coupling capacitance for a highly coupled RLCG interconnect structure has been considered. R. Kar et.al. [4] proposed a model for bandwidth for distributed RLCG interconnects without considering the effect of the mutual inductance and coupling capacitance. But in today’s VLSI technology, the order of crosstalk coupling is so severe that accurate estimation analysis of any performance metrics has to be carried out in the coupling environment. In this paper, a closed form expression for bandwidth has been derived for distributed RLCG interconnects in the presence of mutual inductance and coupling capacitance.

The rest of the paper is organized as follows: Section 2 discusses the basic theory, transmission line model, crosstalk

978-1-4244-9190-2/11/$26.00 ©2011 IEEE

and different modes of operation. Section 3 describes the proposed closed form formula for the on-chip interconnect bandwidth calculation. Section 4 shows the simulation results and finally Section 5 concludes the paper.

II. BASIC THEORY

A. Transmission Line Model A transmission line [6] has a series connection of

inductance and resistance and a parallel capacitance and conductance. An infinitesimal unit length of transmission line looks like the circuit as shown in Figure 1.

Figure 1. RLCG Segment of a Transmission Line

In Figure 1, R = Series resistance per unit length L = Series inductance per unit length C = Shunt capacitance per unit length G = Shunt conductance per unit length For the high speed interconnection system, the transmission

lines include long transmission lines, connectors, vias and crosstalk from adjacent interconnects. An equivalent circuit is extracted with the help of Maxwell, a 2.5-dimensional full-wave solver [11]. Raphael [12] and Fast Henry [13], magneto-quasi-static interconnect analysis tools, are also used. The transient simulations were carried out with HSPICE [14].

The extracted values of R, L, C, and G for 180nm technology are given in Table1.

TABLE I. RLCG PARAMETERS FOR MINIMUM SIZED WIRES IN 0.18µM TECHNOLOGY

Parameter(s) Value Resistance(R) 120kΩ/m Inductance(L) 270nH/m

Capacitance(C) 240pF/m Conductance(G) 15f pS/m

Mutual Inductance(Lm) 54nH/m Coupling Capacitance(Cc) 0.82fF

B. Cross-Talk Crosstalk is the coupling of energy from one line to another via (refer to Figure 2):

1. Mutual capacitance (electric field) 2. Mutual inductance (magnetic field)

The magnitude of the crosstalk is a function of rise time, signal line geometry and net configuration. In order to reduce the crosstalk effect, several methodologies have been employed [7]. A common method is shielding, where the

ground or power lines are placed at the sides of a victim signal line to reduce noise and delay uncertainty. The crosstalk noise between two shielded interconnects can produce a peak noise of 15% of Vdd in a 0.18µm CMOS technology [8]. Crosstalk can induce delays which can change the signal propagation time. Crosstalk also produces glitches which in turn cause the voltage spikes on the wires resulting in false logic behaviour. Crosstalk also affects mutual inductance as well as inter-wire capacitance. In multi-conductor system, crosstalk can change the performance of the transmission line by modifying the effective characteristic impedance, capacitance and propagation velocity. Crosstalk can induce noise on the other line and hence degrades the signal integrity and reduce the noise margins.

Figure 2. Crosstalk Overview

C. Odd Mode When two coupled transmission lines are driven with

voltages of equal magnitude but in out of phase with each other, odd mode of propagation occurs. Potential difference between the conductors lead to an increase in the effective capacitance equal to the twice of the mutual capacitance. Because currents are flowing in opposite directions [9], the total inductance is reduced by the amount equal to the mutual inductance (Lm)

Figure 3. A Two Parallel Transmission Line Model

Figure 4. Magnetic Field in Odd Mode

Figure 5. Electric Field in Odd Mode

Figure 6. Crosstalk Overview for Odd Mode

D. Even Mode When two coupled transmission lines are driven with

voltages of equal magnitude and in phase with each other, even mode propagation occurs. Since the conductors are always at an equal potential, the effective capacitance is reduced by the mutual capacitance.

Figure 7. Electric Field in Even Mode

Figure 8. Magnetic Field in Even Mode

Because the currents are flowing in the same direction [9], the total inductance is increased by the amount equal to the mutual inductance (Lm)

Figure 9. Crosstalk Overview for Even Mode

III. PROPOSED BANDWIDTH MODEL

A. Difference Equation Approach The frequency domain difference approximation [10]

procedure is more general, because it can directly handle lines with arbitrary frequency dependent parameters. The time domain difference approximation procedure should be employed only if the transient characteristics are available. For a single RLCG line, the analytical expressions are obtained for the transient characteristics and limiting values for all the modules of the system and device models. The difference approximation procedure is applied to both the characteristic admittances and propagation functions and the resulting time domain device models have the same form as that of the frequency domain models.

B. Modelling the Bandwidth Let us first consider the interconnect system as shown in

Figure 10 and it is assumed here that the length of the transmission line is d.

Here,

R = Series resistance per unit length L = Series inductance per unit length C = Shunt capacitance per unit length G = Shunt conductance per unit length M = Mutual inductance per unit length Cc = Coupling capacitance per unit length

xΔ = Incremental length of the transmission line ( )txI ,1 and ( )txI ,2 are the currents through the aggressor

and victim line respectively. ( )txV ,1 and ( )txV ,2 are the voltages applied to the aggressor and victim line respectively.

Using Kirchoff’s Voltage Law (KVL), we can write,

( ) ( ) ( ) ( ) ( )

( ) ( ) ( ) ( ) ( )⎪⎪⎭

⎪⎪⎬

⎫

Δ++∂

∂Δ+∂

∂Δ+Δ=

Δ++∂

∂Δ+∂

∂Δ+Δ=

txxVt

txixMt

txixLtxxiRtxV

txxVt

txixMt

txixLtxxiRtxV

,,,,,

,,,,,

212

22

121

11 (3)

And using Kirchoff’s Current Law (KCL), we can write,

( ) ( ) ( ) ( ) ( )( ) ( )

( ) ( ) ( ) ( ) ( )( ) ( )⎪⎪⎭

⎪⎪⎬

⎫

Δ++∂

Δ+−Δ+∂Δ+∂

Δ+∂Δ+Δ+Δ=

Δ++∂

Δ+−Δ+∂Δ+∂

Δ+∂Δ+Δ+Δ=

txxIt

txxVtxxVxCt

txxVxCtxxxVGtxI

txxIt

txxVtxxVxCt

txxVxCtxxxVGtxI

c

c

,,,,,,

,,,,,,

2122

22

1211

11

(4)

Thus, when Δ x approaches to zero, we get, ( ) ( ) ( ) ( )

ttxI

Mt

txILtxRI

xtxV

∂∂

+∂

∂+=

∂∂

−,,

,, 21

11 (5)

( ) ( ) ( ) ( )t

txIMt

txILtxRIx

txV∂

∂+∂

∂+=∂

∂− ,,,, 122

2 (6)

( ) ( ) ( ) ( ) ( )( )t

txVtxVCt

txVCtxGVx

txIc ∂

−∂+∂

∂+=∂

∂− ,,,,, 2111

1 (7)

( ) ( ) ( ) ( ) ( )( )t

txVtxVCt

txVCtxGVx

txIc ∂

−∂+∂

∂+=∂

∂− ,,,,, 1222

2 (8)

Taking Laplace transform on the both sides of (5) to (8), we get,

( ) ( ) ( ) ( )xsMIxIsLRx

xV21

1 ++=∂

∂− (9)

( ) ( ) ( ) ( )xsMIxIsLRx

xV12

2 ++=∂

∂− (10)

( ) ( ) ( ) ( )xVsCxVsCGxxI

c 211 ++=∂

∂− (11)

( ) ( ) ( ) ( )xVsCxVsCGxxI

c 122 −+=∂

∂− (12)

Figure 10. Equivalent circuit of each uniform section

Now, taking the derivative of (9) to (12) with respect to x, we get,

( ) ( ) ( )[ ] ( ) ( ) ( )[ ] ( )xVsLRsCsCGsMxVMCssCGsCRx

xVcc 21

22

12

+−++−++=∂

∂ (13)

( ) ( ) ( )[ ] ( ) ( ) ( )[ ] ( )xVsLRsCsCGsMxVMCssCGsCRx

xVcc 12

22

22

+−++−++=∂

∂ (14)

( ) ( )( )[ ] ( )( ) ( )[ ] ( )xIsLRsCsCGsM

xIMCssCGsLRx

xI

c

c

2

12

21

2

+−+

+−++=∂

∂ (15)

( ) ( ) ( )[ ] ( )( ) ( )[ ] ( )xIsLRsCsCGsM

xIMCssCGsLRx

xI

c

c

1

22

22

2

+−+

+−++=∂

∂ (16)

The general solutions of (13) to (16) are, respectively, given as,

( ) ( )xxxx ooee eAeAeAeAV γγγγ43211 +++= −− (17)

( ) ( )xxxx ooee eAeAeAeAV γγγγ43212 +−+= −− (18)

( ) ( )xx

o

xx

e

ooee eAeAZ

eAeAZ

I γγγγ43

021

01

11 −+−= −− (19)

( ) ( )xx

o

xx

e

ooee eAeAZ

eAeAZ

I γγγγ43

021

02

11 −−−= −− (20)

Where, ( )( ) ( )( )ce CCsGMLsR −+++= γ (21) ( )( ) ( )( )co CCsGMLsR ++−+= γ (22)

( )( ) ( )( )ce

CCsGMLsRZ

−+++= 1

0

(23)

( )( ) ( )( )co

CCsGMLsRZ

++−+= 1

0

(24)

Here, γe and γo are even mode and odd mode propagation constants, respectively and Z0e and Z0o are even and odd mode characteristics impedance, respectively. Two coupled interconnects have been considered where one line is switching and other is quiet. The driver for the active line is replaced by a voltage ramp input in series with a Thevenin resistance RS. For the quiet line, the driver has been modelled as a linear resistance RV connected to ground. Receivers at the far end of the lines are modelled as lumped capacitive loads. From a transmission line point of view, a small capacitive load at far-end of the line represents large termination impedance.

This impedance is significantly higher compared to the characteristic line impedance.

Figure 11. Coupled Line Configuration

As a result, the far-end reflection co-efficient in practical interconnects is around +1. This implies that any forward travelling wave is completely reflected at the far-end and the voltage at the far-end of the line is doubled due to the superposition of the incident voltage wave and the reflected reverse wave. So the amplitude of the reflected wave can be set equal to the incident wave and the solution of (17) to (20) can be written, respectively, as,

( ) ( )xxxx ooee eeAeeAV γγγγ +++= −−311 (25)

( ) ( )xxxx ooee eeAeeAV γγγγ +−+= −−312 (26)

( ) ( )xx

o

xx

e

ooee eeZAee

ZAI γγγγ −⎟⎟

⎠

⎞⎜⎜⎝

⎛+−⎟⎟

⎠

⎞⎜⎜⎝

⎛= −−

0

3

0

11

(27)

( ) ( )xx

o

xx

e

ooee eeZAee

ZAI γγγγ −⎟⎟

⎠

⎞⎜⎜⎝

⎛−−⎟⎟

⎠

⎞⎜⎜⎝

⎛= −−

0

3

0

12

(28)

At x=0, the active line is driven by Vin through RS and victim line is connected to ground through RV. So applying boundary conditions to (25) to (28), RS and RV can be written as,

( )( )

( )

oe

ininS

ZA

ZA

AAVxI

xVVR

0

2

0

1

31

1

1

00

+

+−==

=−= (29)

( )( )

( )

oe

V

ZA

ZA

AAxIxVR

0

2

0

1

31

2

2

00

−

+−===−−=

(30)

Solving (29) and (30), we get, ( ) ( )

( )( ) ( )( )( )sovevose

voein RZRZRZRZ

RZZVdxA

++++++

==0000

001

(31)

( ) ( )( )( ) ( )( )( )sovevose

veoin RZRZRZRZ

RZZVdxA

++++++

==0000

002

(32)

At x=d from (25) and (26), we get, ( ) ( ) ( )dddd ooee eeAeeAdxV γγγγ +++== −−

311 (33) ( ) ( ) ( )dddd ooee eeAeeAdxV γγγγ +−+== −−

312 (34) Now, from Figure 3, V2(x=0) = 0 Therefore, A1 = A3 (35) So, V1(x=0) = Vin = 4A1 (36) Therefore,

( ) ( ) ( )( )ddddin ooee eeeeVdxV γγγγ +−+== −−

42 (37)

From (37), we can write,

( ) ( )[ ]ddVdxV oein γγ cosh cosh2

)(2 −== (38)

Or, ⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+

+⎟⎠⎞

⎜⎝⎛

−+−⎟⎟

⎠

⎞⎜⎜⎝

⎛−

+⎟⎠⎞

⎜⎝⎛

++=

CCin CCGs

MLRs

CCGs

MLRs

sVsV

21

)()(2 (39)

Substituting s=jω in (39), we get,

( )( )

( )( )⎥⎦⎤

+−−⎟⎟

⎠

⎞⎜⎜⎝

⎛−

++

−+

−++

⎢⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛+

++

+−=

CC

CC

CCMLRG

MLR

CCGj

CCMLRG

MLR

CCGjjH

ωω

ωωω

2

2

21)( (40)

Simplifying (40), we get,

( )( )( )

( ) ( )( )( ) ⎥

⎥⎦

⎤

⎭⎬⎫

⎩⎨⎧

−−−−−+⎢

⎣

⎡

−−−= 2222

2222

2222)(MLCC

CCRMMLGCjCCML

MCLCRGjHC

CC

C

C ωω(41)

The modulus of (41) is given by, ( ) ( ) ( )( )

( )( )⎟⎟⎠⎞

⎜⎜⎝

⎛

−−×

⎥⎦⎤

⎢⎣⎡ −−−+−=

2222

222222222

1

)(

C

CCC

CCML

CCRMMLGCMCLCGRjH ωω (42)

Equating (42) to2

1 , we get,

( ) ( ) ( )

( )( )⎟⎟⎠⎞

⎜⎜⎝

⎛

−−×

⎥⎦

⎤⎢⎣

⎡−−−+−=

2222

222222222

1

21

C

CCC

CCML

CCRMMLGCMCLCGR ω (43)

Squaring both sides of (43), we get, ( ) ( ) ( )( )

( ) ( )222222

222222222

21

C

CCC

CCML

CCRMMLGCMCLCGR

−−

−−−+−= ω (44)

Solving (44) forω , it can be written as, ( ) ( ) ( )

( ) ( )( )2222

222222222

2

2

CC

CC

CCRMMLGC

MCLCGRCCML

−−−

−−−−=ω (45)

From (45), the 3-dB frequency can be written as, ( ) ( ) ( )

( ) ( )( )2222

222222222

222

CC

CC

CCRMMLGCMCLCGRCCML

f−−−

−−−−=

π (46)

The above equation (46) is the proposed closed form bandwidth expression for the distributed RLCG interconnects line in the presence of both inductive coupling and capacitive coupling.

IV. SIMULATION RESULTS The circuit considered for SPICE simulation is shown in

Figure 3. The aggressor line is excited by a 1-V step voltage. The length of the transmission line is 10mm. Other distributed parameters are given in Table 1. In the Table 2, the calculated bandwidth is shown for different values of operating frequency, when the values of source resistance and load capacitance are kept constant. The experimental values of bandwidth are compared with the SPICE simulation result. The maximum error is coming as 17.95% and the minimum error is coming as 12.3%. So the results obtained by using the proposed model are at good accuracy with that of the SPICE results.

TABLE II. BANDWIDTH FOR DIFFERENT VALUES OF OPERATING FREQUENCY

Operating Frequency(GHz)

G(S) BW(MHz) (Proposed

Model)

BW(MHz) (SPICE)

% of error

5 0.075 49.78 56.76 12.3% 10 0.15 99.57 121.36 17.95% 15 0.225 149.35 177.78 15.99% 20 0.3 199.13 236.28 15.72% 25 0.375 248.91 291.08 14.49% 30 0.45 298.7 351.47 15.01%

V. CONCLUSIONS This paper adopted a 2-line distributed RLCG transmission

line model of interconnects. In this paper, a closed form expression of bandwidth has been modelled considering both the effects of mutual inductance as well as cross-coupling capacitance. Simulation results show the accuracy and validity of the proposed method. The average error is coming as 15.24%. The proposed method may be considered as a convenient and accurate tool for the bandwidth calculation for the pre-layout phase of the IC design process.

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