[ieee 2011 international conference on electronics, communications and control (icecc) - ningbo,...

Wilkinson Splitter Design for LTE Applications Based on Hi-Q Silicon Technology

Lihuan Huang, Falin Liu Department of Electronic Engineering and Information Science University of Science and Technology of China, Hefei, China

[email protected], [email protected]

Abstract —This paper presents a new design of a small integrated passive device (IPD)——Wilkinson splitter——for China TD-LTE band application. The splitter was designed and simulated in On-Semi Hi-Q technology and was realized in similar CMOS process. Measurement results agree quite well with simulation. This new type of splitter has a very small size and a much smaller thickness than its counterpart using LTCC design.

Keywords-IPD; High-Q Inductor; Wilkinson Splitter;

I. INTRODUCTION Long Term Evolution (LTE) technology has become the

winner of the competition in the fourth generation communication system, and has developed rapidly these years. Different from the 700 MHz FD-LTE system widely used in Europe and USA, the LTE system in China is based on TDD system and operated at Band 38, which is defined by 3GPP and located at 2570-2620 MHz.

Wilkinson dividers and hybrid rings are widely used in microwave and RF systems, mainly in microstrip circuits, as power dividers and combiners. The power splitters generally employ quarter-wave transmission line sections at the design center frequency, which leads to unrealistic dimension in the TD-LTE RF applications. There are two ways to reduce the size of the transmission lines, one is to use folded lines, but the device area is still too large. The other way is to adopt the lumped-element components. The lumped-element approach is more suitable in MMIC application. For the Hi-Q Silicon technology used in this paper, using lumped-element equivalent circuit to replace the transmission lines will greatly reduce the size of the layout area and also reduce the fabrication cost of the device.

II. LUMPED-ELEMENT SPLITTER DESIGN Wilkinson splitter is a kind of microstrip splitter. Compared

with T-junction and resistive power divider, Wilkinson splitter is a lossy three port network, and can be matched at all ports. Furthermore, both the output ports can be isolated [1]. Wilkinson splitter has smaller size, so it is widely used in microwave and RF systems.

A. Wilkinson Splitter Property Fig. 1 shows the layout of a classical microstrip Wilkinson

power splitter. The splitter consists of two /4 transmission lines and one resistor between the two output ports. The resistor can absorb any possible reflecting waves, when the output ports are unmatched, so the two output ports are isolated. The S parameters of the Wilkinson splitter are given by the following equation.

0 1 1

j 1 0 02 1 0 0

S−=

(1)

The matching condition is14

l λ= , 02lZ Z= , 02R Z= .

Figure 1. Microstrip Wilkinson splitter layout.

B. Equivalent Network of Transmission Line It is well known that a /4 transmission line can be

represented by a “Tee” or “Pi” lumped-element equivalent networks. In particular, a quarter-wave line can be replaced by a “Pi” LC network as shown in Fig. 2 [2]. The element inductance and capacitance values are given by

02

lZL

fπ=

0

12l

CZ fπ

= (2)

2393978-1-4577-0321-8/11/$26.00 ©2011 IEEE

Figure 2. Transmission line’s equivalent network.

C. Lumped-Element Splitter Network By replacing both /4 transmission line sections with

equivalent Pi LC networks, it is possible to get a lumped-element version of the Wilkinson splitter, as shown in Fig. 3.

Theoretically, the Pi LC network is best equivalent to the /4 transmission line only at the center frequency, and the

expected performance (insertion loss, return loss, isolation, etc.) should be similar for a narrow bandwidth of the center frequency, but it is wide enough for most applications [3].

At the center frequency of TD-LTE band 2.6GHz, using (1) and (2), we get 02 70.7lZ Z= = Ω , 02 100R Z= = Ω , C=0.866 pF, L=4.33nH.

Figure 3. Lumped-element Wilkinson splitter network.

D. Large On-chip Inductor Design The inductance value of the lumped-element network the

previous section is quite large. Usually the stacked spiral inductor is used to realize large inductance with small area, shown as Fig. 4 [4].

Figure 4. Stacked spiral inductor.

III. ON-CHIP HI-Q INDUCTOR TECHNOLOGY

A. -Semi Hi-Q Silicon Cu Technology We can use the CMOS process based on silicon substrate to

realize the lumped-element splitter for smaller size and better thickness, but the low resistivity silicon substrate in traditional CMOS process causes substantial transmission-line losses and large parasitic capacitance.

Some Silicon substrate IPD process technologies have been developed to solve the substrate problem. On-Semiconductor Company has developed a kind of Hi-Q Silicon Cu Technology, and its characteristics are shown in table I. The fabrication process uses HRS substrate to reduce the loss and use 5μm thickness copper lines to realize the Hi-Q inductor.

TABLE I. ON-SEMI HI-Q TECHNOLOGY CHARACTERISTICS

Process Characteristics

Si HRS Substrate 1.5 k ·cm MIM Operation Voltage 20 V

MIM Capacitance density 0.62 fF/μm² M1 Al Metal

thickness 2 μm

Resistor sheet Resistance 9 /square MN Cu Metal

Thickness 5 μm

Inductor Sheet Resistance

3.5 m /square

MN2 Cu Metal Thickness 5 μm

Base Si Oxide Thickness 5.6 μm Bond Pad Wirebond,

Flipchip The On-Semi IPD’s cross-sectional structure is shown in

Fig. 5. Two MN layers made by copper are used to realize the Hi-Q inductor, and the Metal-Insulator-Metal (MIM) capacitor is made between MC and M1 layers. The thin-film metal resistor is made between M1 and RM layer [5] [6].

Figure 5. On-Semi IPD Cross-Section.

B. WLCSP/RDL Advanced Packaging Technology We can also use Wafer Level Chip Scale Package (WLCSP)

technology to realize the Large Hi-Q inductor on Silicon substrate. WLCSP/RDL structure is shown in Fig. 6. In the packaging process, 5-8 μm thick Cu lines are made on the 8-10 μm thick dielectric layers which are usually made of Polyimide. The Cu lines can be used for connections between pads, transmission lines, and spiral inductors.

Compared with On-Semi Silicon-Cu Technology, the WLCSP technology is made in packaging process, and has limitations with regard to line width and via size. But it is quite essential to establish a connection from the center of the spiral inductor [7].

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Figure 6. Structure of WLCSP/RDL .

IV. SIMULATION AND MEASUREMENT RESULTS We use Advance Design System (ADS) software for the

simulator of the schematics and layout circuits.

A. ADS Schematics Circuit Simulation We established the lumped-element equivalent schematics

circuits in ADS as shown in Fig. 7. The simulator of S parameter is set from 0.5-5 GHz, and the operating center frequency of the splitter is set to 2.6 GHz. The lumped components values are 02 100R Z= = Ω , C=0.866 pF, L=4.33nH.

Adding Q factors to the LC equivalent networks, we can obtain the performance of the splitter in schematic circuit level as shown in Figure 8. Here the capacitor Q factor is set to 100 and the inductor Q factor is set to 30.

Figure 7. ADS schematic simulation circuit of Lumped-element Wilkinson splitter.

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50.5 5.0

-30

-25

-20

-15

-10

-5

-35

0

freq, GHz

dB(S

(2,1

))

m1m2

dB(S

(3,1

))dB

(S(3

,2))

m5

m6

m1freq=dB(S(2,1))=-3.386

2.650GHzm2freq=dB(S(2,1))=-3.372

2.500GHz

m5freq=dB(S(3,2))=-27.834

2.500GHz

m6freq=dB(S(3,2))=-32.712

2.650GHz

Figure 8. The simulation results of Wilkinson splitter schematics circuits in ADS.

B. ADS Layout Design and Simulations Results We then made the layout design of On-chip spiral inductors

as shown in Fig. 9. The inductor consists of two layers of copper line with 30μm line width, and the thickness of the copper line is 5μm. Using Hi-resistor silicon substrate and simulating in ADS momentum simulator, the results of the inductance and Q factors are shown in Fig. 10. The Q factor of the inductor is over 40 at operating bandwidth, which is good enough for Silicon substrate device.

Figure 9. Large inductor layout design.

m2freq=L=4.333

2.500GHzm6freq=L=4.377

2.650GHz

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50.5 5.0

4.5

5.0

5.5

4.0

6.0

freq, GHz

L

m2m6

m2freq=L=4.333

2.500GHzm6freq=L=4.377

2.650GHz m1freq=Q=40.943

2.500GHzm5freq=Q=41.373

2.650GHz

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50.5 5.0

20

25

30

35

40

15

45

freq, GHz

Q

m1m5

m1freq=Q=40.943

2.500GHzm5freq=Q=41.373

2.650GHz

Figure 10. The inductance and Q factor of the large inductor

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.50.5 5.0

-40

-35

-30

-25

-20

-15

-10

-5

-45

0

freq, GHz

dB(S

(2,1

))

m1m2

dB(S

(3,1

))dB

(S(3

,2))

m4

m5

m1freq=dB(S(2,1))=-3.503

2.500GHzm2freq=dB(S(2,1))=-3.542

2.650GHz

m4freq=dB(S(3,2))=-28.861

2.500GHzm5freq=dB(S(3,2))=-33.509

2.650GHz

Figure 11. The simulation results of the Wilkinson splitter layout design.

By adding MIM capacitors and thin-film metal resistors which are defined by On-Semi Hi-Q technology process and combining with the large inductor shown previously, the final splitter layout design is about 1000x700μm in area, the simulation results are shown in Fig. 11. The insertion loss of the splitter is about 0.5 dB and the isolation is over 28 dB in operating bandwidth.

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C. Measurement Results The Wilkinson splitter is realized as flipchip components

and assembled to the test board as shown in Fig. 12 and 13. The splitter layout design is made in CMOS process on Hi-resistor Silicon substrate which is similar to the On-Semi Hi-Q process. The On-chip Inductor consists of one Al line layer which is made in semiconductor fabrication process and one Cu line layer which is made in WLCSP process, and the inductor Q factor is a little lower than the On-Semi Hi-Q process which will slightly increase the insertion loss.

The comparison of the measurement and the simulation results is shown in Fig. 14 and 15. The insertion loss results met quite well in Fig. 14. The isolation results of the output ports have some difference which might be mainly due to the parasitic capacitance when connected the MIM capacitors to the test probe’s ground pin.

Figure 12. Flipchip components assembly demonstration.

Figure 13. On-Wafer Test version Wilkinson splitter.

Figure 14. Comparison of the insertion between measurement and simulation.

Figure 15. Comparison of the isolation between measurement and simulation.

V. CONCLUSIONS This paper has proposed a new design of a lumped-element

Wilkinson splitter suitable for TD-LTE band application. A 3dB Wilkinson splitter as well as their lumped equivalent circuits is simulated using the ADS simulator. The splitter was realized using Hi-Q silicon technology and the measurements met the simulation results quite well. The final layout structure is quite small and simple and can be easily integrated into MCM front-end modules or fabricated as discrete components.

ACKNOWLEDGMENT The authors would like to thank Sychip Shanghai RF team

staff for their assistance, and also thank Prof. Yinchao Chen of the University of South Carolina for his direction of components design.

REFERENCES [1] David M.Pozar, Microwave Engineering Third Edition, Publishing

House of Electronics Industry, 2006. [2] Yonggang Zhou and Yinchao Chen, “Lumped-element equivalent circuit

models for distributed microwave directional couplers,” IEEE Microwave and Millimeter Wave Technology, ICMMT, vol.1, pp.131-134, April 2008.

[3] Fernando Noriega, Pedro J.Gonzalez, “Design LC Wilkinson power splitters,” RF Design, vol.25 (8), pp18~24, 2002,

[4] A.Zolfaghari, A.Chan and B.Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J.Solid-State Circuits, vol. 36, pp.620-628, April 2001.

[5] Ian Robertson, Stepan Lucyszyn, RFIC and MMIC Design and Technology, Publishing House of Electronics Industry, 2007.

[6] On Semiconductor, IPD technology High-Q Intergrated Passive Device, From On Semiconductor website: www.onsemi.com.

[7] Yeong J. Yoon, Yicheng Lu , Rober C. Frye, Maureen Y. Lau, Peter R. Smith, Lou Ahlquist, and Dean P. Kossives, “Design and characterization of multilayer spiral transmission-line baluns.” IEEE Trans. on Microw. Theory and Tech., vol.47, No.9, pp.1841-1847, September 1999.

m25freq=dB(PDV2G451005AJF_sch..S(2,3))=-17.023

2.400GHz


2.550GHz


2.700GHz

m28freq=dB(DeEmbd_PDV_JO182_181_180..S(5,6))=-21.000

2.400GHz


2.550GHz


2.700GHz

2 40 5

-30

-20

-10

-40

0

freq, GHz

dB(P

DV

2G45

1005

AJF

_sch

..S(2

,3))

m25m26m27

dB(D

eEm

bd_P

DV

_JO

182_

181_

180.

.S(5

,6))

m28m29

m30


2.400GHz


2.550GHz


2.700GHz


2.400GHz


2.550GHz


2.700GHz

Simulation (Red) Measurement (Blue)


2.400GHz


2.550GHz


2.700GHz


2.400GHz


2.550GHz


2.700GHz

2 40 5

-25

-20

-15

-10

-5

-30

0

freq, GHz

dB(P

DV

2G45

1005

AJF

_sch

..S(1

,2))

m31m32m33

dB(D

eEm

bd_P

DV

_JO

182_

181_

180.

.S(1

,2))

m34m35m36


2.400GHz


2.550GHz


2.700GHz


2.400GHz


2.550GHz


2.700GHz

Simulation (Red) Measurement (Blue)

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