Implementation of EPON Systems Supporting Accurate Time Synchronization

Zhen Wang, Mei Wang, Ke He, Xue Chen

Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, Beijing, 100876, China

yuchen5098@bupt.edu.cn,wangmeihainan@163.com freshx61@gmail.com,xuechen@bupt.edu.cn

Abstract- In this paper factors affecting accuracy of

time synchronization in EPON are analysed and the

scheme of time synchronization in EPON based on

IEEE1588v2 protocol is designed and implemented by

FPGA. Experimental result shows that the scheme is

feasible and good time synchronization accuracy about

20 nanoseconds can be reached. Key words: EPON, IEEE1588v2, time

synchronization, FPGA

I．Introduction When access networks are applied as backhaul

networks from cell site to mobile switching center, time synchronization is usually required to be provided [1][2]. Ethernet Passive Optical Network (EPON), as a suitable backhaul from cell site to mobile switching center, doesn’t have an inborn accurate time synchronization scheme.

There have been studies [3][4] about clock synchronization schemes, but implementing a low-cost accurate time synchronization scheme still cause great interest to people. In order to support accurate time synchronization in EPON, we propose a scheme based on a precision time protocol known as IEEE1588v2. We analyze several factors which affect time synchronization performance, such as dynamic bandwidth allocation and message transmission interval. We designed an EPON system based on FPGA including IEEE1588v2 function modules and prove that the time synchronization scheme is feasible and good time synchronization accuracy about 20 nanoseconds can be reached through experiment.

II. The time synchronization scheme In order to achieve a low-cost accurate time

synchronization scheme in EPON, we propose an idea of supporting a precision time protocol as IEEE1588v2 through a special service with high quality of service (QOS) requirement which is processed in OLT and ONU’s hardware. We use Master and Slave to stand for the function modules in OLT and ONU which deal with clock management, generate and process the packets used by IEEE1588v2 protocol. The Master gets its real time clock from a parent clock reference and the Slave delivers its synchronized clock from Master’s clock

to wireless nodes connected to it through certain interfaces, such as 1PPS. The scheme is shown in Fig. 1.

Fig.1. the time synchronization scheme In order to analyze the factors which affect the

time accuracy, an IEEE1588v2 interaction process is shown in Fig. 2. At first the Master transmits the sync message and at 2sT the Slave receives the message. Then the Master transmits a follow up message indicating the exact transmitting time

1mT of the sync message. At 3sT the Slave sends out a Delay-Req message to the Master and the time of receipt is 4mT . Then the Master transmits a

Delay-Req response message indicating 4mT and

the Slave receives it at 6sT . The formulas computing difference between the Master and Slave’s clocks could be obtained as follows:

2 1 _s mT T O f f s e t M S D e la y− = + (1)

4 3 _m sT T O ffse t SM D elay− = − + (2) Where Offset stands for the time difference between the master and slave, MS_Delay stands for the line delay from the master to the slave and SM_Delay stands for the line delay from the slave to the master. Here we assume the MS_Delay and SM_Delay are equal and Offset is a constant. Thus from the two Formulas above, Offset could be computed as:

2 1 4 3[( ) ( ) ] / 2s m m sO ffse t T T T T= − − − (3)

2011 Third International Conference on Communications and Mobile Computing

978-0-7695-4357-4/11 $26.00 © 2011 IEEE

DOI 10.1109/CMC.2011.56

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Fig.2. IEEE1588v2 process

When the line delays are asymmetric and there is frequency difference between the master and slave, Offset is no longer a constant. In order to get the actual Offset, we introduce sjT which stands for the time difference between the master and slave. Let ( ) /sm s m mf f f fΔ = − stand for the frequency difference between the master and slave, 'Offset stand for actual offset, then we could get the following formula:

6 2 1 4 3

3 2

5 4

' ( ) [( ) ( )]/ 2( _ _ ) / 2 [ /(1 )]( ) / 2 ( _ _ )

( )

s s m m s

sm sm

s s sm

sm m m

Offset Offset T T T T TMS Delay SM Delay f fT T f MS Delay SM Delayf T T

= = − − − −− + Δ + Δ ×

− + Δ × + +Δ × −

(4)

Where ( _ _ ) / 2MS Delay SM Delay− stands for the asymmetric line delay’s effect and the following items stand for time deviation caused by frequency offset.

From (4) we could see that the difference between Offset’ and Offset is:

3 2

5 4

' ( _ _ )/2[ /(1 )] ( )/2( _ _ ) ( )

sm sm s s sm

sm m m

Offset Offset MS Delay SM Delayf f T T fMS Delay SM Delay f T T

− =− −+ Δ +Δ × − +Δ× + +Δ × −

(5)

Let smTΔ stand for the maximum time difference between master and slave’s clocks, and Tsync stand for message transmission interval [2]. Then we could get smTΔ in the following formula:

s

3 2

5 4

max( ) max{ _ _ /2[ /(1 ) ( )/2 ( _

_ elay)] ( ) }

msm

s ssm sm sm

m m syncsm sm

T T T MS Delay SM Delayf f T T f MS DelaySM D f T T f T

Δ = − = − +Δ +Δ × − +Δ ×+ +Δ × − +Δ ×

(6)

Let ArΔ stand for the asymmetry of line

delay and fΔ stand for frequency difference, then

we could divide smTΔ into two parts which are

marked by ArΔ and fΔ . Then we could get the

following formulas: Tsm Ar fΔ = Δ + Δ (7)

max{ _ _ /2}Ar MS Delay SM DelayΔ = − (8)

3 2

5 4 sync

max{ /(1 ) ( ) / 2( _ _ )

( ) }

sm sm s s

sm

sm m m sm

f f f T Tf MS Delay SM Delayf T T f T

Δ = Δ + Δ × − +Δ × ++Δ × − + Δ ×

(9)

From formula (6) we could see that larger Tsync which equals message transmission interval and larger (Ts3-Ts2) which equals processing delay will deteriorate the performance of time accuracy. The value of Tsync is a compromise between the stability and precision of the local clocks and the communication and computation overhead imposed by these messages. From IEEE1588v2 protocol,we know that message transmission interval can range

from 1282 10−× to 1272 10× seconds. Also from

formula (6) we could see that larger (Ts3-Ts2) from receiving sync message to sending Delay_Req message in ONU will deteriorate the performance of time accuracy.

In EPON systems with a DBA strategy, services with lower QoS requirements would experience a larger queue delay. In order to improve time accuracy, not only should the DBA cycle be shorter, but also high priority or fixed bandwidth reservation should be given to IEEE1588 protocol packets.

III. Experiment As shown in Fig. 3, the experiment setup

consists one OLT, two ONUs, a time accuracy analyzer, a 1:2 optical splitter and optical fibers. The OLT, ONU and analyzer are implemented using the same hardware system with 4 optical interfaces running at the line rate of 1.25Gbit/s. This hardware system uses Altera Corporation’s EP2C70F896 FPGA as the main processing unit. The analyzer is connected to OLT and ONU through optical ports to generate pulses to OLT and ONU simultaneously. OLT and ONU capture their own clock counter on the rising edge of these pulses and send captured data to the analyzer for calculating ONU’s clock differences comparing with OLT. The optical fiber connected from the analyzer to OLT and ONU is of the same length to ensure OLT and ONU register their clock timers at the same time. In this experiment, Master Clock and Slave Clock modules in OLT and ONU use a onboard 125Mhz crystal oscillator with a frequency stability of ±30ppm. We measure time accuracy under 5 minute observation length when message transmission interval ranges

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from 102 10−× to 52 10−× seconds and results are shown in Fig. 4. We also measured time accuracy under different DBA periods when the interval is about 15ms and the result show that the differences is less than 20 ns when DBA period ranges from 262us to 2ms.

OLT

ONU-1

ONU-2

Optical Splitter

Optical Fiber

Analyzer

Fig.3. Experiment setup

Fig.4. Time synchronization accuracy

From the results we could see that time accuracy is degraded when message transmission interval increases and reaches more than 100 ns when the interval is about 30 ms. It is consistent with our expectation because Master Clock and Slave Clock are individually oscillated in our experiment system

and frequency offset will be accumulated with time. To get time accuracy to be about 20 ns, a maximum message transmission interval of 5ms should be used and the bandwidth used by IEEE1588v2 will be about 500Kbit/s per ONU, which is tolerable comparing to its merit. This interval limit will be much longer when ONU’s clock frequency is synchronized to OLT.

IV. Conclusion In this paper we analyze the factors affecting a

precision time protocol’s time accuracy. We design and implement an EPON system supporting IEEE1588v2 protocol and experiment results show that good time accuracy about 20 nanoseconds is achieved. So this technique offers a possible solution to achieve low-cost accurate time synchronization in EPON for bearing wireless and other potential services.

Acknowledgement This study is supported by National High

Technology Research and Development Program of China (No.2009AA01A345) and Fundamental Research Funds for the Central Universities (BUPT2009RC0402).

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[3] M. Henderson and T. Shaver,” Sampling Synchronization with Gigabit Ethernet”, OCEANS 2009, pp1-7,2009

[4] Stephen Topliss, Daniel Beeler, and Laurenz Altwegg,” Synchronization for Passive Optical Networks”, Lightwave Technology, Volume: 13 , Issue: 5 ,1995

[5] IEEE Instrumentation and Measurement Society, “IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (IEEE Std 1588-2008)

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