Figure 1: Various data indicating the impact of Ldi/dt

noise on chip voltage drop noise over several technology

nodes: (a) ITRS data tracking change in transient current

versus average current [2], (b) comparison of inductive

noise versus resistive noise [3], and ITRS data tracking

supply voltage against threshold voltage [4].

Chip-Package Power Delivery Network Resonance Analysis and Co-design Using

Time and Frequency Domain Analysis Techniques

Jonathan Watkins1, Jai Pollayil

2, Calvin Chow

2, Aveek Sarkar

2

1Maxim Integrated Products Inc, Dallas, TX USA

2Apache Design Inc, San Jose, CA USA

2E-mail: aveek.sarkar@ansys.com

Abstract Traditional methods of performing worst-case DC or

static analysis serves limited purposes for power delivery

network (PDN) validation, especially when it comes to

modeling chip-package-PCB coupling or resonance

behavior. These methods do not consider the inductive and

capacitive elements that dominate the chip and package

interaction. They also fail to capture the impact of

simultaneous switching current in creating local hot-spots

and global voltage rail collapse. In this study, an analysis

methodology that combines the use of both time and

frequency domain techniques to model the impact of Ldi/dt

noise and the coupling of chip-level switching current with

chip-package impedance is presented. The outlined

techniques were used on a design targeting high-speed signal

processing applications to identify resonance behavior of

chip-package PDN systems. Simulations were performed on

various configurations of the design to ensure that the

proposed design changes would correct the resonance and

other PDN related issues. The analysis flow, information on

the various data used, run-time and performance statistics,

and the results from these experiments are presented.

Keywords PDN verification, DC, static, AC, transient.

1. Introduction The common method of validating on-die (or IC level)

power delivery network (PDN) or power/ground network

routing inadequacies using static or DC simulations is

grossly inefficient, as this technique only models the “IR”

drop component of the PDN and does not capture the

capacitive and inductive elements that increasingly dominate

the ‘noise’ or voltage drop seen in the chip. This noise or

voltage drop comes from a combination of several factors

such as simultaneous switching of several devices, Ldi/dt,

chip-package resonance, and inadequate decoupling

capacitance. None of these effects are modeled by the DC or

static simulation based approaches, which are mostly useful

to identify gross connectivity issues with the PDN, or for

‘average’ electro-migration (EM) or reliability verification.

Some recent studies are pointing to the importance of

modeling the Ldi/dt component of PDN noise [1]. As seen in

figure 1 (a), the level of transient (or di/dt) current in an IC

fabricated using advanced technology nodes continues to

increase compared to average current. The combined effect

of package and chip L and heightened di/dt, results in

increased Ldi/dt or inductive noise as seen in figure 1 (b).

However, the noise margin in an IC continues to fall as the

supply voltage is scaled down from power consumption or

reliability concerns (figure 1 (c)). So the impact of increased

noise and reduced noise margin can result in chip failures or

reduced performance, unless extensive pre-silicon

simulations are performed to model these parasitic elements

present in the chip, and the package, and the switching

current coming from the simultaneous switching of devices.

978-1-4673-1036-9/12/$31.00 ©2012 IEEE 520 13th Int'l Symposium on Quality Electronic Design

Figure 2: The RedHawk analysis flow for DC, time-

domain and frequency domain analysis.

Thus, accurate estimation and prediction of voltage drop in

the chip is of considerable importance for high-performance

and for low-power designs. On-die voltage drop analysis is

incomplete if the system in which the chip operates is not

considered in the simulation through the incorporation of the

package and PCB parasitics. The package parasitics, along

with the chip capacitance, determine the rate of current

supply to the switching devices and the drop through the

package. To model and predict the impact of the package

parasitics on the chip-level noise, both time and frequency

domain analyses are required.

Time domain analysis is used at a microscopic level to

predict voltage drop seen in individual devices as they

switch to perform their logic operations. It must be

performed at the full-chip level along with the package

parasitics to model as unlike timing and cross-talk; voltage

drop analysis cannot be partitioned, and has to be done

holistically in order to capture the impact of simultaneous

switching across the chip, as various parts of the chip turn on

and off over time. Also, since the package parasitics affect

the entire chip it cannot be partitioned, and must be included

in entirety in this time domain analysis. However, time

domain analysis that models an entire IC in considerable

detail along with the package parasitics, can become

computationally intensive and prohibitive unless appropriate

modeling assumptions are made, which while allowing for

full-chip simulation capacity does not compromise the

accuracy and quality of the results. Frequency domain

analysis on the other hand is more macroscopic in scope. It

is helpful to understand the various resonance frequency

points of the chip and its package and PCB. When taken in

conjunction with the frequency distribution of the chip’s

switching noise, it can help identify potential resonance

conditions that can cause significant voltage rail collapse in

the chip.

In this study, a methodology using a combination of

time and frequency domain simulations to solve chip-

package PDN design needs is presented. This methodology

was applied on a design targeting high-speed signal

processing applications. It was used to predict a resonance

condition in the chip-package system, and to predict voltage

drop noise that closely matched what was seen on the

fabricated parts of the design. It was also used to predict

whether the changes in the design helped to address the

resonance condition. In addition to identifying the chip-

package coupling issue, time domain simulations were used

to highlight areas of weaknesses in the PDN routing

exacerbated by the simultaneous switching of devices that

were connected to weak PDN routings. The proposed

methodology relies on data in industry-standard formats. For

the full-chip time domain simulations, RedHawk™ was

used. The time domain simulations included the entire chip

layout along with the parasitic model of the package.The

performance for RedHawk based full-chip level time domain

simulations done for multiple clock periods at a time-step of

20ps, was about 5 hours on a 32GB machine. For the

frequency domain simulations, first a Chip Power Model

(CPM™) of the chip was created [5]. A CPM captures the

switching current and the various parasitic elements present

in a chip. It reduces chip-level detailed information into a

compact Spice-format based model that can be simulated

along with the model of the package using Spice.

2. Analysis Flow Figure 2 illustrates the RedHawk analysis flow for

performing full-chip level time-domain analysis leading to

the creation of a CPM, which can then be used for a chip-

aware package-level analysis in the frequency domain.

RedHawk uses a cell-based simulation framework. First

electrical models of individual cells capturing their switching

current and the parasitics are created using a library

characterization step called Apache Power Library (APL).

This step creates views of the standard cells, memories, I/Os

and intentional decap cells that include their switching

current signature (if any) for various input slope, output

load, supply voltage and input stimuli conditions. The APL

for every cell, along with their LEF views allow RedHawk to

perform the full-chip simulation at a higher level of

abstraction while providing transistor-level accuracy [6].

The layout of the chip that includes information on the

power/ground routings, placement of individual cells

including decoupling cells, and their connection to each

other and to these power/ground routings, is provided using

a DEF file of the design. RedHawk uses the routing

information provided in the DEF file along with technology

parameters such as rho, dilelectic coffecient, etc. to extract

the power/ground network RLC parasitics. The package

parasitics are included in the RLGC format and connect at

every power/ground pad of the design. The switching

activity was provided using a test bench in the VCD format.

For the initial set of runs, about 500ns of the VCD was

simulated. However, the final simulations were performed

for a reduced set of clock periods (120ns), after the

appropriate clock periods were identified from the initial

simulations. The time-step used for the transient simulation

was 20ps. These time-domain simulations included the full-

Figure 3: The test-design displayed in RedHawk full-

chip dynamic analysis flow.

Figure 4: Self-consistency test for the CPM created for the

chip used for this study. The CPM when simulated with the

package using Spice matches closely with the RedHawk

full-chip time domain simulation done on the original

layout with the same package netlist validating the quality

of the CPM and the reduction technique.

Figure 5: Frequency domain analysis comparing the

resonance frequency of the chip before and after the

addition of decaps on the chip.

chip power/ground parasitics, the package parasitics

provided in the RLGC format, and the switching current and

capacitance from individual cells in the design that had

about 7 million instances (approximately 30 million gates),

and was fabricated using TSMC 65nm technology (shown in

figure 3).

For the frequency domain analysis, first a CPM is

created from the RedHawk simulation. A CPM captures the

electrical properties of the chip PDN, both in terms of its

parasitics (RLC) and its switching current, as seen from the

chip ports at its pad locations [5]. The parasitics include the

power/ground network RLC, device and diffusion

capacitances (from both intentional and intrinsic decoupling

capacitances), and signal wire capacitance. The switching

current reflects the activity on the chip as defined by the

input test-bench or VCD file. A CPM captures this data in a

compact Spice netlist format. Since accuracy of frequency

response is desired for this model, frequency domain based

order methods are deployed for creation of a CPM [5]. The

model also complies to passivity and stability after order

reduction [5,7]. Once a CPM is created, it must be checked

for validity against the original layout from which it is

created. This is done by running a Spice simulation on the

CPM by connecting it to the package netlist, and also by

comparing the current and voltage signatures at the pads

against the corresponding waveforms seen in the full-chip

time domain RedHawk simulation, performed with the same

package netlist. As seen in figure 4, the voltage and the

current waveforms align quite well, indicating that the CPM

is able to capture the electrical properties of the PDN even

though it is a significantly reduced representation of the

complex on-die PDN. Once the CPM is validated, it can be

used for both time and frequency domain analyses of the

package and PCB PDN systems by providing an electrical

model of the chip. The Spice analysis of the CPM along with

the package is typically in the order of minutes, allowing for

experimentation on package and PCB layouts. For this study,

the CPM of the chip was used for frequency domain analysis

to understand the resonance frequency points of the chip-

package PDN.

3. Analysis Results Time domain simulation results from initial

versions of the design indicated significant levels of noise on

the power and ground rails. The VCD that was used for the

analysis had a highly repetitive switching pattern, and the

drop was similar from one clock period to the next. This

high level of drop was seen at the chip supply pads,

suggesting that most of the drop was happening through the

package itself. However, the effective inductance of the

power and ground routing in the package layout was

reasonable, indicating that the package by itself was correct.

A resonance analysis of this package model along with the

CPM of the chip indicated that the resonance frequency was

around 67MHz. At the same time, a frequency domain

profiling of the switching current on the chip indicated that

most of the energy was around 70MHz. Since most of the

Figure 6: Hand calculation indicates that the shift in

resonance frequency matches closely with the additional

decoupling capacitance incorporated in the design.

Figure 7: Time domain current waveform. X-axis is time

while Y-axis is current. Red curve is the “demand

current” which is coming from the switching on the chip.

The yellow curve is the current supplied by the battery in

absence of a package model. The white curve is the

current supplied for revision 1 of the design and blue is

the current supplied for revision 2 of the design.

Figure 8: Time domain voltage drop waveform (VDD-

VSS). Y-axis is VDD-VSS voltage at the chip-package

interface and X-axis is time. Yellow curve is prior to

addition of the on-die decap (red is post decap addition).

The reduced voltage swing in the post-fix database

results from significantly reduced resonance effect in the

chip-package PDN.

switching energy was close to the resonance frequency of the

chip, it was hypothesized that a resonance condition was

reached between this switching pattern and the chip-package

PDN. Since the switching activity was a characteristic of the

logic on the chip and could not be changed, an attempt was

made to shift the resonance frequency itself. This can be

done by either changing the package inductance or the chip

capacitance. For this study, the latter was undertaken. About

70nF of additional decoupling capacitance was added. The

RedHawk full-chip time-domain simulations and the CPM

creation were re-done with this modified design. With the

new CPM, the resonance frequency was seen at 43MHz,

which was further away from the switching energy in the

chip. Figure 5 captures the frequency domain analysis results

before and after the addition of the decaps. Hand calculation

of the resonance frequency shift arising from this decap

addition matched the shift seen in the Spice-based frequency

domain simulation of the CPMs with the package netlists

(figure 6).

The time-domain voltage drop at the pads was reduced

considerably with this modified design. Figure 7 shows the

current waveforms from the time-domain analysis. The red

curve is the “demand current” coming from the switching on

the chip. The yellow curve is the current supplied by the

battery, in absence of a package model. The white curve is

the current supplied for revision 1 of the design and blue is

the current supplied for revision 2 of the design. The current

supplied by the battery tracks the demand current most

closely, when there is no package model in the simulation

due to the lack of inductance in the supply path. The

difference in the red and the yellow curve is due to the

current or charge supplied by on-die decoupling

capacitances. The white curve, which shows the current

supplied to the chip prior to the inclusion of the additional

decaps, highlights the resonance behavior with significant

ringing. The blue curve, which shows the current supplied to

the chip after the inclusion of the additional decaps, shows

significantly diminished ringing. Still, the current supplied

(blue) does not track the demand current (red) as closely,

due to the inductive choking caused by the package

parasitics. Figure 8 shows the time-domain voltage drop

waveform at the pads of the chip before and after the

addition of the extra on-die decoupling capacitance. As seen

in this figure, the post-cap addition waveform (red) is

significantly less drop, compared to the pre-cap addition

waveform (yellow).These predicted noise waveforms

matched the waveforms seen while probing the silicon on the

tester

A comparison was also made for the cell-level voltage

drop for four different conditions: with and without package

for both revisions of the chip (pre- and post-decap addition).

As seen in figure 9, revision 1 of the chip (pre-decap

addition), which exhibitied the resonance behavior with the

package, had the worst instance voltage for the cells in the

design (blue data points). Once the decaps were added and

the resonance condition addressed, the voltage seen at the

cells improved significantly (red data points). For both

revisons of the chip, instance voltage levels were quite

similar when the package model was not included,

suggesting that the chip-package resonance was the main

cause for the high voltage drop situation. However, using the

Figure 9: Histogram comparison of instance voltage

(supply voltage after accounting for voltage drop)

between two revisions of the chip (pre- and post-decap)

addition with and without package models.

same VCD, the static voltage drop on the power and ground

rails was much smaller with a combined drop of 32mV

including 7mV drop through the package. Also as expected,

the static voltage drop numbers did not change from the

addition of the decoupling capacitors. But, the decaps

reduced the power ground noise on the chip significantly by

shifting the resonance frequency point of the chip-package

system from where the chip’s switching energy resided. So a

combination of time and frequency domain analyses was

needed to model the chip-package interaction with the chip

switching current, and to validate a potential fix for the

voltage rail collapse.

4. Conclusions Traditional methods of voltage drop analysis using DC or

static simulations do not model the capacitive and inductive

parasitic elements that are present in the PDN system of the

chip and package. Time and frequency domain simulations

are needed to predict Ldi/dt noise and resonance frequency

of the chip-package-system. In this study, a methodology

using time and frequency domain simulations was used to

identify a chip-package resonance condition in a high-

performance design targeting signal processing applications.

A fix for the design was explored and the results were

compared before and after the repair. The time domain

results were compared against certain measurements and

found to have a good match.

5. References [1]. S. Pant and E. Chiprout, “Power grid physics and

implications for CAD,” Proc. 43rd Annual Conference on

Design Automation, 2006, pp. 199–204.

[2]. ITRS Projections.

[3]. A. Mezhiba and E. Friedman, “Scaling Trends of On-

Chip Power Distribution Noise”, IEEE Transactions on Very

Large Scale Integration (VLSI) Systems, Vol. 12, No. 4,

April 2004, pp. 386-394.

[4]. ITRS Projections.

[5]. E. Kulali, E. Wasserman, and J. Zheng, “Chip power

model - a new methodology for system power integrity

analysis and design,” in Electrical Performance of Electronic

Packaging, 2007 IEEE, Oct. 2007, pp.259 –262.

[6]. A. Sarkar, “Power Noise Analysis for Next Generation

IC’s”, Apache Design Inc White Paper.

[7]. K. Kerns and A. Yang, “Preservation of passivity during

RLC network reduction via split congruence

transformations,” Computer-Aided Design of Integrated

Circuits and Systems, IEEE Transactions on, vol. 17, no. 7,

Jul 1998, pp. 582 –591.