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SCALING EFFECTS ON THE GATE CAPACITANCE OF GRAPHENE NANORIBBON TRANSISTORS

George S. Kliros

Hellenic Air-Force Academy, Department of Electronics and Communication Engineering, Dekeleia, Attica GR-1010, Greece.

E-mail: gsksma@hol.gr

Abstract–Scaling effects on the gate capacitance of graphene nanoribbon field-effect transistors (GNR-FETs) are studied by means of a semi-analytical model. The influence of nanoribbon width, gate-insulator thickness and dielectric constant scaling on the capacitance - voltage characteristics is explored. Gate capacitance has non-monotonic behavior with ripples for thin and high-k gate-insulators. However, beyond the quantum capacitance limit, the ripples are suppressed and smooth monotonic characteristics are obtained. Keywords: Graphene nanoribbon transistors, Gate capacitance, Quantum capacitance, Scaling effects.

1. INTRODUCTION

Nowadays, graphene is considered to be a viable alternative to Si for the channel of field-effect transistors (FETs) [1]. In graphene, the charge carriers in the two-dimensional (2D) channel can change from electrons to holes with the application of an electrostatic gate with a minimum density at the charge neutrality point (Dirac point) characterizing the transition. However, the on-current to off-current ratio of graphene channel FETs is very small due to the lack of a bandgap. As a result, monolayer graphene is not directly suitable for digital circuits, but is very promising for analog, high frequency applications [2].

One of the main characteristics of FETs is the capacitance formed between the channel and the gate. The gate capacitance is important for understanding fundamental electronic properties of the material such as the density of states (DOS) as well as device performance including the I-V characteristics and the device operation frequency. Low-dimensional systems, having a small DOS, are not able to accumulate enough charge to completely screen the external field. In order to describe the effect of the electric field penetration through a two-dimensional electron gas (2DEG), Luryi introduced the concept of quantum capacitance [3]. Consequently, the gate

capacitance has to be considered as a series connection of the insulator capacitance Cins and the quantum capacitance CQ [4].

Graphene has an atomically thin body so that its quantum capacitance can dominate the device's electrostatics. Moreover, its density of states is a strong function of Fermi energy and therefore, quantum capacitance can be changed by applying a gate voltage. Interestingly, variable capacitance devices (varactors) based on single semiconducting carbon nanotubes [5] as well as single graphene sheets [6] have been proposed. Recently, the quantum capacitance of a graphene sheet has been measured by several groups [7-9] and good agreement with theory has been found only at large bias far from the Dirac point. However, deviation from theory at small bias has been observed in all measurements. This deviation has been attributed to electron-hole puddles induced by charged impurities [7]. The effect of electron-hole puddle formation on the quantum capacitance of both monolayer and bilayer graphene has also been investigated [10]. In this work, scaling effects on the gate capacitance of graphene nanoribbon field-effect transistors (GNR-FETs) are studied by means of a semi-analytical model which takes into account the presence of electron-hole puddles induced by local potential fluctuations. The influence of nanoribbon width, gate-insulator thickness and dielectric constant scaling on the gate capacitance - voltage characteristics is investigated.

2. THE MODEL

Let us consider a semiconducting graphene nanoribbon of width W<<L, connected to metallic electrodes acting as source/drain (S/D) reservoirs supplying carriers to the nanoribbon. In this top-gate geometry, the GNR is placed on a thick substrate and covered by a second much thinner insulating layer of width tins separating it from the top gate (figures 1(a) and (b)).

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In principle, the band structure of a GNR depends on the properties of its edges [11]. However, recent experiments suggest no clear dependence of the bandgap on the chirality due to the resolution limit of the current patterning techniques. Moreover, edge disorder effectively wipes out any distinction between zigzag and armchair GNRs [11]. Thus, following Ref. [11] a simple relationship for the density of states (DOS) of GNRs can be obtained:

( ) ( )nnF n

Eg E S E Eπ υ E E>

= −−

∑ 20

4h

(1)

where S(Ε) is the unit step function and En are the subband threshold energies whose analytical expressions are given by /n FE nπ υ W= h .

Fig. 1. (a) Schematics of a top-gate transistor where a semiconducting GNR of width W<<L is embedded in a gate-insulator of thickness tins. The GNR is connected to the source (S) and drain (D) reservoirs. (b) The structure of an armchair graphene ribbon of width W.

It has been numerically confirmed that, even for potential fluctuations on an atomistic scale, there is strong evidence for electron-hole puddle formation on an intrinsic scale of 10 nm, in agreement with the experimental observations [12]. The simplest way to incorporate the effects of electron-hole puddles formation is to assume a Gaussian distribution for the density fluctuations associated with the puddles [13]. Then, the DOS per unit ribbon's length in the presence of electron-hole puddles can be written as [10, 13]:

( )( ) exp ( )ε ED E g ε dεσπ σ

+∞

−∞

⎛ ⎞−= −⎜ ⎟

⎝ ⎠∫

2

2

122

(2)

where g(ε) is given by Eq. (1) and the parameter σ corresponds to the standard deviation of the potential distribution representing the strength of the potential fluctuation. The potential fluctuation strength σ has been found to be in the range of 10-80 meV in typical graphene samples as extracted by fitting a recent microscopic self-consistent theory to existing experimental

transport data [12]. The carrier density per unit length is given by

( ) ( ) ( )D F Fn E D E f E E dE+∞

−∞

= −∫1 (3)

where ( ) 1( ) 1 / Bf x exp x k T

−= ⎡ + ⎤⎣ ⎦ is the Fermi-

Dirac distribution function which describes the distribution of electrons in the leads. Considering the electrostatics describing the structure, the following relation between the gate voltage and the Fermi energy can be obtained [8].

( )( ) .F D FG F

ins

E e n EV E conste C

= + +1 (4)

where Cins is is the gate-insulator capacitance per unit length of the GNR and the constant term includes the work function difference between the electrochemical potentials of the metal top-gate electrode and of the graphene ribbon, which can be neglected in our analysis provided that it is gate-voltage independent. The gate-insulator capacitance can be modeled by [14]:

ins Gins

WC N κ ε αt

⎛ ⎞= +⎜ ⎟

⎝ ⎠0 (5)

where NG is the number of gates (in this work NG=1), κ is the relative dielectric constant of the gate insulator, tins is the gate-insulator thickness and α ≈1 is a dimensionless fitting parameter. The non-zero value of parameter α is due to the electrostatic edge effect [14].

When the DOS as a function of energy is known, the quantum capacitance of the channel CQ at finite temperature can be calculated as [10]

( ) ( )FQ

f E-EC e D E dE

E

+∞

−∞

⎛ ∂ ⎞= −⎜ ⎟∂⎝ ⎠

∫2 (6)

The total gate capacitance CG can be modeled as a series of insulator capacitance Cins and quantum capacitance CQ

( )

( )( )

ins Q FD G

ins Q F

C C EC V

C C E=

+ (7)

The so-called quantum capacitance limit

(QCL) is reached if Cins > CQ. It has been argued that the device operation in the QCL have advantages regarding the power-delay product [15].

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3. RESULTS AND DISCUSSION

In this section we explore the effects of GNR width, gate-insulator thickness as well as dielectric constant κ scaling on the Capacitance-Voltage characteristics at room temperature in the presence of electron-hole puddles induced by local potential fluctuations. A reasonable moderate value of σ=35 meV is adopted to represent the potential fluctuation strength [10].

Fig. 2 shows the carrier line density as a function of gate voltage for GNRs with width variations from 2.5 nm to 10 nm. A thin gate-insulator with thickness tins=2 nm with relatively high dielectric constant κ=16 is used so that the transistor operation approaches the QCL. As it is seen, the carrier density modulation changes drastically with the bandgap widening which is a direct consequence of GNR narrowing. Looking at the n1D curves one obtains a range of threshold gate voltages from about 0.15 V to 0.75 V in order the transistor to be in the ON-state.

In Fig. 3, the gate capacitance is shown for different channel widths. As the width increases, a non-monotonicity of the C-V characteristics is observed. The number of peaks in the gate capacitance is a signature of the number of subbands contributing to the total carrier density.

Fig. 4 displays the dependence of the ratio CG/Cins on gate voltage for channels with width variations from 2.5 nm to 10 nm. Under ON-current conditions the effect of the quantum capacitance is a strong width-dependent reduction of CG from the ideal value Cins.

In figs. 5 and 6 the dependence of the gate capacitance CG(VG) characteristics on gate-insulator thickness and dielectric constant κ respectively, is illustrated. CG(VG) has non-monotonic behavior with ripples for thin or high-κ gate-insulators suggesting that the capacitance modulation is due to the quantum capacitance effect i.e., the DOS becomes the dominant source of capacitance. However, as we go beyond the QCL by increasing insulator thickness or decreasing dielectric constant, the ripples are suppressed and smooth monotonic characteristics are obtained over a bias range of 2 V± . As its seen gate capacitance remains approximately constant in the simulated range 0 5GV . V≥ , when high-κ insulators with thickness 10inst nm≥ or thin gate-insulators with 4κ ≤ are used.

Fig. 2. Carrier line density at room temperature versus gate

voltage for different GNR widths.

Fig. 3. Gate-capacitance at room temperature in GNR-FET

of various channel widths as a function of gate voltage.

Fig. 4. Ratio of CG/Cins as a function of gate voltage for

GNR-FETs with various channel widths.

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Fig. 5. Room temperature gate capacitance of 5nm-GNR

FET for different gate-insulator thicknesses tins. The dielectric constant of gate insulator is κ =16.

Fig. 6. Room temperature gate-capacitance of 5 nm GNR-

FETs for various κ gate-insulators. A thin insulator of thickness tins=2 nm is used..

4. CONCLUSIONS

In summary, scaling effects on the gate capacitance of graphene GNR-FETs are studied by means of a semi-analytical model which takes into account the presence of electron-hole puddles induced by local potential fluctuations. Thin gate-insulators of high-κ dielectric constant are used in our calculations in order to approach the quantum capacitance limit. Τhe scaling characteristics of the gate-insulator thickness and dielectric constant are explored. Gate capacitance has non-monotonic behavior with ripples for thin or high-κ gate-insulators. However, beyond the quantum capacitance limit (QCL) by increasing insulator thickness or decreasing dielectric constant κ, the ripples are suppressed and smooth monotonic characteristics are obtained. The interesting features of the C-V characteristics in

GNR-FETs described above could be tested experimentally by using recent advanced techniques on measuring quantum capacitance [9]. It is worth noting that, in the above calculations of the gate capacitance, parasitic capacitances due to capacitive coupling to the contacts have been neglected. This is a reasonable approximation since their contribution is negligible and cannot be tuned by a gate bias [9].

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