A 168µW MICS Band Transmitter Based on Injection Locking for Biomedical Sensor Nodes

Hadi Borjkhani1, Mehdi Borjkhani2, Samad Sheikhaei3 Department of Computer and Electrical Engineering University of Tehran

Tehran, Iran 1h_borjkhani@ut.ac.ir ,2m.borjkhani@ut.ac.ir ,3sheikhaei@ut.ac.ir

Abstract- Currently need for ultra low power wireless transmitters in medical applications are inevitable. In this paper a new transmitter for body-worn and implantable sensor nodes is presented. Most of the sensor nodes supply their power using energy harvesting instead of a battery, since the power earned by harvesting is limited, so the average and the peak power consumption of the sensor node must be minimized. transmitter blocks which implemented in sensor nodes are too power consuming. So we propose a new low power Binary Frequency Shift Keying (BFSK) transmitter based on sub-harmonic current mode injection locking, and edge combining technique. A 34MHz reference clock is used and the frequency of reference clock multiplied by 12 for desired carrier frequency. The phase noise of the carrier at 1MHz frequency offset is -110.3dBc, total power consumption is about 168µW. The output carrier frequency is 408MHz. BFSK modulation scheme is used at the frequency much lower than the carrier frequency in order to reduce the power consumption.

Keywords- MICS, WSN, BSN, BFSK Modulation, Sensor Node, Sub-Harmonic Injection Locking, Edge Combiner, Injection locked Oscillator, Transmitter.

I. INTRODUCTION Today’s sensor nodes have many application in biomedicine, since FCC established a new MICS frequency bandwidth for body sensor network applications (BSN). Sensor nodes are used to monitor the vital body signals such as ECG, EMG, EEG, body temperature, blood pressure, glucose and heart rate. Mentioned biosignals are required parameters that help researchers or scientists to find treatment for various diseases. In clinical healing system they are used to measure and monitor the patient’s vital signals in real time [1]-[4]. Measurement of biosignals need a sensor and a link between sensor and monitoring system (base station), where the biosignals are processed and stored or monitored. The link between the sensor node and the base station can be wired or wireless, although the wireless communication costs more and needs additional building blocks such as Transceiver, LNA and ADC, but it preferred over the wired link, because the wired link barely let the user (patient) to move from one side to other side and also wired sensor probes cab easily damaged and consequently corrupts the recorded signal. Also wired link for implanted sensors is an invasive procedure. With the help of wireless link sensor nodes

can easily implant. Sensor nodes consist of sensor, low noise amplifier (LNA), analog to digital converter (ADC), simple processor and transmitter. Sensor nodes have been used to sense and collect information of the environment, same as WSN nodes. Conventional WSN nodes need a battery as a power source since they consumes too much energy. Using a Battery increases the area of the node and also have a short lifetime and needs to be exchanged. In some cases such as implanting a sensor node in human body, exchanging the battery is an invasive procedure, so using a battery is not a good choice at least for implanted sensor nodes. Recently some implemented sensor nodes require less energy than the energy earned by energy harvesting.

Implanted Sensor Node

Reciever

MonitorMonitor

Sensor Node

RF Block

LNASensor ADC

Sensor Node

Processor

ADCLNA

Fig. 1. Wireless data communication between implanted or body-worn sensor node and base station

Transmitter in sensor nodes consumes dominated power of the system. If we reduce the power consumption in this block we relief the system from battery usage. In a dynamic system such as transmitter, the power consumption is proportional to the voltage swing, supply voltage and operation frequency the equation is given as:

. .swing DDP V V f∝ (1)

In conventional type Transmitters the power consumption is more than the power that is earned by energy harvesting because the mixing operation at high frequency need accurate oscillator at the frequency of the output carrier, since the carrier frequency is high to reduce the size of antenna. So according to the equation (1) data modulation at high frequency is power consuming. Not only the frequency which data is modulated is important but the complexity of the modulation itself has a great effect in reducing the power consumption [5], [6]. So we choose the BFSK modulation scheme for its simplicity [5].

Proceedings of 20th Iranian Conference on Biomedical Engineering (ICBME 2013), University of Tehran, Tehran, Iran, December18-20, 2013

978-1-4799-3232-0/13/$31.00 ©2013 IEEE 194

Data Modulation Duty cycle adjustion Sub‐H Injection‐Locked Osc.

Low frequency Moderate frequency

Freq. ×3

Edge combiner

High frequency (Output carrier frequency)

Impedance matching

Fig2. Detailed block diagram of the proposed transmitter architecture for a sensor node.

Transceiver in MICS band reported in [6] which is used ILFD technique to take the advantage of both OOK and FSK modulation. The transmitter in MICS band is also introduced in [7] which voltage mode injection locking is implemented to reduce the power consumption. In this paper we introduce a new architecture that is simple and easy to implement which employs several techniques to reduce the power consumption. In this new architecture data modulation occur at frequency much lower than carrier frequency (12 times). In order to increase the modulated signal to output carrier frequency we employ the current mode sub-harmonic injection locking and edge combining technique. This paper is organized as follow, section II describes the proposed transmitter architecture and it’s building blocks, section III shows the simulation results and the performance of the transmitter, and the conclusion is given at section IV.

II. PROPOSED ARCHITECTURE Proposed architecture shown in Fig.2, consist of data modulation at low frequency and a duty cycle controller circuit, a current mode sub-harmonic injection locking to ring oscillator, edge combiner and a impedance matching circuit at output. This architecture compared to the [7] has only one three stage ring oscillator and also the size and complexity of the transmitter reduced in oscillator and power amplifier.

A. Data Modulation Data modulation accomplished by pulling the crystal oscillator frequency into two distinct frequency which makes the binary frequency shift keying (BFSK) modulation. The crystal oscillator frequency assumed to be 34MHz, and a 20KHz frequency deviation is necessary to bear the binary frequency modulation, and the frequency difference at output carrier frequency is 240KHz.

B. Duty Cycle Controller (Pulser) Duty cycle adjusting is necessary since we need to strengthen the sub-harmonics. Proposed circuit shown in Fig.3 is employed to reduce the duty cycle of the reference clock and increase the power of the sub-harmonics. Duty cycle reduction cause equal strength of the harmonics so the oscillator can easily lock to the harmonics of the reference signal. Equations are given as:

14 sin( )2n

n Tan T

ππ

= (2)

214 sin( ) , 1

2n TP T T T T

n Tπ

π⎛ ⎞∝ = Δ⎜ ⎟⎝ ⎠

(3)

Where n represents the Nth harmonic and ∆T/T shows the duty cycle. If we reduce the duty cycle to zero according to the equations (2) and (3) the power of the harmonics will be almost equal. Here we choose 6.25% duty cycle to make sure that the ring oscillator is locked to the harmonics of the injecting reference signal.

Fig. 3.Pulser Circuit is used to adjust the Duty Cycle for required Nth-

Harmonic power

Proceedings of 20th Iranian Conference on Biomedical Engineering (ICBME 2013), University of Tehran, Tehran, Iran, December18-20, 2013

978-1-4799-3232-0/13/$31.00 ©2013 IEEE 195

Inverter with appropriate size control Duty cycle of the reference signal, here VBx and VAx (Shown in Fig.3) are delayed input for the NAND gate. the result of this NAND operation has shown in Fig.4. Proposed duty cycle controller is simple in comparison to the conventional circuits that uses a XOR gate.

Fig. 4.Waveform of the injected signal

C. Sub-Harmonic Injection Locked Ring Oscillator

Methods of the injection to a ring oscillator are different [7]-[8]. We use the current mode injection locking rather than voltage mode injection locking technique. Since the voltage mode injection locking produce more spurious and degrades the phase noise of the output signal and also sub-harmonic injection locking is not implementable, so we use the current mode injection locking to solve these issues. To lock a free running ring oscillator to sub-harmonics of the injected signal (Vinject shown in Fig.5) we seek the following steps: the first step is to find the locking range of the three stage ring oscillator and the second step is to design the three stage ring oscillator for desired frequency. Here we design the ring oscillator to oscillate at the 4x frequency of the reference signal. The free running frequency of the three stage ring oscillator is:

16( )of td

= (4)

Where td is the delay of the single inverter which is given by [12]:

01 12 1d d t

tt t tυα

−⎛ ⎞= + −⎜ ⎟+⎝ ⎠ (5)

Using equation (4) and (5) we design the free running oscillator at frequency around 136MHz.

Fig. 5. Current mode Injection Locking to a three stage ring oscillator

Frequency of the injection locked ring oscillator is given as [9]:

4

1 2 3

1( )2( )thinj

d d d

ft t t

=+ +

(6)

Where td1, td2, td3 are given as:

10

0.462

DD DDd

T

CV CVtI I

= + (7)

20

0.462

DD DDd

T

CV CVtI I

= + (8)

30 0

0.462

DD DDd

CV CVtI I

= + (9)

Using the equations (4) - (9) we have:

4

0

0

( ) 2.850.951.9

1

thinj

inj

ff

I I

=+

±

(10)

Where the 4( ) th

injf is the fourth harmonic of the reference signal. We choose Iinj/Io=0.5, according to the equation (10) we have

4[( ) ] 1.125 153thinj Max of f MHz= = (11)

4[( ) ] 0.75 102thinj Min of f MHz= = (12)

Locking range of the three stage free running oscillator is 51MHz, since our desired frequency is 136MHz, then theoretically ring oscillator can lock to frequency of 136MHz. BFSK modulation only needs two different frequency to send the data ‘0’ and ‘1’.

Proceedings of 20th Iranian Conference on Biomedical Engineering (ICBME 2013), University of Tehran, Tehran, Iran, December18-20, 2013

978-1-4799-3232-0/13/$31.00 ©2013 IEEE 196

Fig.6. Harmonic balance simulation result for a injection locked oscillator at 4x frequency of the reference signal. The frequency difference between the data ‘0’ and ‘1’ in our proposed circuit is about 240Hz so the sub-harmonic injection locked oscillator only needs to be locked into two distinct frequencies. Fig.6 shows the Harmonic Balance simulation results of the locked ring oscillator, when reference signal has changed into two distinct frequencies of 34MHz and 34.02MHz.

D. Edge Combiner

The last part of the transmitter is the edge combiner as a power amplifier (Fig.7). Edge combiner occupies the three phase of the ring oscillator waveforms to multiple the frequency where the multiplication order is three. First the AND operations multiple the output waveforms of the three phase ring oscillator together and the OR operation sums the output waveforms. The amplitude of the output waveform is 2/πRpIDC, where the IDC, is the current of the tail in edge combiner. RP is the impedance of the LC tank and a tapped capacitor matching network is used to match the low impedance of the antenna (the impedance of the antenna is 50Ω ).

50 Ω

Vout

Vo1

Vo2

Vo2

Vo3

Vo3

Vo1

C1

C2

C1

C2 RL

Vout

Vout

90mV

Equivalent Circuit of the Matching Network

Fig. 7. Edge combiner circuit and the equivalent circuit for the impedance matching network, output waveform has a 90mV peak to peak amplitude.

The R Impedance of the antenna transforms to n2R where n is equal to (C1+C2)/C1. For achieving high efficiency, the

transformed impedance should be equal to the equivalent Parallel impedance of the inductor.

Fig.8. Output waveform of the transmitter, 90mV peak to peak and the settling time is less than 80nsec.

III. PERFORMANCE The whole circuit simulated using the TSMC 0.13um CMOS technology file. CSR (Carrie-to-Spurious Ratio) in both frequencies of 408MHz and 408.24MHz is about 38dB (Fig.9). The phase noise of the output waveform has shown in Fig.10. both injection locking and free running modes of the transmitter has shown at the range of the frequency between 1Hz and 10 MHz, as you can see in the Fig. 10 the phase noise of the Output waveform is much better than the free running one. Output carrier signal has shown in Fig.8, settling time of the carrier is less than 80nsec. This settling time is smaller than the 250nsec settling time which is reported in [7].

Fig9. Harmonic balance simulation for output carrier signal when the

As shown in the Fig.10 the phase noise of the edge combiner degraded by 9 dB due to the multiplication. The amount of degradation in phase noise has a relationship with multiplication order of the frequency since at edge combiner we multiple the frequency of the oscillator to three then theoretically phase noise degrade to 9.5dB almost same as simulation results (20log(3)= 9.5dB).

Proceedings of 20th Iranian Conference on Biomedical Engineering (ICBME 2013), University of Tehran, Tehran, Iran, December18-20, 2013

978-1-4799-3232-0/13/$31.00 ©2013 IEEE 197

The summary of the transmitter performance is described in Table 1. Although the power consumption of the proposed transmitter is higher than the [7], less than the [12] and [13]. But our transmitter settles in 80nsec rather than 250nsec, size and the complexity of the transmitter is reduced in comparison to [7]. Since we take the advantage of current mode sub-harmonic injection locking technique, we can multiple the crystal reference signal up to 24, without increasing the area of the transmitter (just by adjusting the duty cycle of the reference signal). Our proposed architecture consumes 168µW and output carrier power is given:

2

0.0910log( ) 30 16.8400 pp

ppV v

V dBm=

+ = − (13)

Several parameters such as Rp (the parallel resistance of the inductor), the IDC, the rise and fall time of the three stage ring oscillator waveforms can control the output carrier power. Edge combiner decreases the power consumption as a result reduces the output carrier power.

Fig.10. Phase noise of the output when it is in free running and injection locking mode and also the phase noise of the injection locked ring Oscillators @ 136MHz Table 1. Performance of the ULP transmitters and the proposed transmitter

[12] [13] [7] This work

Power 400uw 350uw 90uw 168uw

Frequency 402-

405MHz

391-

415MHz

400MHz-

400.18MHz

408-

408.24MHz

Modulation BFSK MSK BFSK BFSK

Phase

noise@1MHz

offset

- - -102dBc -110.3dBc

Transmit

power

-16dBm - -17dBm -16.8dBm

process 130nm 90nm 130nm 130nm

VDD 1v 0.7v 1v 0.8v

IV. CONCLUSION Recent advances in biomedical field are requiring the need for low power transmitters for wireless communication. We

report a 168µW MICS band transmitter for implantable and body-worn sensor nodes. Several technique is used to reduce the power of the sensor node. Data modulation occur at frequency of the reference signal (34MHz considered as ‘0’ and 34.02MHz considered as ‘1’). Sub-harmonic injection locking and edge combining technique have been combined to multiple the modulated signal, in order to reach the frequency of 408MHz and 408.24MHz. The multiplication order can boost up to 24 without any area and complexity punishment. The phase noise of the output signal reduced, since the output signal is locked to the low phase noise reference signal.

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Proceedings of 20th Iranian Conference on Biomedical Engineering (ICBME 2013), University of Tehran, Tehran, Iran, December18-20, 2013

978-1-4799-3232-0/13/$31.00 ©2013 IEEE 198