Waiting Time Optim

Florante GA

508 CFlorante.Garcia@amd.com

Abstract One of the important steps that a semiconductthrough is electrical testing, which typically on an automated test equipment (ATE) plprimary goal of this step is to achieve mcoverage while minimizing testing time aoptimal. There are various test methods useranging from a simple continuity test to impsuch as built-in self-tests (BISTs) in whichinstructed to run internally and the test prograthe result only when it is done. BISTs are, in deterministic in nature; testing time can vary dthe internal clock frequency at which the tesother factors based on the chip’s operation. optimize testing time of non-deterministic testsread the results register immediately on compBIST execution, and not wait for a hard-codetime to elapse – typically, an amount of time slowest possible test execution to complete.discusses a method that eliminates unnecessawaiting for data that may have long arrived.

Introduction Built-in self-tests consist of three events: instruction, execution/waiting for completion,of result. After loading the instruction intthrough JTAG or other means, the BIST initiexecution while concurrent dummy vectors setime before attempting to read the result of the

There are two clock domains involved: the tesloading, waiting, and reading, and the core cBIST execution. The core clock domain is inDUT and aligns with a market-segment frepoint. While these two clocks run independentregister must be read only after the BIST completed. To make sure that the resulting dthere must be enough wait-time to allow execution to complete before result readout tak

Existing implementations have these thpopulated with a predetermined number including wait-time catered for the slowest rucreates unnecessary waiting time for faster rundata in the result register becomes available the wait vectors are complete.

mization of Non-deterministic Tests at A

Garcia; Jaime Padilla; Ericson Rosaria Advanced Micro Devices, Inc. hai Chee Lane, Singapore- 469032

m, Jaime.Padilla@amd.com, Ericson.Rosaria@am

tor chip goes is performed latform. The

maximum test as much as ed in testing, plementations the chip is

am checks for a way, non-depending on st is run and

One way to s at ATE is to pletion of the ed amount of based on the . This paper ary time lost

loading of and reading to the DUT iates internal erve as wait-e BIST.

ster clock for clock for the nternal to the equency test tly, the result execution is

data is valid, the slowest

kes place.

hree events of vectors,

un-time. This n-times when

long before

Figure 1: Simplified illustration of

This paper focuses on eliminatingtime and enables reading of the rafter the BIST completes runningDFT must include a pilot pin that ccompletion of the BIST executioprogram must have an infrastructurpattern bursts in the same test nattributes being set independently. Tset to “exit on first fail” mode, is a for the “in progress” state of the ppin switches to “done” state, the lothe wait burst, and the read-out butime.

Problem Statement Waiting for non-deterministic outptime by having the wait-time set delay. This creates the worst popoints at the highest internal unnecessary test time waiting foavailable. Figure 2 illustrate thiportion of the diagram is the evrunning while the tester is waitiWhen the BIST runs at the slowestime is minimized before the data afaster test point, the tester unnecessarily.

ATE

md.com

f a built-in self-test.

g this unnecessary wait-result data immediately g. To achieve this, the changes state to indicate on. Also, the ATE test re that supports multiple node, with each burst’s The wait burst, which is vector loop that strobes

pilot pin. Once the pilot ooping strobe fails, exits urst kicks in, wasting no

put can compromise test to the longest possible ssible problem on test

frequency, incurring or data that is already s process: the middle

vent when the BIST is ng for it to complete.

st test point, the waiting arrives; when it runs at a

wastes time waiting

723978-1-4799-2834-7/13/$31.00 c©2013 IEEE

Figure 2: Run-time events in a BIST.

Average time wasted on unnecessary waitinFigure 2 as the difference between tslowest andhighly dependent on the range of frequencies BISTs are run.

As an example, consider two BISTs that rufrequencies of 2.0 GHz and 1.4 GHz taking 125 ms, respectively, to complete. Using method, the wait-time must be set to at least 12is just right when the BIST runs at 1.4 GHz bextra 25 ms waiting time when it runs aEliminating that extra 25 ms is the focus of thi

Procedure This section outlines the simplified steps invoconcept, with special focus on the wait burst we derive the optimization covered in this pap

1. Load the instruction (burst1). No difcurrent method, this burst tells the DUT wcan be an instruction to initiate a memoother functional tests. Included in the inpreconditioning of the pilot pin to the “state.

2. Wait (burst2). While the BIST is busy invector loop simply waits until the pilot pithe “done” state, or until the maximcompleted. The current method always wmax loop to complete. When the wait burwithout seeing the “done” condition, it inthe test has timed out or the loop countenough; hence, the result register value is maximum loop count must be characalculated) to cater to the slowest BIStime.

3. Read the result (burst3). Also no difcurrent method, this burst reads out the reto determine whether the BIST completed.

Though at this point the whole concept is thnature, all necessary enablers appear to be feas

1. Multiple burst set-ups in a single testemplate may be developed to handle threattributes independent of one another. I

ng is seen in d tfastest. It is at which the

un at internal 100 ms and the current

25 ms, which but causes an at 2.0 GHz. is paper.

olved in this from which er:

fferent from what to do. It ory BIST or nstruction is

“in progress”

nside, a tester in changes to

mum loop is waits for the rst completes ndicates that t is not long invalid. The

acterized (or ST execution

fferent from esult register successfully

heoretical in sible.

st. An ATE e bursts with

It allows the

wait burst to exit on first fail wbursts may be set as they curre

2. Pilot pin. To serve as a monexisting pin and let the signal circuit come out of that pilot pcircuit will allow precondition“in progress” before starting toggling it to “done” once thrunning (tfastest to tslowest windowoutside world that the BIST is for read-out.

3. Pattern delay loop. Set to “epattern loop strobes for “in propin and exits only when the pwhen the max loop is complete

4. The ATE test template will treas good; no failure is bad bec“done” state did not come out o

Typically, the pattern delay is a sifor the longest possible wait-timethe chip does not support a pilot pinpin is the TDO from which a resultpossible to implement this concepsingle vector line, we loop a wholthe necessary header patterns to reuntil we get the “done” conditionobviously more efficient than loopi

This concept must be considered eaphase, when the DFT to suppointegrated into the chip’s blueprintis locked without the necessary DFimpossible to benefit from this conc

Feasibility of implementation can bthe cost of additional DFT to suppthe test-time optimization that implementing this concept.

Results With neither actual implemenavailable, we can visualize the theconcept through calculations.

WaitTime = (D + N) * Tcore WaitTime = V * Tper D, N, and Tcore are internal to the chexternal to the chip. Though N caand Tper, it can be obtainedcharacterization or based on theorcharacteristics. Once N is known, calculated using Equation 1(a). Usivalue in Equation 1(b), the numberwait burst then can be calculated us From 1(a) = 1(b), the number of vecan be calculated in equations

while the load and read ntly are.

nitor pin, multiplex an from an additional DFT

pin. That additional DFT ning of the pilot pin to the wait burst (t0), and

he BIST has completed w). This signal tells the done and result is ready

exit on first fail,” this ogress” state on the pilot pin toggles to “done” or ed.

eat the wait burst failure cause it means that the of the pilot pin.

ingle vector line looped . But sometimes, when n and the only available t can be polled, it is still pt. Instead of looping a e burst that includes all ead out data from TDO n. Looping a vector is ing a pattern burst.

arly in the silicon design ort the pilot pin gets . Once a product design

FT, it will be difficult or cept.

be scoped by comparing port the pilot pin against

can be derived from

ntation nor prototype eoretical benefit of this

1(a) 1(b)

hip while V and Tper are an vary regardless of V d practically through retical chip operational WaitTime then can be

ing that same WaitTime r of vector loops for the sing Tper min value.

ectors for the delay loop 2(c) and 2(d). The

724 2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

maximum number of vector cycles will be used to make sure that the result is always available after the loop is done and provided the BIST ran successfully. V * Tper = (D + N) * Tcore 2(a) V = (D + N) * (Tcore / Tper) 2(b) Vmaxloop = (D + N) * (Tcore max / Tper min) 2(c) Vminloop = (D + N) * (Tcore min / Tper max) 2(d) Waiting time can then be calculated using the number of delay loop cycles and tester period. Shown in equations 3(a) to 3(c), WaitTime Window is a range in the delay loop count when the BIST result possibly can become available. WaitTimemax = Vmaxloop * Tper max 3(a) WaitTimemin = Vminloop * Tper min 3(b) WaitTime Window = WaitTimemax – WaitTimemin 3(c) where:

D = number of deterministic cycles (internal) N = number of non-deterministic cycles (internal) Tcore = core period (internal) V = number of delay loop tester cycles (external) Tper = tester period (external)

In the example detailed in Table 1, test-time optimization in the context of this paper comes from avoiding 6,857,143 tester cycles when running at minimum Tcore. In terms of absolute time, that amount of vectors translates to 24.28 ms using Equations 3(a), 3(b), and 3(c), as shown in the table.

Table 1. Illustration on how delay loop count is affected by N, Tper, and Tcore. 1The largest number of wait loop vectors required happens when the BIST runs at Tcore max with max N cycles and tester runs at Tper min. 2The number of wait loop vectors needed for the earliest result to be available happens when the BIST runs at Tcore min with min N cycles and tester runs at Tper max.

WaitTimemax = 12857143 * 5 ns = 64.28 ms WaitTimemin = 6000000 * 6.67 ns = 40.00 ms WaitTime Window = 64.28ms – 40 ms = 24.28 ms

In the example, the result becomes available for read out between 40 ms (6 million vectors) and 64.28 ms (12.86 million vectors) from the start of the BIST execution. By using the concept presented in this paper, any extra waiting time of up to 24.28 ms is eliminated. With all the parameters known, a test engineer can quantify the maximum number of vectors it takes to wait for a BIST to complete execution and provide results for the tester/program to evaluate. Consequently, the

unnecessary waiting time to be avoided also can be quantified using these calculations. Once actual data is available, it can be counter-checked against those calculations.

Future Work As part of confirming the theoretical figures presented here, we plan to get on the tester to prove the actual usefulness of this idea. In the long run, migrating test coverage from the system-level test (SLT) platform to the ATE platform, testing time of non-deterministic test contents can become a concern. With the use of this concept, that concern may be minimized.

Acknowledgements 1. To the technical committee for giving us a chance to

share this idea

2. To our leads in AMD who provide motivation and inspiration to innovate

References 1. LTX-Credence Sapphire Software Manuals, LTX-

Credence Corporation, 2008. 2. SmarTest 7.2.0 Documentation, Advantest

Corporation, 2009. 3. IEEE Trans. Industrial Electronics, Special Issue on

Testing, Vol. 36, No. 2, May 1989.

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013) 725