Three-Path Electroplated Copper Compliant Interconnects – Fabrication and Modeling Studies

Raphael Okereke and Suresh K. Sitaraman George W. Woodruff School of Mechanical Engineering

Georgia Institute of Technology Atlanta, GA 30332 USA

Suresh.Sitaraman@me.gatech.edu

Abstract Compliant interconnects have been studied in universities

and industry over the past decade, as compliant interconnects could mechanically decouple the die from the substrate and thus could reduce the stresses in the die. In this work, we present the design, fabrication and modeling results of three-path electroplated compliant interconnect that addresses several of the challenges associated with various other compliant interconnects.

Sample interconnects were fabricated on 4” wafers to enable experimental validation of the designed micro-structures. There were about 8300 interconnects on each 20 x 20 mm2 chip in area-array layout. The interconnects were subjected to compliance testing. In parallel to the experiments, finite-element simulations were carried out to determine the mechanical compliance and the electrical resistance of the interconnects as well as their thermo-mechanical reliability. It is seen that the out-of-plane mechanical compliance will be more than 1 mm/N, several orders of magnitude greater than solder bump interconnects, and from a reliability perspective, the interconnects will last at least 1000 thermal cycles.

1 Introduction Electronic packages involving silicon die assemblies on

organic substrates have traditionally employed solder bumps as interconnects. These packages have typically used underfills to ensure the reliability of the bumps. The underfilled solder bumps mechanically couple the die to the substrate while providing routing for electrical signals. As die technologies continue to scale to attain higher transistor densities, the number of input/output connections needed per die continues to increase as well. The International Technology Roadmap for Semiconductors (ITRS) 2012 [1] forecasts a maximum pin count of 9192 for a 140 mm2 “cost-performance” die by the year 2026. This equates to a pitch size of approximately 125 µm for chip-to-substrate interconnects, down from 200 µm for the year 2012.

This trend creates reliability concerns with solder-bumped packages as a result of the decreased volume of solder per interconnect. The likelihood of bump failure increases with the reduction in bump sizes. Another type of failure common with low-K dielectric device packages is white bump failures. White bumps, so named for their appearance in an acoustic scan image, occur as a result of delamination of the dielectric layers beneath the bumps. This failure type usually occurs during the assembly-reflow process ever before the package is underfilled [2, 3]. White bump issues are further exacerbated with ultra-low-K packages which employ porous dielectrics as a way to achieve extremely low dielectric constants [1]. With the compromised structural integrity of

such a dielectric coupled with the high stresses generated in an underfilled package, the likelihood of reliability failures is greatly increased. Therefore an alternative packaging solution is needed to reliably package next generation electronic devices employing ultra-low-K materials.

Ultimately an interconnect technology that generates low package stresses is therefore needed. Such an interconnect by necessity needs to be compliant such that the reaction forces at the interconnect-to-die interfaces are low enough to not crack or delaminate low/ultra-low K dielectric layers. A challenge however with this type of interconnect is that they generally have higher electrical parasitics than conventional solder bumps or copper pillars [4]. Nonetheless, this is not a debilitating side effect as this paper will show that these interconnects are capable of meeting the electrical requirements of its intended package. It will also be shown that the proposed interconnect is cost effective by leveraging established fabrication procedures and wafer-level batch fabrication techniques.

2 Design

Figure 1: Interconnect geometric design details Several compliant interconnect designs exist but are

mostly of a single (electrical) path nature e.g. [5-8]. Single-path interconnects do not have redundant electrical paths, and thus, any defect or failure in that path during fabrication or operation can potentially make the die assembly not functional. Furthermore with respect to ultra-low K packages, the net reaction forces generated by single-path interconnects are concentrated over a relatively small area on the die which could potentially lead to high local stresses in such regions.

978-1-4799-0232-3/13/$31.00 ©2013 IEEE 129 2013 Electronic Components & Technology Conference

Figure 2: Fabrication of domed interconnects

Therefore a multi-path interconnect design, which offers improved compliance as a result of its distributed cross-section, is proposed. Since the effective area is kept constant, its electrical resistance will remain unchanged as would be shown later. On the other hand, its multiple conducting paths create interfering magnetic fields which attenuates its overall inductance, and thus has added benefit compared to single-path interconnects.

An added benefit of multiple paths is the redundancy. During operation, even if one of the electrical paths fails, the other paths will be functional, and therefore, no catastrophic failure will happen. In such a scenario, the die will continue to operate, as the electrical resistance change due to the loss of one of the legs of the interconnect will be significantly smaller when compared to the overall resistance of various traces connecting to the interconnect.

Multi-path interconnects [9-11] have been reported by our group and others. Out of these, “FlexConnects” [9] has an off-center design such that the die and the substrate pads do not align. Stress-engineered interconnects [10] require non-standard cleanroom fabrication processes. Floating-pad

technology [11] interconnects require sunken airgaps, flared base metal cups, vias in polymer films, transferable kapton film, and several processing steps, and no recent information seems to be available in open literature on these interconnects.

3 Fabrication Figure 2 illustrates a cut-section highlighting the

fabrication steps. Starting with a wafer with annular pads and patterned resist, as illustrated in Figure 2a, the resist will be reflowed in an oven (or on a hotplate) to generate the dome profile shown in Figure 2b. A metallization seed layer of titanium and copper (Figure 2c) will then be sputtered over the wafer for electroplating the compliant structure. The titanium layer ensures adhesion of the sputtered copper layer to the annular copper pad to improve its structural integrity. Following the metallization step, a second photoresist layer is spun onto the wafer as illustrated in Figure 2d for patterning the interconnect geometry. The photoresist is then patterned as in Figure 2e, and the interconnect plated up as in Figure 2f.

Figure 3: Pro-Engineer®5.0 3D rendering of Interconnect Upon electroplating, a third layer resist will be spun to

define the mold cavity for electroplating the solder as shown in Figure 2g. Solder is then electroplated as shown in Figure 2h. This completes the buildup process for the interconnects. The next step will be to release the structures to make them free-standing. First, the top two resist layers will be stripped away using an appropriate stripper and then the copper/titanium seed layer will be etched away using appropriate chemistries with good selectivity between copper and solder. This will expose the underlying polymer dome which will then etched away to reveal the free standing structure shown in Figure 2i. The last step which is the reflow of the plated solder shown in Figure 2j is an optional step. Unlike stencil printed solders, plated solder has sufficient mechanical rigidity and will stay adhered to the pad without the need for reflowing. Figure 3 shows a Pro-Engineer®5.0 3D rendering of the finished fully released interconnect while Figure 4 shows the SEM image of fabricated interconnect without the plated solder.

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Figure 4: Fully released domed interconnect sample

4 Modeling Finite-element models were created in ANSYS®13 for

mechanical simulations while FastHenry®2 was used for electrical simulations. The material properties used for the simulations are listed in Table 1. Copper was modeled as elastic-plastic with multi-linear kinematic hardening and Sn/Ag solder was modeled using Anand’s viscoplastic equation.

4.1 Compliance Compliance of the interconnect in a strict mathematical

sense is the inverse of the stiffness of the interconnect. In more general terms, it is a measure of how flexible the structure is. The higher the compliance, the lower its reaction forces at its supports for a given displacement. This implies that a compliant interconnect is less likely to crack or delaminate a low-K dielectric layer. However higher mechanical compliance implies higher electrical parasitics, and therefore, a good interconnect design aims to balance its mechanical performance against its electrical parasitics.

Models were created to determine the out-of-plane (y-direction) and in-plane (x-z plane) compliances of the interconnect. The modeling setup for the out-of-plane compliance determination is illustrated in Figure 5. The three arms of the interconnect were fixed in all degrees of freedom at their free ends. A vertical force was then applied to the center pad of the interconnect. Its out-of-plane compliance was calculated as the ratio of displacement of the pad to the applied force in the direction of the force. A similar setup was used for the in-plane compliance but with the force applied in the direction of the plane as shown in Figure 6. In addition to this, the force was applied in small incremental angles, θ, over 360o to determine the dependence of the in-plane compliance on the orientation of the applied force. The designed beam width, beam height and dome height of the interconnect were 6.6, 13.2 and 9 µm respectively.

Figure 5: Out-of-plane compliance simulation setup

Figure 6: In-plane compliance simulation setup

The out-of-plane compliance was computed to be 1.56 mm/N while Figure 7 shows the in-plane compliance of the interconnect as a function of the orientation of the applied force. The plot shows the interconnect to have a uniform in-plane compliance of about 0.89 mm/N. A uniform in-plane compliance suggests that the interconnect could be mounted without regard to orientation. Both compliance values are orders of magnitude greater than those of solder bumps fabricated at the same pitch.

Figure 7: In-plane compliance of interconnect as a function of load direction

4.2 Electrical Resistance and Inductance Electrical models were created in both ANSYS® and

FastHenry® to determine the resistance of the interconnects. The setup for the electrical models in both ANSYS and FastHenry were similar. The free-ends of the three electrical paths were tied to a common port and then electrically grounded. In ANSYS, a current of 1 mA was then applied to the central pad of the interconnect which created a potential difference across the interconnect. The electrical resistance of

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the interconnect was then obtained by dividing the voltage potential across the interconnect by the applied current. Figure 8A and B show the meshed geometry models in ANSYS and FastHenry, respectively. The resistance obtained using ANSYS was 11.6 mΩ and is believed to be more accurate as no geometric approximations were used. In FastHenry, the central pad was tied to a second port and then a frequency of 0.01 Hz was input into the program to generate comparable static simulation results. The difference between ANSYS and FastHenry resistance values was less than 1.5%. The simulated inductance using FastHenry was found to be 32.0 pH.

A. B.

Figure 8: Meshed models used for electrical characterization A) ANSYS discretization B) FastHenry discretization The in-built redundancy of the interconnect is best

exemplified with simulations of failed electrical paths. Models simulating failures in one or two electrical paths were created. These simulations describe how the resistance changes as fatigue failures begin to occur across the different electrical paths. The change in electrical parasitics of the interconnect with path failures is illustrated in Figure 9. With no failures, the resistance and inductance values remain at the levels reported earlier. When one path fractures, the interconnect will still function due to the two remaining electrical paths, and the interconnect resistance and inductance will increase by about 50% compared to the initial resistance and inductance values. When two paths fracture, and that is, with only one functional path remaining, the resistance and inductance values are about three times the original values.

The reference horizontal lines shown in Figure 9 represent the resistance (lower line) and inductance of a single-path interconnect design with the same total cross-sectional area as the multipath design. From Figure 9, it is seen that both single-path and multipath designs have the same electrical resistance but the multipath design has inductance values less than half that of the single path design. This shows that a multipath design has superior electrical parasitics when compared with a single path design. Also, the multipath design offers higher mechanical compliance as well as redundant electrical paths. It is noteworthy to mention that the simulated single-path and multipath designs had the same electrical path lengths.

Figure 9: Interconnect resistance for: No failures, 1 path failure and failure of 2 paths

4.3 Thermo-mechanical Simulation Thermo-mechanical models of an assembly incorporating

the three-path compliant interconnects were created to predict its fatigue life. Material properties of the silicon die, substrate and solder are listed in Table 1. The simulation used a 20 x 20 mm die mounted on a 24 x 24 mm organic substrate. To reduce the computational cost of simulating a fully-populated die assembly, a strip model was used. At 200 μm pitch, a total of 50 interconnects were modeled representing a half-symmetry strip model of a full-area array assembly. The width of the strip used in the model was the pitch of the interconnect and was equal to 200 µm. Figure 10 shows a strip model of the simulated assembly.

Table 1: Material properties used in finite element models

Component Material Properties

Interconnect Copper

[12]

Isotropic, homogeneous, multi-linear kinematic hardening model Modulus: 121 GPa

Poisson: 0.3

Resistivity: 1.69e-8 Ωm

Solder bump Ag3.5Sn

[13]

Isotropic, homogeneous, Anand’s viscoplastic model Modulus: 59 GPa

Resistivity:7.78e-8 Ωm

Die Silicon

[14]

Isotropic, homogeneous, linear elastic

Modulus: 125 GPa Poisson:0.25

CTE: 3 ppm/K

Substrate FR4

Orthotropic, homogeneous (smear properties) linear elastic

Modulus: 24 GPa Poisson:0.14

CTE: 11 ppm/K

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Figure 10: Modeled strip of a die-substrate assembly

4.3.1BoundaryConditionsSymmetry boundary conditions were applied on the cut x

face of the strip. The central bottom node at the cut face of the strip was constrained in all directions to prevent rigid body translation. The nodes on the z-faces of the strip were coupled independently both on the die and the substrate. The applied boundary conditions are illustrated in Figure 10.

4.3.2ThermalCyclingSimulationsThe assembly was assumed to be stress-free at solder

melting temperature of about 220 oC and simulated to be cooled down to room temperature as shown in Figure 11. The assembly was then simulated to be dwelt at room temperature and was subsequently simulated to be thermal cycled between temperatures of 0 oC and 100 oC. The thermal load specification complies with JEDEC JESD22-A104D-J [15]. The simulations were carried out for at least three thermal cycles until the stress/strain values stabilized. From these simulations, the die stresses and the overall warpage of the assembly as well as the accumulated total strain per cycle in the interconnect were obtained.

Figure 11: Thermal Load profile

4.3.3DieStresses

Figure 12: First principal stress (MPa) in die at 0 oC.

Figure 13: Out-of-plane die nodal displacement (mm) at 0 oC.

The overall principal stress within the die at 0 oC is shown

in Figure 12. This stress can be seen to vary between -1.11 MPa and 3.33 MPa. The extremely low die stress is a result of the high compliance of the interconnect. The high compliance of the interconnect decouples the die from the substrate, and therefore, reduces the die stress. This is evidenced by the low die warpage depicted by the out-of-plane (y-direction) displacement plot shown in Figure 13. The overall warpage of the die was calculated to be approximately 5.5 µm over a distance of 10 mm (half the die length). This warpage value falls within the surface variations of laminates/test boards and hence could be considered negligible.

4.3.4FatigueLifePrediction

Figure 14: Elemental accumulated total strain range for the third stabilized thermal cycle

. . 0.9.

.

∆ (1)

The fatigue life, Nf, of the outermost interconnect was

determined by the failure of either of its three paths. A

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Coffin-Manson type equation, equation 1, was used to predict fatigue life based on the accumulated total strain range, Δε, [16]. The accumulated total strain range was computed over a stable stress-strain hysteresis loop which occurred after the third thermal cycle. The fatigue ductility coefficient, εf, used in the model was averaged based on a typical range between 0.15 and 0.3 for copper [17].

Figure 14 is a plot of the elemental accumulated total strain range in the interconnect over the third thermal cycle. The maximum accumulated total strain range per cycle occurred at the location indicated by the arrow. Using Figure 14, a volume-averaged total strain range per thermal cycle near the critical region was computed as 0.00779, and thus, it appears that the interconnect will last more than 1200 thermal cycles as indicated by equation (1).

5 Testing The fabricated samples were characterized mechanically

and electrically as validation of the models and as proof of concept.

5.1 Resistance Measurement Electrical resistance measurements of the interconnects

were carried out using a four-point probing station. Figure 15 illustrates the resistance measurement setup for the four-point measurement. The measured resistance of the interconnect was found to be 15 mΩ. A finite-element model with the same dimensions, as in the fabricated interconnect, was then created. Using the resistivity value for copper in Table 1, the model yielded a resistance of 14 mΩ. Difference between these numbers could be attributed to the resistivity value of copper used in the models. Also, the resistance values reported here are greater than the values reported in Section 4.2 as the fabricated geometry had a smaller cross-section area compared to the designed geometry.

Figure 15: Four point resistance measurement setup

5.2 Compliance Measurements Mechanical compliance testing of the interconnect was

performed using a Triboscan® nano-indenter. The test setup was identical to that used in the model. A die sample with fabricated interconnects was fastened to nano-indenter’s work table. A load tip was then used to apply a prescribed amount of force to the interconnect in the out-of-plane direction while recording its displacement. One such force displacement curve is shown in Figure 16. From the unloading curve of Figure 16, the compliance of the interconnect was calculated to be 5.00 mm/N. This is several orders of magnitude higher than comparable solder bumps of the same pitch.

Compliance simulations with the fabricated cross-sectional dimensions gave a compliance of 2.19 mm/N; a

difference of about 50% compared to the measured compliance value. A possible reason for the discrepancy could be from the modulus of copper used in the model. Literature shows that the modulus of electroplated copper could vary widely depending on the plating parameters used. For example [18] reported a modulus range between 30 GPa to 200 GPa for electroplated copper. Repeating the out-of-plane compliance simulations for the modulus range of 30 to 200 GPa gives a compliance range of 8.76 to 1.34 mm/N for the interconnect.

Figure 16: Load vs. displacement plot to determine out-of-plane compliance

6 Conclusion The presented interconnect technology has been shown to

be reliable through finite-element simulations and has several advantages over other compliant interconnect technologies. The interconnects can be fabricated at the wafer level thereby making them cost-effective. The interconnects have low electrical parasitics with resistance and inductance values being 11.6 mΩ and 32 pH, respectively. The parallel electrical paths provide redundancy to reduce “open” failures during operation. Although this publication has focused on 200-μm-pitch interconnects, the interconnects can be scaled to other pitches. We have scaled and fabricated 100-μm-pitch interconnects as chip-to-substrate interconnects. We are also pursuing 400-μm-pitch interconnects that can be used as interposer-to-board or 3D-stack-package to board interconnects.

Acknowledgements The authors gratefully acknowledge the support of the

NSF in providing funding for this project under Grant No. ECCS-0901679.

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