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978-1-4799-2751-7/13/$31.00 ©2013 IEEE

A 4.2GS/s 4-bit ADC in 45nm CMOS Technology Manoj Kumar

Dept. of Microelectronics Indian Institute of Information Technology

Allahabad, India [email protected]

Saloni Varshney

Dept. of Microelectronics Indian Institute of Information Technology

Allahabad, India [email protected]

Abstract— In this paper an analog to digital converter architecture is introduced. The proposed design is based on a mixed approach of flash type ADC and SAR type ADC. This design offers lesser number of comparators and so low power consumption with much less circuit complexity in comparison to conventional flash ADC architecture. Based on the proposed idea, a 4-bit ADC is simulated in Cadence virtuoso Tool using 45nm CMOS technology with power supply voltage of ± 0.6 V. Maximum sampling speed of ADC is achieved as 4.2 GS/s. The ADC consumes 72µW of power .The measured INL and DNL are 0.40 LSB and 0.42 LSB respectively.

Keywords—Analog-digital conversion (ADC), Flash ADCs, INL, DNL

I. INTRODUCTION The evolution of advanced ultra-wideband communication technologies has improved the optical communication systems and serial links. This subsequently increases the demand of high-speed and low power ADCs having low-to-medium resolution (4 to 6 bit), for converting high frequency analog signals to digital signals for baseband processing. These Ultra wideband applications and wireless personal area networks always starve for high speed, lower resolution analog-to-digital converters [1]. Requirement of low power ADCs increasing day-by-day so that battery life can be prolonged in portable devices. Flash ADCs are the most desired ones for high speed and low resolution applications because of low latency and high data rate. However, in flash architecture the number of comparators increases exponentially with resolution which leads to increased complexity, high power dissipation and area, however, successive approximation register (SAR) ADCs dissipates lesser power at the cost of reduced operation speed [2]. In this paper, a 4-bit transitional architecture between flash and SAR ADC is proposed, which resembles to binary search algorithm. Section II describes the proposed ADC architecture. Simulation result is shown in section III while conclusion is in section IV.

II. PROPOSED ADC ARCHITECTURE The proposed ADC falls in between flash and SAR architecture category as all the comparisons are carried out in

one cycle and converted digital code is calculated using a technique similar to binary search algorithm. Fig. 1 shows the block diagram of proposed ADC.

In this work, four basic blocks are used (i) High speed comparator (ii) inverter (iii) or gate and (iv) multiplexer. To meet the required specification, these basic blocks are designed individually and then the ADC has been constructed by integrating them. The comparator is a bottle neck of ADC which consumes the maximum power among all the blocks. However, the proposed ADC uses 7 comparators but for a single conversion only 4 comparators will be effective at a time and rest 3 will be in “stand by” mode which saves a huge amount of power. To address the issue of low power dissipation, inverter is used to keep the comparators in “stand by” mode.

The most significant bit is used to drive the inverter, which divides the whole ADC architecture into two parts, the circuitry followed by inverter and a circuitry followed right after first comparator. The power supply (Vdd) arrangement of comparators for the inverted and non-inverted branches is shown in block diagram. Algorithm for this technique to calculate equivalent digital code corresponding to an analog voltage is defined in the following steps: 1. Compare input voltage (Vin) with half of the reference voltage (Vref/2), this gives the MSB of the equivalent digital code. If Vin > Vref/2 => MSB = 1, else MSB = 0; 2. To calculate MSB-1 bit: i. In case if MSB is at logic '1' then compare input voltage(Vin) with 3/4th of reference voltage i.e. 3/4Vref. ii. In case if MSB is at logic '0' then compare input voltage(Vin) with 1/4th of reference voltage i.e. 1/4Vref. To achieve this, connect MSB bit to an inverter, connect the Power supply terminal of comparator with 3Vref/4 and Vref/4 inputs to the inverter's input and output respectively. 3. Repeat steps 1 and 2 for next bits i.e. (MSB-2), (MSB-3) and so on. 4. Use multiplexers to select comparing voltages for comparators depending upon previous most significant bits.

2013 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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A demonstration of digital code calculationADC is illustrated in following steps: Step 1:- Begin, Initialize all the parameter, set valuvoltage (Vin) if Vin ≥ V/2, set B3 =High set B3=Low Step 2:- Set inv. input = B3 then if B3 = High then comp (c), comp (d), mode comp (b), comp (f), comp (g) = “Sta and if B3= Low then comp (c), comp (d), by” mode comp (b), comp (f), comp (g) = “O Step 3:- if B3 =High then if Vin ≥ 3V/4 , set comp (c ) outp set comp (c) outpSet B2 = output of comp (c) = output of comp (c) “OR1” out else if B3 =Low then if Vin ≥ V/4 , set comp (b ) output = Hig set comp (b) output = Low Set B2 = output of comp (b) = output of comp (c) OR1 out Step 4:- if B3 =High then if comp (c) output is low & Vin set comp (d) output =High if comp (c) output is High & Vin set comp (d) output =High

Fig. 1 Block diagram of proposed ADC

n by the proposed

ues of analog input

else

comp (e) = “On” and

and by” mode comp (e) = “Stand and

On” mode

ut = High else put = Low

tput of comp (b)

gh else w

put of comp (b)

≥ 5V/8 , h and

≥ 7V/8, else

set comp (d) oSet B1 = output of comp (d = output of comp (d el if B3 = Low th if comp (b) output set comp (f) o if comp (b) output set comp (f) ou set comp (f) ouSet B1 = output of comp (f) = output of comp (d Step 5:- if B3 =High if comp (c) ,comp(d) set comp (e) o Set B0 = output of comp ( = output of comp ( else if B3 =Low then if comp (b) ,comp(f) out set comp (g if comp (b) output is Loand Vin ≥ 3V/16 , set comp (g) if comp (b) output iand Vin ≥ 5V/16 , set comp (g) if comp (b) ,comp(d) o set comp (g) o set comp (g) Set B0 = output = output of comp end

output =Low d) d) “OR2” output of comp (f) lse hen is Low & Vin ≥ V/8 ,

output =High and is High & Vin ≥ 3V/8, utput =High else utput =Low )

d) “OR2” output of comp (f)

then output is Low and Vin ≥ 9V/16

output =High and (e) (e) “OR3” output of comp (g) e

tput is Low and Vin ≥ V/16, g) output =High and ow, comp(f) output is High output =High and

is High, comp(d) output is Low output =High and utput is High and Vin ≥ 7 V/16, output =High else output =Low of comp (g) (e) “OR3” output of comp (g)


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Fig. 2 Schematic of comparator [3]

Fig. 2 shows the schematic of comparator. This comparator design consists of four stages, which are, input preamplifier, latch, self bias differential amplifier and output buffer. The resolution of latch circuitry is very low so preamplifier is used to reduce the input offset voltage of the latch by the gain of preamplifier. The self bias differential amplifier is used to amplify the latch output and buffer is used to provide enough current for the load. Multiplexers are realized by transmission gate logic while inverter and or gate are realized using MOS transistors. Reference voltages are generated by ladder circuit.

III. ANALYSIS AND RESULTS This section presents the analysis and simulation results of proposed ADC. The design is simulated on Cadence virtuoso Tool with 45nm technology file. Fig. 3 presents the dc characteristics of comparator. At In1 a voltage of 500mV to 0V is applied and at In2 a 0v constant signal is applied. A full swing from -500mV to 0V is observed in Fig. 3.

. Fig. 3 DC response of comparator


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F

Fig. 4 shows the transient analysis of proposa 0 to 0.6V full scale range ramp signasimulation is done using ± 0.6 V power sushows all codes from 0 to 15 which reprfunctionality. The static performance of ADC is given bvalues. INL can be defined as the deviatioactual transfer function of the ADC from curve and DNL is defined as the difference step width and the ideal value of 1LSB [4]. Fig. 5 & Fig. 6 show the value of INL isvalue of DNL is 0.42 LSB.

Fig. 5 INL Codes

Fig. 4 Transient response of proposed ADC

sed ADC. At input al is applied. The upply. The output resent the correct

by INL and DNL on in LSB of the the ideal transfer between an actual

0.4 LSB and the

Fig. 6 DN

IV. CON

In this paper a high speed apresented which is highly suoptical communication systemcomparators are effective at a tpower and use very less chipconventional flash ADC. Maxproposed ADC is 4.2 GHz. CaLSB & 0.42 LSB respectdissipation of ADC is calculate

NL Codes

NCLUSION and low power 4-bit ADC is uitable for ultra-wideband and

ms. For one conversion, only 4 time which save huge amount of p area in comparison to 4- bit ximum sampling frequency of alculated INL & DNL are 0.40 ively. The maximum power

ed as 72µW.


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The speed of proposed 4-bit ADC is calculated as follows-

fmax = 525 MHz, fs = 2 x fmax = 2 x 525 MHz = 1050 MHz

Speed = no. of bits x fs = 4.2 GS/s

Table I shows the measured parameters of the proposed ADC and a comparison with other related work.

REFERENCES [1] S. Sheikhaei, S. Mirabbasi and A. Ivanov, “A 43mW Single-Channel

4GS/s 4-Bit Flash ADC in 0.18 um CMOS,” IEEE Custom Intergrated Circuits Conf. (CICC), 2007, pp. 333-336.

[2] T. Rabuske, F. Rabuskey, J. Fernandes and C. Rodrigues, “A 4-bit 1.5GSps 4.2mW Comparator-Based Binary Search ADC in 90nm,” 19th IEEE Int. Conf. on Electronics, Circuits and Systems (ICECS), 2012, pp. 496-499.

[3] P.E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 2nd Edition, Oxford University Press, 2002.

[4] Maxim Integrated Products, INL/DNL Measurements for High-Speed Analog to Digital Converters (ADCs).

[5] T. Sundstrom and A. Alvandpour, “A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS,” IEEE Conf. of NORCHIP, 2008, pp. 264-267.

[6] J. Yao, J. Liu, “A 5-GS/s 4-bit flash ADC with triode-load bias voltage trimming offset calibration in 65-nm CMOS, IEEE Custom Integrated Circuits Conf. (CICC), 2011, pp. 1-5.

[7] Y. M. Tousi and E. Afshari, “A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS,” IEEE J. of Solid-State Circuits, vol. 46, no. 10, pp. 2312-2324, oct. 2011.

[8] J. O. Plouchart, M. A. T. Sanduleanu, Z. T. Deniz, T. J. Beukema, S. Reynolds, B. D. Parker, M. Beakes, J. A. Tierno and D. Friedman, “A 3.2GS/s 4.55b ENOB Two-Step Subranging ADC in 45nm SOI CMOS,” IEEE Custom Integrated Circuits Conf. (CICC) ,2012, pp. 1-4.

Table I. ADC Performance Summary & Comparison

Author Name & Year

Rabuske 2012 [2]

Su ndstrom

2008 [5]

Yao 2011 [6]

Tousi 2011[7]

Poulchart 2012[8]

This Paper

Technology (nm)

90 90 65 65 45 45

Supply Voltage (V)

1.2 1.2 1.2 1.2 1.05 1.2

Power 4.2mW 30mW 34.3mW 2mW 22 mW 72µW Speed 1.5 GS/s 2.5 GS/s 5 GS/s 1.2 GS/s 3.2GS/s 4.2 GS/s

Resolution 4-bit 4-bit 4-bit 4-bit 4.64 4-bit INL(LSB) - 0.54 0.44 +0.78/-0.83 0.17 0.40 DNL(LSB) - 0.48 0.41 +0.54/-0.38 0.23 0.42


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