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Digital Communication & Information Theory NO PRJ
TITLE
ABSTRACT DOMAIN YOP
1
Error
Detection
in Majority
Logic
Decoding
of
Euclidean
Geometry
Low
Density
Parity
Check (EG-
LDPC)
Codes
In a recent paper, a method was proposed to accelerate the majority logic decoding of difference set low density
parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware
but requires a large decoding time. For memory applications, this increases the memory access time. The
method detects whether a word has errors in the first iterations of majority logic decoding, and when there are
no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be
error-free, the average decoding time is greatly reduced. In this brief, we study the application of a similar
technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step
majority logic decodable. The results obtained show that the method is also effective for EG-LDPC codes.
Extensive simulation results are given to accurately estimate the probability of error detection for different code
sizes and numbers of errors.
Digital
Communicat
ions and
Information
theory
2013
2
Reconfigur
able FFT
using
CORDIC
based
architecture
for MIMO-
OFDM
receivers
Fast Fourier Transform (FFT) is one of the most important algorithm in signal processing and communications
and is used in orthogonal frequency division multiplexing (OFDM) systems. FFT are the crucial computational
blocks to perform the baseband multicarrier demodulation in a MIMO OFDM system and the hardware
complexity will be very high. This paper proposes a CORDIC based reconfigurable 64 point Fast Fourier
Transform which is used for various IEEE standard based WLAN receivers. The CORDIC based FFT block
minimizes the hardware complexity because of the elimination of multiplier units and twiddle factors. This
design has the minimal hardware and computational complexity to meet the IEEE standard. In this paper, a
reconfigurable FFT has been realized based on CORDIC architecture. The coding for reconfigurable 64 point
FFT has been done using VHDL under Xilinx platform. The results are verified and are found to be compatible
with Virtex xc6vcx240t-2ff704.
Digital
Communicat
ions and
Information
theory
2013
3
Speed
optimizatio
n of a
FPGA
based
modified
viterbi
decoder
In the modern era of electronics and communication decoding and encoding of any data(s) using VLSI
technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path
with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the
same time increase the speed compared to normal decoder. This paper presents three objectives. Firstly, an
orthodox viterbi decoder is designed and simulated. For faster process application, the Gate Diffused Input
Logic (GDIL) based viterbi decoder is designed using Xilinx ISE, simulated and synthesized successfully. The
new proposed GDIL viterbi provides very less path delay with low power simulation results. Secondly, the
GDIL viterbi is again compared with our proposed technique, which comprises a Survivor Path Unit (SPU)
implements a trace back method with DRAM. This proposed approach of incorporating DRAM stores the path
information in a manner which allows fast read access without requiring physical partitioning of the DRAM.
This leads to a comprehensive gain in speed with low power effects. Thirdly, all the viterbi decoders are
compared, simulated, synthesized and the proposed approach shows the best simulation and synthesize results
for low power and high speed application in VLSI design. The Add-Compare-Select (ACS) and Trace Back
(TB) units and its sub circuits of the decoder(s) have been operated in deep pipelined manner to achieve high
Digital
Communicat
ions and
Information
theory
2013
#56, II Floor, Pushpagiri Complex, 17th Cross 8th Main, Opp Water Tank,Vijaynagar,Bangalore-560040.
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VLSI PROJECTS – 2013
(Network-Security & Cryptographic Sciences, DSP, Arithematic Core & Digital Electronics, Digital
Communication & Information Theory, Digital Image Proccesing)
transmission rate. Although the register exchange based survivor unit has better throughput when compared to
trace back unit, but in this paper by introducing the RAM cell between the ACS array and output register bank,
a significant amount of reduction in path delay has been observed. All the designing of viterbi is done using
Xilinx ISE 12.4 and synthesized successfully in the FPGA Virtex 6 target device operated at 64.516 MHz clock
frequency, reduces almost 41% of total path delay.
4
Faulty
Node
Detection
in
Distributed
Systems
Using BCH
Code
This paper proposes a faulty node detection scheme that performs collective monitoring of a distributed system.
The algorithm is designed to observe every node's behavior collectively based on the pseudo-random Bose-
Chaudhuri-Hocquenghem (BCH) code. Each node sends a single BCH bit simultaneously as a replacement for
the cyclic redundancy check (CRC) code. This method can be used for detecting and preventing serious
damage caused by node failure. Simulation results show that the high-polynomial CRC retains its performance
level, although its code is modified for the distributed BCH code.
Digital
Communicat
ions and
Information
theory
2013
5
Optimizing
Chien
Search
Usage in
the BCH
Decoder for
High Error
Rate
Transmissi
on
In hybrid automatic repeat request (HARQ), Bose-Chaudhuri-Hocquenghem (BCH) coders can be used before
transmission over noisy channel. A sent message is retrieved correctly via decoding, whenever it is correctable.
For uncorrectable message, a retransmission is requested by the receiver. In this paper, the detection time for
uncorrectable words is reduced. In particular, "Chien" search usage is optimized. It is only used when all roots
of the error locator polynomial belong to F_{2^m}^* = GF(2^m) {0}. Two binary primitive narrow sense BCH
codes are considered; the short length BCH(63,39,9) and the long length BCH(16383,16215,25) codes.
Digital
Communicat
ions and
Information
theory
2013
6
BPSK
System on
Spartan 3E
FPGA
The paper presents a theoretical background overview of the digital communication systems and the BPSK
modulation and demodulation. The purposed design is the BPSK system. The BPSK modulation and
demodulation represents an important modulation technique in terms of signal power. The BPSK system is
simulated using Matlab/ Simulink environment and System Generator, a tool from Xilinx used for FPGA design
as well as implemented on two Spartan 3E Starter Kit boards. The first board behaves as a modulator and the
second as a demodulator. The modulator and demodulator algorithms have been implemented on FPGA using
the VHDL language on Xilinx ISE 12.3. The local clock oscillator of the board is 50Mhz which corresponds
with a period of 20ns. The frequency of the BPSK carrier is 31,250 kHz. Both, the modulator and demodulator,
have been designed and simulated and theirs performances were evaluated by measurements.
Digital
Communicat
ions and
Information
theory
2012
7
FPGA
Implementa
tionof
Encoder for
(15, k)
Binary
BCH Code
Using
VHDL and
Performanc
e
Compariso
n for
Multiple
Error
Correction
Control
In this paper we have designed and implemented (15, k) a BCH Encoder on FPGA using VHDL for reliable data
transfer in AWGN channel with multiple error correction control. The digital logic implementation of binary
encoding of multiple error correcting BCH code (15, k) of length n=15 over GF (24) with irreducible primitive
polynomial x4+x+1 is organised into shift register circuits. Using the cyclic codes, the reminder b(x) can be
obtained in a linear (15-k) stage shift register with feedback connections corresponding to the coefficients of the
generated polynomial. Three encoder are designed using VHDL to encode the single, double and triple error
correcting BCH code (15, k) corresponding to the coefficient of generated polynomial. Information bit is
transmitted in unchanged form upto k clock cycles and during this period parity bits are calculated in the LFSR
then the parity bits are transmitted from k+1 to 15 clock cycles. Total 15-k numbers of parity bits with k
information bits are transmitted in 15 codeword. Here we have implemented (15, 5, 3), (15, 7, 2) and (15, 11, 1)
BCH code encoder on Xilinx Spartan 3 FPGA using VHDL and the simulation & synthesis are done using
Xilinx ISE 10.1. Also a comparative performance based on synthesis & simulation on FPGA is presented.
Digital
Communicat
ions and
Information
theory
2012
8
Design of a
Mixed-
Signal
Cartesian
Feedback
Loop for a
Low Power
Zero-IF
WCDMA
Transmitter
In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF
WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q
modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop.
We propose an optimized CORDIC design for the digital part in order to improve the system operating
frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined
CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two
times less than a fully analog system.
Digital
Communicat
ions and
Information
theory
2012
9
Design and
implementa
tion of
demodulati
on
technique
with
complex
dpll using
cordic
algorithm
CORDIC (Coordinate Rotation Digital Computer) is a simple and efficient algorithm to calculate hyperbolic and
trigonometric functions. It is commonly used when no multiplier hardware is available (e.g., simple
microcontrollers and FPGAs). The only operations it requires are addition, subtraction, bit shift and lookup table.
The pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex
Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver is designed. The design of
CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where
latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in the proposed
design can be achieved through optimization in the number of micro rotations. For better loop performance of
first order complex DPLL and to minimize quantization error, the number of iterations are also optimized.
Digital
Communicat
ions and
Information
theory
2012
10
Implementa
tion of
generalized
dft on field
programma
ble gate
array
We introduce the implementation of Generalized Discrete Fourier Transform (GDFT) with nonlinear phase on a
Field Programmable Gate Array (FPGA.) After briefly revisiting the GDFT framework, we apply the framework
to a channel equalization problem in an Orthogonal Frequency Division Multiplexing (OFDM) communication
system. The block diagram of the system is introduced and detailed explanations of the implementation for each
block are given along with the necessary VHDL code snippets. The resource usage and registered performance
of the design is reported and alternatives to improve the design in terms of performance and resolution are
provided. To the best of our knowledge, this is the first hardware implementation of GDFT reported.
Digital
Communicat
ions and
Information
theory
2012
11
Design and
Implementa
tion of
Reed
Solomon
Decoder for
802.16
Network
using
FPGA
This paper presents a design and FPGA implementation of a reconfigurable FEC Decoder based on Reed
Solomon Code for WiMax Network. The implementation, written in Very High Speed hardware description
Language (VHDL) is based on Berlekamp Massey, Forney and Chein Algorithm. The 802.16 network standard
recommends the use of Reed-Solomon code RS (255,239), which is implemented and discussed in this paper. It
is targeted to be applied in a forward error correction system based on 802.16 network standard to improve the
overall performance of the system. The objective of this work is to implement a Reed- Solomon VHDL code to
measure the performance of the RS Decoder on Xilinx Virtex II pro (xc2vp50- 5-ff1148) and Xilinx Spartan 3e
(xc3s500e-4-fg320) FPGA.The performance of the implemented RS codec on both FPGAs will be compared
.The performance metrics to be used are the area occupied by the design and the speed at which the design can
run.
Digital
Communicat
ions and
Information
theory
2012
12
Hardware
Implementa
tion of
Discrete
Fourier
Transform
and its
Inverse
Using
Floating
Point
Numbers
This paper concentrates on the FPGA implementation of discrete Fourier transforms (DFT) and inverse discrete
Fourier transform (IDFT) based on floating point numbers. Floating point representation of the numbers support
much wider range of values and achieve greater range at the expense of precision. Firstly general purpose
arithmetic modules addition, subtraction, multiplier and divider based on 32 bit single precision IEEE-754
standard are designed and then DFT/IDFT algorithms architectures are implemented. The architectures of DFT
and IDFT algorithms are based on radix 2 butterfly computations due to its less computation time .To reduce the
required hardware resources, resource sharing scheme is used. Algorithms architectures are designed using
hardware description language (VHDL), simulated using ModelSim6.6e tool and then hardware is implemented
on Xilinx Virtex-5 LX110T board.
Digital
Communicat
ions and
Information
theory
2012
13
Implementa
tion of
Adaptive
FIR Filter
for Pulse
Doppler
Radar
Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are
often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented
on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the
design of Adaptive Finite Impulse Response (FIR) filter for moving target detection in various clutter conditions
in Radar Receiver. The design uses pipelined COordinate Rotation DIgital Computer (CORDIC) unit and
pipelined multiplier to get high system throughput and reduced latency in each of the pipelined stage. Saving
area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed
design can be achieved through optimization in the number of micro rotations. For better adaptation and
performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized.
Digital
Communicat
ions and
Information
theory
2012
14
FPGA
Implementa
tion of
Modified
Architectur
e for
Adaptive
Viterbi
Decoder
The demand for high speed, low power and low cost for Viterbi decoding especially in wireless communication
are always required. Thus the paper presents the design of an adaptive Viterbi decoder that uses survivor path
with parameters for wireless communication in an attempt to reduce the power and cost and at the same time
increase the speed. The decoder was simulated using MATLAB 7. In the simulation the BER is calculated and
compared with the other models. Furthermore, the system operation under high frequency conditions is also
investigated. Next a VHDL description has been adopted to embed the lowpower design. The adopted design
were coded in VHDL and implemented on a SPARTAN 3. The results show that speed has been increased since
the the processing execution time has been reduced by removing the trace back algorithms that is used to find the
correct paths. Furthermore, the survivor path decoder is capable of supporting frequency up to 790 MHz for
constraint lengths 7, and 9 , rate 1/3 and long survivor path is 4. Finally, the cost has been reduced since the
different constraint length didn’t affect of the complexity of the decoder and the processing time of computing
the correct path
Digital
Communicat
ions and
Information
theory
2012
15
An
Efficient
All-Digital
Phase-
Locked
Loop with
Input Fault
Detection
An all-digital phase-locked loop (ADPLL) having a fault detection of the input reference signal was modeled in
Verilog hardware descriptive language (HDL) and is presented in this paper. The design can track an input
signal with frequency ranging from 61kHz to 43MHz in a maximum locked-in time of five reference cycles. In
the case of loss of input reference, it can continue to generate an output signal with the previously stored
parameters and report the anomaly as status. The functional and timing requirements of the design were verified
using Synopsys electronic design automation (EDA) tools. The ADPLL can be utilized as an intellectual
property (IP) core to reduce the development time of an application-specified integrated circuit (ASIC) product.
The input fault monitoring capability can provide operational feedback that improves the overall system
reliability.
Digital
Communicat
ions and
Information
theory
2012
16
A Novel
Hardware-
Based All-
Digital
Phase-
Locked
Loop
Applied to
Grid-
Connected
Power
Converters
For grid-connected power converters, the frequency and phase angle of the grid voltage, which are essential to
the system operations, must be quickly and accurately obtained even if the utility voltage is distorted or
unbalanced. In this paper, a novel hardware-based all-digital phase-locked loop (ADPLL) is proposed for grid
interface converters to detect the frequency and phase angle based on the voltage zero crossings. The proposed
ADPLL features wide track-in range and fast pull-in time, and it can easily be integrated with the digital
controller for gridconnected power converters. A discrete small-signal model is presented to investigate the
performance and parameter dependence of the ADPLL. As expected, the output phase error and pulse jitter are
minimized by selecting a high clock frequency and proper regulator parameters. With additional voltage sensors,
the ADPLL can be readily extended into applications with grid disturbances. Experimental results verify the
analysis and the effectiveness of the ADPLL.
Digital
Communicat
ions and
Information
theory
2012
17
Mixed
Cartesian
Feedback
for Zero-IF
WCDMA
Transmitter
In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a
classic WCDMA Zero-Intermediate Frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB)
loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback
I/Q demodulator and a digital stage adjusting the phase rotation around the loop. The digital phase-alignment
system consumes 2.94 mW (tree time less than a full-analog system).
Digital
Communicat
ions and
Information
theory
2012
18
FPGA
Implementa
tion of
Digital
Up/Down
Convertor
for
WCDMA
System
In this paper, we present FPGA implementation of a digital down convertor (DDC) and digital up convertor
(DUC) for a single carrier WCDMA system. The DDC and DUC is complex in nature. The implementation of
DDC is simple because it does not require mixers or filters. Xilinx System Generator and Xilinx ISE are used to
develop the hardware circuit for the FPGA. Both the circuits are verified on the Virtex-4 FPGA.
Digital
Communicat
ions and
Information
theory
2012
19
Analysis of
32-bit Fault
Tolerant
ALU
Methods
This paper presents a BCH based hardware implementation of 32-bit Fault-tolerant ALU in which is compared
with the current techniques such as Residue code, Triple Modular Redundancy (TMR) with single voting and
TMR with triplicated voter that are widely used in space application to mitigate the upsets, in terms of area
penalty. We consider BCH (Bose, Chaudhuri, and Hocquenghem) codec (encoder, decoder) that is implemented
FPGA hardware. The new implementation of ALU employing BCH code on Spartan-3 FPGA has been
provided. The results show reduced area requirements compared to the other technique and it can correct any 5-
bit error in any positions of 32-bits input registers of ALU
Digital
Communicat
ions and
Information
theory
2012