New Aspects on Analyzing ZVS Conditions for Converters Using Super-junction Si and Wide Bandgap SiC and GaN Power FETs

Rais Miftakhutdinov TEXAS INSTRUMENTS INC.

1000 Centre Green Way, Ste. 100 Cary, North Carolina, USA

Tel.: +1 – 919.859.7702. Fax: +1 – 919.859.7785.

E-Mail: r-miftakhutdinov1@ti.com URL: http://www.ti.com

Keywords «Gallium Nitride (GaN)», «MOSFET», «Silicon Carbide (SiC)», «Super Junction Devices», «Soft Switching», «ZVS Converters».

Abstract Paper analyzes substantial Coss behavior differences of FETs using super-junction Si, SiC and GaN technologies versus traditional Si process and suggests new practical models for power losses optimization. These models applied to derive normalized ZVS conditions and boundaries for popular PWM ZVS topologies allowing efficiency optimization at wide operating conditions.

Introduction Latest achievements in super-junction Si and wide bandgap SiC and GaN based power FET developments yielded commercial devices with very low Rdson and impressive switching performance. This technology is progressing rapidly and significantly changes power system design landscape versus traditional vertical Si MOSFETs. Still, detailed explanations are lacking how the new devices behave at different operating conditions and practical analytical models are needed for solving tradeoffs between efficiency, power density and system cost. For example, parasitic capacitances of new power FETs are substantially non-linear and behave differently from the traditional analytical models being used so far for zero voltage switching (ZVS) analysis. New general trend for power industry is that minimum losses and high efficiency must be maintained over the whole load current and input voltage operating range. Thus, the loss of ZVS even in limited operating range adversely affects on power system performance. Additionally, practical engineer has to deal with different drive technique for new power FETs and critical layout issues to accommodate fast switching behavior causing high dv/dt and di/dt noise and EMI issues. The paper addresses design and analysis issues to achieve ZVS in power converters employing new power FET technologies. It organized as following. In Section II key parameters of super-junction Si and SiC and GaN devices that contribute to conduction and switching losses, like Rdson, gate charge, input, output and Miller capacitances, are reviewed and compared. Section III focuses on output capacitance Coss behavior for various FETs and discusses their evaluation and modeling issues. Section IV describes switching process of PWM ZVS converters and determines normalized ZVS boundaries depending on power transformer magnetizing and leakage inductances and operating conditions. Section V includes simulation data to verify validity of analysis and derived approximation models. Finally, the conclusion section summarizes major goals and results reported in the paper.

Review of Si, SiC, GaN FET Technologies and FETs Wide bandgap semiconductor materials like GaN, GaAs, SiC exhibit combination of parameters that potentially make them better fit for power devices versus Si (Table I). Semiconductor material

parameters like breakdown voltage Vbr, mobility µe, bandgap Eg, relative dielectric constant εr determine theoretical limits of specific on resistance per die area at specified voltage rating of the

device, as it is shown in Equations 1 and 2 derived in [1]. Equation 1 applied to indirect bandgap materials like Si and SiC, while Equation 2 is for direct bandgap materials like GaN. Specific resistance using these equations is in mΩ•mm2.

Table I: Key Parameters of Popular Semiconductor Materials

Material Si GaAs InP GaN 4H-SiC

Bandgap, eV 1.1 1.43 1.35 3.4 3.26

Breakdown Field, V/µm 30 40 50 300 200-<300

Electron Mobility, cm2/Vs 1500 8500 5400 1500 700

Saturated Electron velocity, 107 cm/s 1 <1.0 1 1.3 2

Peak Electron velocity, 107 cm/s 1 2.1 2.3 2.5 2

Thermal Conductivity, W/cmK 1.3 0.55 0.68 >1.5 <3.8

Lattice Constant (a), A 5.43 5.65 5.87 3.19 3.07

Dielectric Constant, εr 11.7 12.9 12.5 9 9.7

reEgVbrRonspi

εμ ××××=

−62210351.3 (1)

reEgVbrRonspi

εμ ××××=

− 5.72210725.8 (2)

Based on this, theoretical limit plots have been drawn for different semiconductor materials and technologies (Fig. 1)

Fig. 1: Specific Ron resistance of different materials in mΩ•mm2 versus breakdown voltage in V

100 1 103× 1 104×0.1

1

10

100

1 103×

1 104×

1 105×

1 106×

GaNSiCSi

GaN Vbr( )

SiC Vbr( )

Si Vbr( )

Vbr

Based on these plots, for power device rated at 1000 V, the specific resistance of Si FET is 250 and 1400 times respectively higher versus SiC and GaN FETs. Certainly, the performance of currently available SiC and GaN power devices is far from their theoretical limits and significant efforts are under way to improve the process, manufacturability and yield at lower cost. But even early commercial samples show impressive performance. The SiC power devices also demonstrate better performance at high temperatures versus Si that makes them perfect choice for applications like drilling, airspace, electrical energy production and conversion, transportation. Production of SiC and GaN power devices is growing about 38% per year [2] and higher volumes will gradually drive the cost down.

Table II: Key Parameters of Commercially Available SiC and Si Power FETs

Vendor Part Material

Vds, V

Id, A

Vg, V

Rdson, mΩ

Qg, nc

FM, mΩ•nc

Die size, mm

Cree CPM2-1200-0080B SiC 1200 20 +25/

-10 80 49 3920 3.36x 3.1

Cree CPM2-1200-0025B SiC 1200 50 25/-

10 25 179 4475 6.44x4.04

Rohm SCT2080KE SiC 1200 35 +22/-6 80 106 8480 TO-247

Micro Semi

APTMC120AM55CT1AG SiC 1200 55 +25/

-10 49 98 4802 Module

ST Micro SCT30N120 SiC 1200 45 +25/

-10 80 105 8400 HiP247

Infineon IPW90R120C3 Si 900 36 +20/-20 100 270 27000 TO-247

Micro Semi APT41F100J Si 1000 42 +30/

-30 180 570 102600 Module

Key parameters of commercial SiC and Si FETs for comparison are shown in Table II. It shows that figure of merit FM of SiC FETs is about one order lower than Si FETs at rated Vds voltages 900V and above.Data sheet based switching performance parameters of the same power FETs are shown in Table III.

Wide bandgap power devices technology is in its introductory stage and this means large diversity of approaches taken by manufactures. FET devices include not only normally OFF, but also normally ON variations, i.e. JFETs. There are also SiC BJT power devices in the market. Even normally OFF devices require wide variety of drive voltages like, for example, 5 V for GaN FETs from EPC [3] to 20 V for SiC FETs from Cree [4]. Driver IC vendors follow the trend and introduced driver circuits optimized for specific power devices. For example drivers LM5113, LM5114 and UCC27611 from Texas Instruments are optimized for GaN FETs from EPC, while UCC27532 driver from the same company is optimized for use with SiC FETs [5].

Table III: Key Switching Parameters

Vendor Part Material Vds, V

Id, A

Ciss, pF

Coss, pF

Crss, pF

Cree CPM2-1200-0080B SiC 1200 20 950 80 6.5

Cree CPM2-1200-0025B SiC 1200 50 2980 220 23

Rohm SCT2080KE SiC 1200 35 2080 77 16

MicroSemi APTMC120AM55CT1AG SiC 1200 55 1900 160 13

ST Micro SCT30N120 SiC 1200 45 1700 130 25

Infineon IPW90R120C3 Si 900 36 6800 330 35

MicroSemi APT41F100J Si 1000 42 18500 1555 245

Non-linear Output Capacitances, their Evaluation and Modeling For highest efficiency at all operating conditions, the maintaining ZVS over entire load current range is critical. For accurate ZVS prediction, the switching energy of power FETs as function of drain-source voltage Vds, needs to be known. This switching energy is usually derived using Coss over Vds plots provided in datasheet by manufacturers. Example of such plot for classical vertical technology FET MTB8N50E is shown in Fig. 2a. Analytical interpretation of Coss as function of Vds and switching losses analysis is addressed in [6]…[10], [12]. This paper focuses on approach that can be applied to ZVS boundary conditions analysis and allows system level efficiency optimization at all operating conditions.

a) Coss behavior over Vds based on data sheet b) Plot of Coss behavior based on analytical equation (3)

Fig. 2: Coss behavior over drain source voltage of MTB8N50E using traditional vertical Si process

For standard vertical process the generalized Equation 3 provides good approximation. a

VoVdsVoVossCossVdsCoss ⎟

⎠⎞

⎜⎝⎛

++×= 11)( (3)

Where 0.5<a<1, Coss1 = Coss(Voss1) is provided in electrical table of datasheet. Usually Voss1 = 25V. Vo is offset voltage that derived from equation (4) describing Coss in the vicinity of Vds =0V.

a

VoVoVossCossVCoss ⎟

⎠⎞

⎜⎝⎛ +×= 11)0( (4)

0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 250

500

1000

1500

2000

2500

3000

3500

4000

Cef1 Vds( )pF

VdsV

Analytical approximation of Coss(Vds) for the same FET MTB8N50E shown in Fig. 2b demonstrates good correlation. In this case a = 0.8 and Vo = 1V.

Knowing analytical equation for Coss behavior as function of Vds, the functions of charge Qoss(Vds) and energy Eoss(Vds) can be easily derived by integration Coss(Vds) over Vds. There are few issues with such approximation. Firstly, Coss(Vds) plots are based on small signal measurements, typically at 1MHz signal while Vgs is shorted. Real switching behavior of FETs is large signal process and includes Vgs being at Miller plateau, not at zero level. Secondly, the behavior of Coss for super junction Si and wide bandgap FETs is more complex and it is difficult to approximate its behavior by single generalized equation over whole Vds range feasible for practical design. And thirdly, for ZVS analysis purposes the energy stored in parasitic capacitances of FET is more meaningful. Some FET manufactures provide energy plots over Vds in datasheet. Such plot for SPS11N60FCD super junction FET is shown in Fig. 3a.

a) Experimental plot from datasheet b) Analytically derived plot

Fig. 3: Comparison of analytical energy model Ecds over Vds for SPA11N60FCD type MOSFET The plot based on related analytical approximation described in [11] is shown in Fig. 3b. The equation used for this approximation is as follows:

25ln11 2

2 VdsCinitV

VVdsVossKc

CossEcds ×+⎟⎠⎞

⎜⎝⎛ +××= (5)

Here, Ecds is the energy stored, Coss1 is output capacitance from datasheet at Voss1 = 25V, Vds is the voltage, where the switching energy has to be found. Parameters Kc and Cinit are constants for each specific MOSFET. For SPA11N60FCD type FET from Infineon, Kc = 2.2 and Cinit = 40 pF. The plots shown in Fig. 3 are based on small signal measurements, while power FETs as part of switching power system operate at large signal by turning on and off with high voltage applied. It is important estimate large signal turn on losses associated with Coss and energy required to achieve ZVS and eliminate such losses. To evaluate large signal turn on losses the following test setup shown in Fig. 4 is suggested. In this test setup, transistors under test Q1 and Q2 are periodically switched on and off by external drive circuit. The drive signal must have sufficient delay time tgap between turning off one MOSFET and turning on another one to avoid current shoot through condition. It is critical to have the test setup layout with minimum loop parasitic inductance between capacitor Cin and transistors Q1 and Q2 to avoid the ringing affecting test results. From theory, the energy required to charge capacitor does not depend on charge current waveform and equal to twice of energy delivered to capacitor. Lost energy associated with full discharge of capacitor also does not depend on discharge current. Thus, within single switching event that includes discharge of Cds of one FET and charge of Cds of another FET during turn on of first FET, twice of energy stored in Cd-s capacitor is taken from input power supply. During periodical switching we have two switching events per switching cycle. Thus, for the switching turn on energy Eson over Vds consumed by single transistor the Equation 6 is applied.

0 100 200 300 400 500 6000

1

2

3

4

5

6

7

8

Vds (V)

Eoss

(mic

roJ)

4)( TIsVsVdsEson ××= (6)

Where Vs is supply voltage equal to Vds, Is is measured input current and T is the switching cycle of drive pulses used in this test.

The equivalent capacitance that needs to be recharged to achieve ZVS can be calculated using following Equation 7.

2

)(2)(Vs

VdsEsonVdsCson ×= (7)

Fig. 4: Test setup to measure Eson over Vd-s using switching process The turn on lost energy and related equivalent capacitance has been measured for Si super junction, GaN and SiC MOSFETs. The results of these measurements are presented in Fig. 5.

a) Switching turn on energy losses b) Switching turn on equivalent capacitance

Fig. 5: Switching turn on energy losses and equivalent capacitance using large signal measurements Comparison energy losses and equivalent capacitance based on large signal measurements in accordance to test setup in Fig.4 with vendors datasheet plots based on small signal show significant difference. Small signal based energy loss are 2.5 to 5 times smaller than based on large signal estimation. Also, large signal test based plots are smoother and do not show abrupt slope change as small signal test based plots [12]. Such differences need to be taken into account while designing efficient ZVS power converters to correctly estimate ZVS conditions and boundaries. Smooth large signal Cson behavior allows use the same generalized Equation 3 derived for standard Si based FETs. The approximation becomes simpler versus small signal model, like for example Equation (5). The approximation equations are provided below for the FETs Si super-junction SPP11N60CFD (Equation 8), GaN TPS2002PS (Equation 9) and SiC C2M0080120D (Equation 10):

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 4000

2

4

6

8

10

12

14

16

18

20

Si SPP11N60CFDGaN TPH2002PSSiC C2M0080120D

Vd-s, V

Turn

on

Ener

gy lo

sses

, uJ

0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400100

1000

10000

Si SPP11N60CFDGaN TPH2002PSSiC C2M0080120DSPP11N60CFD ModelTPH2002PS ModelC2M0080120D Model

Vd-s, V

Equi

vale

nt T

urn

On

Switc

hing

Cap

acita

nce,

Cso

n, p

F

75.0

55201617)( ⎟

⎠⎞

⎜⎝⎛

++×=

VVdsVVpFVdsCoss (8)

47.0

5520427)( ⎟

⎠⎞

⎜⎝⎛

++×=

VVdsVVpFVdsCoss (9)

4.0

5520762)( ⎟

⎠⎞

⎜⎝⎛

++×=

VVdsVVpFVdsCoss (10)

There is sufficient for practical design correlation between measured plots shown in Fig.5b as solid lines with approximation using Equations 8…10 shown in Feg.5b as symbol dots. Such analytical model allows relatively easy determine ZVS boundary conditions for converter and select optimal inductive components to achieve ZVS at specified conditions.

Switching Process and ZVS Boundaries of PWM ZVS Converters Typical PWM ZVS converter relies on leakage and magnetizing inductances of main transformer to achieve ZVS switching. The further analysis considers asymmetrical half bridge converter (Fig. 6) as an example, although the analysis can be applied to phase shifted full bridge, active clamp forward or other topologies using transition mode ZVS for switching losses reduction. After the topology is selected during the design, the next stage is to determine leakage and magnetizing inductances of power transformer that guarantee ZVS switching over the entire load current range. The energy stored in the leakage and magnetizing inductances is compared with the energy required to recharge MOSFET capacitances. We will review first all possible switching conditions when ZVS exists or lost. These conditions are shown in Fig. 7 describing the process when Q1 is turning OFF at time t1. This starts resonant transition process that could end with ZVS or without, depending on energy available in the leakage inductance Ls and magnetizing inductance Lm. In these waveforms current is is flowing in diagonal of half-bridge and vq is mid-point voltage between FETs Q1 and Q2. Current Id(n1+n2) is the current reflected from secondary side of transformer into the primary side, where n1=Wo/W1 and n2=Wo/W2. When is(t1) > ID(n1+n2) during the switching process, the rectifier DR2 stops conducting and only DR1 conducts. The overall switching process when FET Q2 is turning off is similar with the only differences in initial conditions.

Fig. 6: Asymmetrical half-bridge topology used as an example to review possible switching conditions

At the mid and high load current conditions ZVS is primarily maintained by the energy stored in the leakage inductance. In some cases, it is beneficiary to use special inductor in series with the primary winding of power transformer along with the clamped diodes ensure ZVS. At light load the energy is provided mostly by the magnetizing inductance of power transformer. Because the resonance frequency associated with the leakage inductance is significantly different from the resonance frequency associated with the magnetizing inductance, the delay time between primary FETs switching must be adjusted as function of the load current. Such adaptive delay time has to be provided by the controller IC. As the result of this analysis the following ZVS boundary conditions can be written as shown in Equations 11...14.

a) Energy of Ls allows ZVS, DR1, DR2 are ON b) Energy of Ls is too low, no ZVS c) Energy of Ls allows ZVS, DR1 is OFF, DR2 is ON

d) Energy of Ls exhausted, Lm provides ZVS e) Energy of Ls and Lm is too low, no ZVS f) No load condition, only Lm provides ZVS

Fig. 7: All possible switching conditions with and without ZVS for PWM ZVS converters ZVS boundary in accordance to waveforms in Fig. 7a and 7b:

22

2))1(( VaCdstiLs s ×≥× (11)

ZVS boundary in accordance to waveforms in Fig. 7c:

222

2))21()1((

2))1(( VaCdsnnItiLstiLs Dss ×≥+×−×−× (12)

ZVS boundary in accordance to waveforms in Fig. 7d and 7e:

222

2))21()1((

2))1(( VaCdsnnItiLmtiLs Dss ×≥+×−×+× (13)

ZVS boundary in accordance to waveforms in Fig. 7f:

22

2))1(()( VaCdstiLmLs s ×≥×+ (14)

Analysis Validation by Simulation To validate the analysis phase shifted full-bridge converter with the following requirements have been simulated: Input voltage range from 325 V to 450 V, output voltage and current are 12 V and 70 A accordingly. The switching frequency is 130 kHz. Super-junction FETs SPP11N60CFD are used on primary side. The selected leakage inductance is 5 μH and magnetizing inductance is 800 μH. The converter uses center-tapped synchronous rectification on secondary side with two FDP047AN08A0 FETs connected in parallel. Based on the analysis, ZVS boundary conditions and current on primary side of the converter have been drawn as function over the load current. These plots are shown in Fig.8a. Solid black line is primary current is(T1) that includes reflected secondary current and magnetizing current of the converter. Blue curve with circles combines boundary conditions by Equations 11…14. Below the blue curve is the area, where there is no ZVS. Thus, when the load current is above 10 A but lower than 35A, the converter does not have complete ZVS and it should cause increased switching power losses at this operating conditions. The simulated efficiency is shown in Fig. 8b. The efficiency dip in the load current region from about 10 A up to 35 A is clearly

observed. This the region where ZVS is only partial and thus, the selection of leakage and magnetizing inductances of power transformer is not optimized at full operating range. This is done by purpose for demonstration of ZVS optimization importance. By increasing leakage inductance or reducing magnetizing inductance full ZVS at all operating conditions can be achieved.

a) ZVS boundaries and primary current over load current b) Simulated efficiency shows increased losses from 10A to 35A load current

Fig. 8: Efficiency drop in the no ZVS region from 10A to 35A load current

Conclusion The paper starts with brief review and comparison of key parameters like Rdson, gate charge and parasitic capacitances of super-junction Si, SiC and GaN based newest commercially available power MOSFETs. It is pointed out that the revisit of extremely non-linear Coss small signal behavior of such devices is needed and new models developed for switching losses optimization using large signal measurements. Detailed description of switching conditions for popular PWM ZVS converters and related ZVS boundary equations are provided. The results of analysis are normalized allowing easily interpret ZVS operating conditions in graphical form. Efficiency simulations confirm the validity of analysis.

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0 10 20 30 40 50 60 700

1

2

3

4

5

Boundary 1Boundary 2Boundary 3Primary FET currentReflected secondary FET current

Load current, A

Curr

ent t

hrou

gh p

rimar

y FE

T

0 10 20 30 40 50 60 7090

91

92

93

94

95

96

97

98

99

100

EfficiencyLoad Current, A

Effic

ienc

y, %