IEEE CONECCT2014 1569825555

Differential Multi-phase DLL for Reconfigurable

Radio Frequency Synthesizer

Javed S Gaggatur, Vishal Khatri, Immanuel Raja, Manas K Lenka Electrical Communication Engineering

Gaurab Banerjee Electrical Communication Engineering

Indian Institute of Science Bangalore, 560012, INDIA banerjee@ece.iisc .ernet.in

Indian Institute of Science Bangalore, 560012, INDIA

(gsjaved, vishal,immanuel,manas) @ece.iisc .ernet.in

Abstract-A multi phase, delay-locked loop (DLL) based fre­quency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves ::; 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in O.13-j.tm CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stucklharmonic lock removal assist.

Index Terms-stuck lock, harmonic lock, delay-locked loops, multi phase, phase detector, frequency synthesis

I . INTRODUCTION

The delay-locked loop (DLL) has traditionally been used for clock generation, clock de-skewing, and data recovery in wire-line communication systems . Unconditional stability and the absence of j itter accumulation, makes it attractive for wideband RF applications . However, there are several challenges in operating a DLL at high frequencies, which limit its usage in RF systems. First, the reset path delay in the phase frequency detector limits the maximum operating frequency of the DLL. Second, the linear detection range of a PD lies within the period of the operating / reference frequency (± Tref ) [ 1 ] . When the operating frequency of a DLL increases, the corresponding Tref decreases. If the intrinsic delay of a voltage-controlled delay line (VCDL) is larger than the linear detection range of the PD, harmonic locking is observed. Third, when the frequency of operation increases, the short turn-on pulse-width can increase the current mismatch in the charge pump inducing a large static phase error [2] . Some of these nonidealities can affect the RF performance of the DLL by adding residual j itter (phase noise), and duty cycle errors (undesired harmonics) in the output [3] .

In this paper, we present the design of a wide range, 8-phase DLL. We also try to analyse the issue of "stuck locking " and propose a method to prevent its occurrence.

II . SYSTEM DESCRIPTION

The frequency synthesizer for a reconfigurable radio (Fig. i) needs to cover a wide range of frequencies (500 MHz-3 GHz) for multi-standard operation. The synthesizer must meet highly stringent and sometimes conflicting specifications . Given these requirements, getting a high quality local oscillator (LO) signal is very important. Most but not all frequencies can be generated using dividers and their combinations. But this

1

Bandpass Filter

Tunable LN A MIXER Lowpass

Filter

Fast Settling Tunable Frequency Synthesizer

ADC

Fig. 1 : Block Diagram of a Reconfigurable Radio

Delay· Locked Loop T,ef

Fig. 2: Block Diagram of a delay locked loop, DLL [4]

requires a synthesizer operating at least 2X the desired fre­quency. Delay locked loops (DLLs) and Phase locked loops (PLLs) are generally used for integer-N and fractional-N multi­phase frequency synthesis. DLLs have better stability, noise characteristics and a faster settling time in comparison to PLLs [4] but suffer from delay cell mismatch issue. The LO output is a square wave, which introduces harmonic down-conversion in RF circuits where RF information in higher frequencies, such as, 3wo , 5wo , two gets down-converted to the baseband, thus degrading the signal to noise ratio (SNR). Harmonic rejection mixing (HRM) can mitigate the effects of harmonic down­conversion, using a perfectly aligned multi-phase clock. Thus, DLL is a candidate architecture to generate an 8-phase clock

Ref.CLK � DLL.CLK � UP : i ! DOWN �

(II ) L1 Rising edge of DLL·eLK should be

I : located In this range.

Rtf.CLK � � DLLoCLK � c::> �

UP -----!.--r"L... DOWN ! l i

(b )

Fig. 3 : A DLL locking operation and operating frequency range limitation [7]

over the desired frequency range.

III . ARCHITECTURE

A DLL based frequency multiplier operates (as shown in Fig .2) by taking relatively j itter-free edges of the crystal oscillator (at a low frequency) and generating evenly spaced edges which span one period of the crystal oscillator output. These evenly-spaced edges (equivalently, phases) are then combined to synthesize a high-frequency RF signal .

The reference signal is the input to the delay chain. Each delay element produces a delayed version of this input. The phase detector senses the phase difference between the input and the output of the delay chain and generates an error signal . This error signal is then used to control a charge pump. The output of the charge pump is filtered by the loop filter to provide a control voltage that varies the delay of each stage to minimize the phase error. When the loop is in lock, the input and output of the delay chain are in-phase. The outputs of delay elements generate evenly spaced waveforms with edges within one period, resulting in phases between 0 and 1 800 , which are otherwise difficult to generate using conventional RF circuits.

The random timing errors, due to thennal noise, voltage variations, etc . accumulate within a single delay period but do not carry over to the next period. This is a key difference between phase-locked loops (PLLs) and DLLs, where the next output oscillation period in a DLL is always triggered by the reference crystal output. This provides low close-in phase noise, useful in many RF applications [4] , [5] , [6] .

A. STUCK / HARMONIC LOCK problem in DLL

When the delay of the voltage controlled delay line (VCDL) is initially smaller (or larger) than time period of the reference clock,Re!cLK , the DLL adjusts the TVCDL such that the phase difference disappears in a negative feedback loop as shown in Fig .2. The phase difference is detected by sampling the reference clock with the rising edge of the output clock (DLL-CLK in Fig . 3) . Depending on the sampled value, a DOWN or UP pulse is generated. These pulses discharge (or

2

Fig. 4: Architecture of the proposed DLL design

charge) a capacitor in the loop filter, thereby decreasing the control voltage and reducing the phase difference gradually.

If the DLL delay falls as shown in Fig .3(a), then a harmonic or a stuck lock occurs. This can happen due to the startup condition of the delay line. If the delay line does not turn on immediately when the loop starts, then the control voltage will keep on integrating until the VCDL turns on. This may cause the last phase to fall within positive half cycle of reference clock causing the DLL to be stuck.

The stuck-free conditions can be expressed with the follow­ing inequality [7] ,

0 . 5TcLK < TVCDL.min < TCLK TCLK < TVCDL.max < 1 . 5TcLK

( 1 )

(2)

Undesired locking occurs if the delay is less than 0 .5TcLK. The selection of loop gain decides the locking time. If the loop gain is too small, the locking time is high whereas if the gain too high, locking does not occur, but the control voltage keeps oscillating due to insufficient resolution.

We propose a simple stucklhannonic locking removal circuit as shown in Fig 4. When the DLL is turned ON, the VCDL is not turned ON (the current starving transistor is OFF) . As the loop integrates, all the delay cells in the VCDL turn ON and the loop tries to lock. It may so happen that during this initial startup phase, the two edges that are being compared fall out of the lock range of delay line. This may lead to a harmonic/stuck lock.

The proposed circuit alleviates this issue by sampling the reference clock (REF-CLK) with respect to the delayed clock (DEL-CLK) and a generates a DETECT signal whenever the delayed clock lies out of the lock range. This DETECT signal is then used to break or complete the loop.

Fig .S describes the stuck lock removal circuit. The control voltage is initialized to the maximum voltage (sustainable by charge pump). If the delayed clock falls out of the lock range, then DETECT signal goes low and an auxiliary charge pump discharges the loop capacitor. This discharging happens in open loop configuration. When the delayed clock falls within

REF eLK

Dela e

TSPC D-F/F

CLK RESETD

PRE _SW]ULSE

- , , ,Lock R,mge

�

DETECT becomes I

Auxiliary Chm·ge pump

Main Charge Pump

Fig. 5: A simple STUCK / HARMONIC Lock Removal circuit

RESETD = O VCNTRL_max = I

RESETD = I VCNTRL_max = 0 AUX_CP_DOWN = I MAIN_CP = O

RESETD = O VCNTRL_max = 0 AUX_CP _DOWN = I MAIN_CP = O Loop gets closed

Fig. 6 : Row of STUCK / HARMONIC Lock Removal during switch

the lock range, the DETECT signal goes high and the loop is completed, and the DLL operates normally. The proposed solution ensures that the loop begins its operation only when the delayed clock is within the locking range of the DLL.

B. Loop Bandwidth Tracking

Loop bandwidth tracking is done to ensure that a broad delay range is available and hence, the locking range of the DLL can be increased. However, this leads to the requirement of having a variable charge pump current which then, leads to increased complexity in the design and locking and unlocking of the DLL due to duty cycle mismatch [5] , [8] . The bandwidth tracking was used to enhance the quality of signal by reducing the jitter.

3

�-------r----r-Voo

� = Vout

V. """1-:-:---11 .,.

(a)

Fig. 7: (a) Current-starved delay cell (b) Pseudo-differential delay cell [9]

,.. ........

� .

� .

� .

, , , !¥8flrL�_J1J\IL� , , ,

Fig. 8: 8-phase output waveform and the reference clock

IV. CIRCUIT DESIGN

A. Delay Cell and Delay Line

As shown in Fig .7 , the delay cell is a single-ended inverter, consisting of M2 and M3 in series with Ml and M4 operating in the triode region. The delay of the circuit is determined by the equivalent resistance of Ml and M4 , controlled by Vc . An additional inverter comprising M5 and M6 serves as an output buffer for higher frequency operation. The circuit performs a rail-to-rail operation, so it consumes no static power.

Differential signals are preferable for better common-mode rejection. Cross-coupled inverters are utilized to regulate the differential outputs to perform the pseudo-differential oper­ation, as shown in Fig.7 . A clock with 50% duty cycle is

Delay Variation with respect to Control Voltage 200

1BO ["', \ 160 'iii � '" 140 Ia Gi c 120

1\ \ t····· .. 100 I�b 1 -

! BO � a .. v � u � u .. Control Voltage(V)

Fig. 9 : Delay variation with respect to control voltage for f=2.5 GHz

Delayed

CLK+

REF

Delayed CLK+

Delayed

CLK

Fig. 10 : Dynamic Phase Detector Schematic Diagram

critical for maintaining the spur level of the synthesized output. Appropriate design of the cross-coupled inverters can perform the duty cycle correction [9] .

The delay line is made by cascading eight such pseudo­differential delay cells. The output of each delay cell is buffered and taken out as a distinct phase. The delay variation with respect to change in control voltage VeT RL is shown in Fig .9 .

B. Phase Detector

A differential dynamic Phase Detector (PD) shown in Fig. 10 compares the phase of the reference clock with that of the feedback clock. The differential phase detector has a positive­edge triggered and a negative-edge triggered phase detector to compare the rising and falling edges of the differential clocks . The phase detectors have the same input to output delay. This is done to ensure that the UPIDOWN and UP­BARIDOWNBAR pulses being given to the charge pumps are also differential. A dynamic architecture provides an added advantage of high speed over a static phase detector.

4

Fig. I I : Differential Charge Pump circuit

C. Charge Pump

Fig . I I shows a differential charge pump with a feedback amplifier which allows to set a well defined COlmnon mode level. The charge sharing effect is mitigated by using a differential charge pump.

V. RESULTS

Starting with settling-time equation:

Assuming 90% settling,

Ts = 2 . 30257

1 7 = ­

Wp

(3)

(4)

(5)

Assuming that the DLL locks in 10 clock cycles, then Ts = lOT. The delay cell gain, KDL= 74 psN. The loop capacitor value was fixed to 10 pF, then the charge pump current was calculated to be 780.0pA. Based on this value and the delay saturation observed in the delay cell, an optimum range of 0.4V-0.8V was selected as the charge pump output voltage swing. The DLL was designed to operate from 500 MHz to 5 GHz. We observed duty cycle distortion along the delay line due to unequal rise and fall times observed at the edges. Due to this, the DLL was able to lock only between 850 MHz and 3 GHz.

TABLE I: Results

Lock Peak-to- RMS Phase Freq time peak jitter Error (GHz) (ns) jitter (ps) (%) (ps) 1 1 6 6.734 1 .09 0.673%

1 . 5 95 2.6 0 .42 0.39% 2.5 50 5 0.82 1 .25% 3 85 4 0.64 1 .2%

Tran s i �m RHPOn s � 8S�D."m��L-------------�-----------------------------------------------------------------------------------, ��---__ �__ Locked Signal

VCTRL keeps dropping t i l l t h e s ignal gets locked, i .e, secondary loop is OFF

Secondary Loop ON, Dout = 1 DLL Loop OFF

2 0 4 0 6 0 80 tim� (n ; )

Fig. 12: Harmonic/Stuck Locking Mitigation

A. Stuck/Harmonic Locking and its mitigation

As shown in Fig . 5 and Fig . 6, we analyse the stuck-at­lock condition at 500 MHz. To start with, the control voltage is set to 0.8V which puts the delay line in a minimum delay configuration. When the secondary loop is activated, the control voltage starts dropping, Dout is 1 in this case, as shown in Fig . 12 . Once the rising edge has moved within the locking range, Dout goes to O. Now, the DLL loop takes over and locks the loop.

Table I lists the results of the DLL locking for four different frequencies. Jitter and phase error are also listed.

VI . CONCLUSION

This paper presents a DLL-based frequency synthesizer for a reconfigurable, wideband radio. The DLL functions between 850 MHz and 3 GHz without an assisting loop. The peak to peak jitter observed at 2 .5 GHz is about 5 ps. The DLL operating frequency can be further reduced by adding a charge pump to mitigate the start-up problem in the delay line. The generated phases are expected to be useful in harmonic rejection mixers in wideband software defined radio receivers.

ACKNOWLEDGEMENT

The authors would like to thank their colleagues at the ECE department, IISc and the Department of Electronics and Information Technology (DeitY), Govt. of India, for financial support for CAD tools .

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