Evolution of Conventional Antilogarithmic Approach and Implementation in FPGA through

VHDL

Kousik Dan National Institute of Technology Calicut, Kerala-673601, india Kousikdan9609@gmail.com

Abstract —An antilog is the inverse function of a logarithm. Today, conventional use of the term "antilog" has been replaced in mathematics by the term "exponent". The binary logarithm is often used in the field of computer science and information theory because it is closely connected to the binary numeral system, in the analysis of algorithms and Single-elimination tournaments etc. So an efficient system has to perform antilogarithm at higher speed, lower power consumption with minimal area requirement .In this paper calculation of antilogarithm of a number with any base is proposed through four different approaches where next approach is modified version of previous approach. Obviously modification is done in such a way that there is an improvement of area, power and delays at each subsequent stage. FPGA implementation of each method is done with which, following the simulation result, comparison of these 4 methods can be made. Xilinx 13.2 version is used for simulation. The VHDL approach for FPGA implementation is done in binary fix point with base 2. However it is possible to take any other base and proceed through same algorithm with some modification that will be explained later. Area, power, delay and error analysis is done. At the end possible optimization techniques are proposed for future modification.

Keywords—Antilogarithm, FPGA, Hardware Description Language, Low Power.

Nomenclature: ALN—Accuracy limit number is the smallest number that larger number can be easily represented by suitable combination of ALN; It can be said as unit number of a particular bit pattern.

v(i)=Value of ith position digit of a number.

I. INTRODUCTION

Antilog calculation can be approached in two ways .One is iterative process where an approximate result is obtained at each stage of iteration. Increasing the accuracy increases the number of iteration process and consequently that will increase the number of multiplication or addition and hence power consumption or delay in actual hardware. Another antilog calculation is conventional approach that is the point of interest in this

paper where power and delay is the main concern .Again reduction of delay affect the area requirement at the time of hardware implementation. So a method is to find which meet power, delay and area requirement.

Antilog of a number X with a base B is present as

Z=Antilog(X) where X is called power of B or logarithm of Z with base B .This X can be represented in many format like real, fixed and floating. In binary fix point calculation gives overall idea that can be easily interpreted with other formats. To find antilogarithm of a number some algorithms or methods are to be followed and implementation of those ideas in FPGA that are explained later. Let’s see the methods or algorithms.

II. ALGORITHMS

Calculation for antilog is done first in very simple way. Suppose we have to find antilog ‘Z’ of power ‘x’ with the base ‘B’, then it can be written as

The power ‘x’ can be split into two parts that is integer part xi and fractional part xf . So

At that time Z can be represented as

Where Bi and Bf are the calculated parts of antilog that are obtained from integer and fractional part of the power respectively. To calculate Bi the base B is to be multiplied with itself xi times. But in calculation of Bf the same logic cannot be applied. However in calculation of Bf some methodologies have come into the field that are described next.

A. 1ST METHOD

At first a fraction number called accuracy limit number (ALN) xf0 is to be chosen such that

1839978-1-4799-3080-7/14/$31.00 c©2014 IEEE

After calculating the value of v follows the below mentioned steps 1. Set the register R=1 and reset the counter C=0 initially. 2. Perform the operation . 3. Increment counter C=C+1. 4. If then go to next step Else go back to step 2. 5. Stop operation. At the end the register value R gives the result that is R . As an example if we want to find the value of 20.357 then a number is to be chosen from 20.001, 20.0001, 20.00001 or so on and then multiply the value with itself 357, 3570 or 35700 times according to the selection of the number. If numbers of multiplications are more result will be more accurate in a fixed number of bit patterns. However time requirement is much more due to so many numbers of multiplications.

B. 2ND METHOD

Reduction of multiplication number is possible if another register Rk and two counters i and Ck are added and then as we process the following steps

1. Set the registers Rl=1, R=1, and reset the counters Ck=0, C=0 and i=0 initially. 2. Perform the operation 3. Increment counter Ck=Ck+1. 4. If then reset Ck=0 and Go to next step Else Go back to step 2. 5. If then Go to next step. Else go to step 9. 6. Perform the operations 7. Increment counter C=C+1. 8. If then C=0 Go to next step Else Go back to step 6. 9. ,Rl=Rk 10. If then go to next step Else go back to step 2. 10. Stop operation.

Here no of multiplications are or (42+9) or (42+9+9) instead of 357 or

3570 or 35700 to calculate 20.357 with 20.001 or 20.0001 or20.00001 respectively. In calculation of the fix point number the no of multiplications are further reduced which is explained in

next section with a specific example of unsigned fixed point number. Suppose

For B=2, (8 bit) and (8 bit)

Then maximum no of multiplications needed in first method is 255 and in second method is (8+8) =16. No of multiplications are reduced and hence power and time are also reduced with small increase in number of register and counter. The maximum no of multiplications can be further reduced to 8 using LUT approach where error data is saved in LUT. And only one bit shifting and 8 bit addition is to be performed 8 times instead of 8 multiplications that again reduce power and time with almost same area compared to second method.

C. 3RD METHOD

Reduction of multiplication, hence time and power consumption is reduced in base 2 by only one step addition, one bit shifting and concatenate (copy /paste) operation. Initially Rk is loaded with the value In rest of the iteration Rk value is updated according to

For example if xf0=”00000001” for 8 bit power then

That is represented in 13 bit as “1000000010110” where first bit is integer part and rest are fraction part.

Table 1.1

Stored value of error bit pattern for positive coefficient

Error

1 1000000010110 1000000010110 00000000 2 1000000101100 1000000101100 00000000 3 1000001011001 1000001011000 00000001 4 1000010110101 1000010110000 00000011 5 1000101110010 1000101100000 00000011 6 1001100000110 1001011000000 00100101 7 1011010100000 1010110000000 10010101

Fractional parts of all values (approximate or actual) of Rk are taken up to 13 bit. Errors are saved in bit ROM and updated value of Rk is used 8 times to get final value of R=Bf. The stored binary value of error in ROM is given in the last column in table 1.1

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It can be easily calculated that 4th iteration the approximate register value Rk is 1000010110101 that is shifted version of approximate value of 3rd iteration. So it is required to correct the approximate value by adding error bit pattern shown in table 1.1. Above all are explained for unsigned numbers. Signed numbers’ calculation can be done same way with little modification

Power,

)

Here x splits into such a way that (-1+xi) gives negative but (1+xf) remain positive. As an example -4.567 is splitting into xim=-5 and xfm=0.433.Now follow the same steps described above in all the three methods for calculating Bf with the value of xfm.

In binary as the base is 2, multiplication operation required to calculate Bi and multiplication of that value with Bf to get the final result can be avoided in two steps.

1. Calculate the value of xi in integer format 2. Left Shift or right shift (xi) bits the fractional part of Bf (m.n) as per needed using concatenate operation where m and n represent the bit length of integer and fractional part of Bf respectively.

.

: Left Shift is for positive value of xi and right shift is for negative value of xi.

In case of Hex-decimal and octal operation that left or right shift is and respectively. So in general if the base is represented by 2a format where a=natural number then left shift is .However in the other cases the conventional way of multiplications are to be follow.

D. 4TH METHOD

Maximum number of multiplications can be reduced to 4 using the concept of 2’s complement. To be clearer let us take an example The value of fraction part of power in worst case is

xf=“0.11111111”. 2’s complement of that is “0.00000001”.

So, we can write that

So, only one multiplication is needed for the second term and the first term is included in the integer part. In worst case Xf= (exactly 4 bits are ‘1’ and others ‘0’) and then maximum number of multiplications are 4 Instead of that is 8 in 3rd method.

From the second term it can be easily realized that multiplication has to be done for 5 times. However in the 3rd method it is 4. So a condition has to be introduced to restrict the number always less than the no of one’s present in Xf. Algorithm in 3rd approach is be modified to get that condition.

1. If the no of ‘1’ in Xf is >4 then ,M=1 Else M=0. 2. If M=1 then Follow 3rd method. Taking

complement of xf instead of xf with updating of Rk using step 3.

Else follow 3rd method with updating of Rk using step 3.

3. If M=0 then

Else

4. If M=0 then Bf=R Else 5. Stop operation.

Reduction in multiplication leads to decrease in time and power consumption but at the cost of increasing area.ROM size should be doubled here and extra one counter is needed to load the no of ‘1’ present in xf .In table 1.2 extra loaded error bit pattern is shown.

Table 1.2 Stored value of error bit pattern for negative coefficient

Error

1 0110101110100 0110110101000 0110100

2 0111010101100 0111010111010 0001110

3 0111101010010 0111101010110 0000100

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4 0111110101000 0111110

5 0111111010011 0111111

6 0111111101001 0111111

7 0111111110100 0111111

III. FPGA IMPLEMENTAAPPROACH

Unsigned fixed point antilogarithm implemented here in FPGA through VHDL

Fixed point represented as

Signed bit 1 bit

Integer bit pattern m bit

Frac

For unsigned operation first bit is omitterepresented by 8 bit fixed point number belong to fraction part only. So integer integer bit width is any non-zero value thresult obtained from 3rd or 4th method for be shifted left by the value representepattern.

Last two methods are implemented in device. Area requirement in each of these min terms of components that are found ireport. Again summary of synthesis is al3.1a and 3.1b that represent area requiremof slices, 4 input LUT, no of IOB.FPGA schematic are also shown in fig 3.1a methods 3 and 4 respectively.

Table 3.1a Device utilization summary of 3rd me

Table 3.1b

Device utilization summary of 4th m

0101001 0000001

1010100 0000001

1101001 0000000

1110100 0000000

ATION

methods are L.

ction bit pattern n bit

ed. Here power is where all the bits bit width is 0. If hen only the final fraction part is to

ed by integer bit

xc3s500e-5fg320 methods are given in HDL synthesis lso given in table

ment in terms of no based technology and fig 3.1b for

thod

method

HDL Synthesis Report fo Macro Statistics

# Multipliers 13x13-bit multiplier # Adders/Subtractors 13-bit adder # Counters 4-bit up counter # Registers 13-bit register 26-bit register # Comparators 4-bit comparator great 4-bit comparator lesse# Multiplexers 1-bit 8-to-1 multiplexe

HDL Synthesis Report fo Macro Statistics

# Multipliers 13x13-bit multiplier # Adders/Subtractors 13-bit adder 4-bit adder 8-bit adder # Counters 4-bit up counter # Registers 1-bit register 13-bit register 26-bit register 8-bit register # Comparators 4-bit comparator great 4-bit comparator great 4-bit comparator lesse# Multiplexers 1-bit 8-to-1 multiplexe

or 3rd method

: 1 : 1 : 1 : 1 : 2 : 2 : 2 : 1 : 1 : 2

ter : 1 equal : 1 : 1 er : 1

or 4th method

: 1 : 1 : 3 : 1 : 1 : 1 : 4 : 4 : 6 : 3 : 1 : 1 : 1 : 3

tequal : 1 ter : 1 equal : 1 : 2 er : 2

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Fig 3.1a FPGA Technology schematics for 3

3rd method

FFPGA Technology sche

Fig 3.1b ematics for 4th method

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Using these methods the o/p result that represent antilogarithm of i/p power bit pattern is of 13 bit where first bit is integer part and rest are fraction part. Out of 12 bits of fractional part first 8 bits always give the correct result even in worst case condition. So maximum error in 3rdmethod can be calculated as

In 4th method as numbers of multiplications are less maximum percentage error is less than that of 3rd method. From the table 2.1 all these four methods can be compared to each other in terms of area, power consumption, delay and error. In each column the best method is in top and next efficient method is below that and so on.

Table 2.1 Comparison of four methods in point of view of area

requirement, delay and power consumption.

I N C R E A S I N G

Area Delay Power consumption

error

1st method 1st method 1st method 1st method

4th method 2nd method 2nd method 2nd method

2nd method 3rd method 3rd method 3rd method

3rd method 4th method 4th method 4th method

IV. RELATED WORK

The approximate area requirement and power consumption for hardware implementation is more according to reference 2 and 4 than that of 3rd method cited in this paper. Again focusing of low power affect the delay in the approach of reference 3, 6 and that point is trade off in my 4th method. Considerable power density is to be maintained for reliability of the hardware that is inherited in my 3rd and 4th method but poorly seen in 1st and 5th reference. Again antilog of any base can be calculated using 3rd or 4th method by changing the error values only in table 1.1 and 1.2. That is another point of interest of this paper.

V. FUTURE WORK

The methods presented here are now more efficient than many other techniques for calculating antilog. Again further improvements are possible to make the system much more acceptable. Some points are given that may be the goal in future modification of these methods.

1. An efficient technique is to be found that avoid large bit multiplication to reduce delay and power consumption in a great manner.

2. Reduce the ROM size which reduces area.

3. Introducing parallel or pipelining approach to reduce delay more.

VI. CONCLUSION

This paper presented antilogarithmic evolution approach and its implementation on FPGA through VHDL. Among all the methods 3rd and 4th are more efficient considering all points of view. In comparison of the 3rd and 4th methods the former one is efficient in area while latter one is efficient in power and speed. So a trade off exists between these two methods.

At last it is to be concluded here that those four are applicable for any format of input with various bases. This is also one of the attractive features of these methodologies that open a way to modify the methods as per requirement.

REFERENCES

[1] H. Kim, B. G. Nam, J. H. Sohn, J. H. Woo, and H. J. Yoo, “A 231-MHz, 2.18-mW 32-bit logarithmic arithmetic unit for fixed-point 3-D graphics system,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2373-2381, 2006, DOI:10.1109/JSSC.2006.882887. [2] S. Paul, N. Jayakumar, and S. P. Khatri, “A fast hardware approach for approximate, efficient logarithm and antilogarithm computations,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 2, pp. 269-277, Feb. 2009, DOI:10.1109/TVLSI.2008.2003481 [3] K. H. Abed and R. E. Siferd, “VLSI implementation of a low-power antilogarithmic converter,” IEEE Transactions on Computers, vol. 52, no. 9, pp. 1221-1228, 2003,DOI:10.1109/TC.2003.1228517. [4] J. N. Mitchell, “Computer multiplication and division using binary logarithm,” IRE Trans. Computer, vol. EC-11, pp. 512-517, 1962. [5] M. Combet, H. Zonneveld, and L. Verbeek, “Computation of the base two logarithm of binary numbers,” IEEE Transactions on Electronic Computers,vol. EC-14, no. 6, pp. 863-867, Dec. 1965,DOI:10.1109/PGEC.1965.264080. [6] K. H. Abed and R. E. Siferd, “CMOS VLSI implementation of 16-Bit logarithm and anti-logarithm converters,” in Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 2, Lansing, MI, USA, 2000, pp. 776-779.

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