SiP Embedded Technology in 12 inch Format

Dyi-Chung Hu, Tsung Jen Yang, Ferry HuTechnology Center

ACE Technology, Inc.65, Kung-Fu N. Road, Hinchu Industrial Park,

Hinchu, Taiwan 303e-mail: dc_hu@ace-tek.com.tw

laser process commonly used in the advanced PCB process. OneAbstract can also use the PCB metallization process to make RDL. The other

type of SiP embedded using of molding technology to embed theSiP technology has been one of the alternative solutions to die into a mold compound. One example is General Electric's

system integration. Compare to SoC, SiP has the advantages of Embedded COF (Chip on Flex) technology. Basically, dies areintegration of dies made from different technologies, e.g. GaAs and adhered to a temporary substrate to its predetermined position, laterSilicon. In some cases, SiP technology may provide faster time to it was fixed by surrounding the die with molding compound. Later,the market and at a lower cost. the flat surface of reconfigured dies in the molded substrate can be

Despite many research activities, there are few companies used to processing RDL. Molded die technology is also used byactually went into mass production using SiP embedded technology Infineon (1) in their Embedded Wafer Level Ball Grid Arraydue to lack of standard process and equipment. ACET has (eWLB) technology and also RCP technology (Redistributed Chipdeveloped a SiP embedded structure and process for mass Package) by Freescale (2). The embedded reconstructed dies are

production. Current, ACET has mass production packages using 6" embedded in molding compound into a wafer like form. The size ofand 8" panel format. In order to further enhance the productivity the wafer can be 8" or 12". After wafer like form is obtained, it canand efficiency of the SiP embedded technology, going into a larger be processed like a silicon wafer and the tools used in wafer levelsubstrate is a next logical step. In the paper, we shall describe the packages can be used.development of SiP embedded technology in ACET. We also The major challenges to realize SiP embedded technology indemonstrated successfully of building packages using 12 inch mass production are as follows; First is to accurately embed the dieformat in our manual line. into a substrate in the predetermined position and second is to

assure the bonding pads are free of contaminates from the panelprocess (Wafer like form, later in this paper we called it panel form).

Introduction The third challenge is to minimize the warpage of the panel suchthat it can be processed by the standard semiconductor processingtools. The forth challenge is the compatibility the materials sets to

The trend of putting more function and devices to portable teceia n hra rcs uigmnfcuigo hand mobile systems have demanded packages with more function, ches.more devices into a smaller footprint. To meet this demand, SiP packages.(System in Package) technology has been one of the alternative ACET SiP Embedded Processsolutions to system integration. Compare to SoC (System on Chip),SiP has the advantages of integration of dies made from different Figure (1) briefly describes the process that we used totechnology, e.g. GaAs and Silcon. In some cases, SiP technology

make the SiP Embedded packages. First the bare dies are placed onmay provide faster time to the market and at a lower cost.

There are many companies and laboratories worldwidedevelop SiP technology. SiP technologies can be divided into three Die Bonding Tiiin

categories; Namely, SiP Stacked, SiP Side by Side, SiP Embedded.In this paper, we are concentrated to SiP Embedded technology. We Panel Forming I

can further classify the SiP Embedded technology into two types by +their embedding die technology. The first type uses lamination Carrier Attach Carriertechnology to embed the die. This technology is similar to that ofRD+UBused in PCB or FPC industry. Fraunhofer IZM has developedembedded chip technology call chip in polymer (CiP) technology. Thin Film Wiring & UBMITRI also has developed similar technology called chip in substrate Solder Balltechnology (CiSP). The process is as follows; thinned dies are Testing & Singulation --bonded to a substrate by a die bonder. Later, the thin dies arelaminated to the substrate. The pad on the die can be opened by

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Figure 1 ACET SiP Embedded process. Several different dies can be embedded in the samea temporary tool with predetermined position by a die bonder. The packages to form SiP modules. Another benefit of this technology istool surface has a layer of adhesive to prevent the dies from moving the addition of passive components such as inductors also can beduring the following processes. Later, the gaps between the dies are integrated into the same packages without additional cost.filled with filler that is encapsulation dielectric material. Anadditional back plate was placed on top of the encapsulation ACET 12" Panel Process Developmentmaterials. Later the encapsulation material is cured and the dies arefixed to the predetermined positions. After the encapsulation Processing packages using a bigger substrate has been amaterial is cured, the panel is then released from the temporary tool. successful model used in the semiconductor and TFT-LCD industryThe released panel can be in 6 or 8 inch format. The released panel for cost down reasons. This model can also be used in SiPis again place on top of a carrier. The panel and carrier structure Embedded manufacture. First, 12" round format panel was selectedthen can be processed in standard wafer processing tools. The RDL because of availability of thin film processing tools used in theis formed by first blank sputtering of Ti Cu or TiW Cu seed layers. semiconductor industry. In order to evaluate the expandabilty ofThe RDL pattern is defined by photo resist and lithography process. ACET SiP Embedded manufacture technology to 12" panel; weThe additional RDL copper thickness required for particular need to assure: first, the success of panel forming process in 12"package can be plated up in the plating tool. This process is similar format. Second, to assure the mass production process developed into semi-additive process used in advanced PCB industry to define our 8" panel line can be extended to 12" panel.fine lines. After making the RDL, the UBM process can beprocessed. Typical Cu/Ni/Au metallization is used for UBM. Later A 12" panel process was developed successfully. Figure (4)the solder balls are placed on top of the UBM. The packages are shows the embedded dies on a 12" panel in its panel form after thethen tested inspected and ready for shipping. ACET has successfulthntsednpcedadray f g panel is released from the tooling. The pad locations are withinuse this process in mass production of SiP embedded packages. ±15 um of their predetermined position. The pad location accuracy

Figure (2) shows the schematic structure of a packagemade by ACET technology. Figure (3) shows a typical cross sectionof the packages manufactured by ACET technology.

Soder Bl

RDLDie ~~~~~~~~~~~~Figure4 The picture shows dies are embedded in the filling

materials in their predetermined position.

Figure 2 The ACET SiP Embedded structure. The bonding pad location accuracy can be further enhanced byusing a more accurate bonder. This 12" panel is ready for furtherthin film lithography process. The dielectric layers can be spinnedon to the panel. The uniformity of layer thickness is within 10%across the panel. For metallization process, a seed layer was

sputtered on the dielectric surface. Again the uniformity of seedlayer thickness is within 10% across the 12" panel. A manualplating tool was used for plating the copper to the desired thickness.Uniformity of 10% copper thickness variations across the panel can

_ n~~~~~~~~~~~~~~eachieved by optimizing the process conditions in our manualplating tool. The panel is further processed to UBM and 0.3 mmsolder balls are placed on top of the UBM. Later the panel is testedin panel form. Individual packages are singulated from the panel.Figure 5 shows the 12" panel made by ACET SiP Embedded dietechnology. In this particular panel, the package size is 6x4 mm,2620 chips can be fitted in this panel.

Figure 3 Cross section of package made by ACET technology.

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References

1. M. Brunnbauer, E. Furgut, G. Beer and T. Meyer, "EmbeddedWafer Level Ball Grid Array (eWLB)", Proc. ElectronicsPackaging Technology Conference, pg 1-5, December 2006.2. B. Keser, C. Amrine, T Duong, S. Hayes, G. Leal, W. Lytle, D.

76U I I 6 l i i JMitchell, R. Wenzel, "The Redistributed Chip package", IEEETransactions CPMT, Part B, Vol. 31, pg 39 -43.

Figure 5 ACET 12" SiP Embedded Panel.

With the same diameter, the squared panels can hold 27%more dies on one panel than the round ones. We also successfullyproduce squared panel using our manual line. Figure (6) shows thesquare panel that we have produced.

Figure 6 shows 12" square SiP Embedded panel produced by themanual line.

Conclusion

ACET has mass production SiP Embedded packages using the6" and 8" panel format. ACET's 8" SiP Embedded panel formingand processing technology can be extended to 12" format. Theregistration accuracies of the dies are within the spec. The warpageof the panel is also under control and can be processed in thestandard thin film processing equipments. It is expected that thesize of the panel can be further increased beyond 12 inches usingACETSIP Embedded technology. Per package cost can be furtherreduced by going into bigger panels in the future.

Acknowledgement

The authors wish to thank ACET' s technology center team fortheir team efforts in developing the 12" SiP Embedded process andbring up the manual line.

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