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7/27/2019 Ieee Current Mode

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Soft Switching Technolsgies Corporataorr2224 Evergreen Rd. Suite .B 6, Middleton, W I 53562 T l S hTel : (608) 835-6552, Fax : (e1O8) 836-6553, E-naanl. i j i a t f i l r t ~ ~ ~ ~ ~ ~ - w ~ t c h . c o n n

Abstract-In this pager, both peak current mode and averagecurrent mode control schemes will be iniveskigated as applied toa full bridge PW M converter with a two iinductor rectifier. Thet w o inductor rectifier circuit offers reduced secondary sidecurrent rating and i s most suitable for high currentapplications. With current mode control, the two ~ n d ~ c ~ o rrectifier s modelled as two parallel connected buck converlcrs.

I. INTRODUCTIONSince its inception in the late 1960s, current mode controlhas been widely applied to switch mode powex supplies.This approach offers improved dynamic response andparalleling cap ability as co mpa red to vloltage mode, control orduty cyc le control by effectively elimiiieiting the phase lag ofthe control to inductor current transfer function.TWOypes of current mode control relevant eo this workare peak and average current mode control. Peak currentmode control (PCMC) off ers inhie rent inp ut voltagefeedforwa rd, pulse by pulse peak current limiting andconse quen t flux balance in isolated pow er supplies. De!jpitethese advantages, PCMC incurs poor noise immunity,average current error, and instabilities in the absence of slope

complznsation. Alternatively, average current mode control(ACMC) exhibits accurate regulation o f the programmedcurrent and improved noise immunity without slopecompensation.In this paper, peak and average current mode controltechniques are applied to a full bridge E'WM converter .withtw o inductor rectifier. Th e two inductor rectifier circuitoffers reduced secondary side current rating compared to afull bridge or center tapped rectifier topology and is mostsuitable for high current applications. Fixthermore, the twoinductor rectifier can be modeled a s tw o parallel buckconverters. How ever the analysis differs from parallelconnected modules in that the output inductors share thesame output filter capacitor. This leads to cross couplingbetween the two converters which needs to be accounted for.

CONV WIT

A full bridge PWM DC-to-DC converter with a twoinductor rectifier was first proposed by the author in [ l ] andis shown in Fig. 1. The two inductor rectifier circuit wasfirst reported in [2].

Fig. I : A full bridge PWM iX- to- .DCconverter with a two indiictorrectifierThe output voltage is controlled using hase shift controlwhich allows zero voltage switchjng (ZVS) of the inputbridge. The advantages o f the two inductor rectifier circuitinclude lower secondary s.i& current rating and hence lowerlosses, frequency doubling at the output capacitor, outputcurrent doubling in addition to an inherent 24. voltage ratio.This makes this converter attractivk: for high current, Lowvolta,ge applicatio ns.

'Flhree cir cui t. mo des c m be identified for the converter ofFig. 'L within half a switching cycle: a power delivery mode(mode-I) , a freewhee ling mode (mode-IT) and a commutat ionmode (mode-111) as shown in Fig. 2.I n phase shift control, when a switch in the leading edgeis tuned off, the energy available for achieving ZVS for theleading leg is th e output filter energy. How ever, for thelagging leg switches, th e only energy available forcommutat ion i s the leakage inductance energy. Hence, theleading leg switches achieve ZV S even at light loads,whereas %VS i s lost in the lagging leg switches below acertain load condition. Typical voltage and currentwaveforms are shown in Fig. 3. In the sie.ady state the outputvoltage is given by

Note that sirice the output cunent is th e su m of the twooutput filter cun-enes, th e current rating of transformersecondary winding is one half the load current. Thiseffectively reduces the ac winding losses in the transformerand output fileer inductors.


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sec.(a)v f p y ql f + + v os Ls

'n q=lIl/pppprim. sec.(b ) Ls Lsprim. sec.(C)

Fig. 2: Equivalent circuit modes of the convertex

i Mode-I :Mode-111 Mode-III!

. .... . +t. . .. . ., . .. .. .. .. . .. .. .. . . .. . .. . .. .... . . . . ... . . .. . .. . .. .. _ .. _ .. .. .. ... .i i 'Ds2

t. .. . .. . .. .. . ., . .. .. . . . .. .. . .. ... ... . , . . . . .. . c

i DTs- 2Fig. 3 : Typical waveforms of the converter

Adopting current mode control ensures current sharingbetwe en the two outp ut filter inductors. An inner currentloop regulates the filter inductor currents while an outervoltage loop regulates the output voltage. In power supplyapplications operating in current limit, the inner current loopis the only active loop.

The two inductor rectifier can be modeled as tw o parallelconnected buck converters. How ever the analys is differsfrom parallel connected modules in that the output inductorsshare the same output filter capacitor. Thi s results in crosscoupling between the two output inductor currents and caremust be taken when d esigning the control loops.

111. Average Current Mode Control ImplementationAverage current mode control is preferred for accuratecontrol of the average output current and offers higher noiseimmunity compared with peak current control. This isadvantageous in current limited power supplies where thesupply current is limited. For this mod e of control, currentsensing can be performed either on the input side or theoutput side of the isolation transformer. However, with inputcurrent sensing, the negative slope of the output currentneeds to be synthesized which can result in an error if theoutput filter inductors are designed using swinging cores.On the other hand, output current sensing offers accurate

measurement of the average output current but does notguarantee flux balancing in the isolation transformer. A s aresult, a dc bloclung capacitor is needed to prevent fluximbalance. Figure 4 shows a converter schematic withaverage current control and outpu t current sensing. In thisconfiguration, a dc blocking capacitor (C,) is utilized toprevent flux imbalance.I I& : " L f I ,I

I I I I -1'5

Fig. 4: Converter under average current mode controlDifferent techniques have been proposed to analyzeswitching converters utilizing current mode control [3-51.The simplified PWM switch model will be used to analyzethe system at hand and is show n in Fig. 5 [3].

transformerFig. 5: PWM switch modelSince the output current is the sum of the tw o outpu t filterinductor currents, the system can be reduced to two parallelconnected buck converters [7,8]. Furthermore, since the

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output filter inductor currents are not individually regulated,the small signal model of the system can be reduced to thatof a single buck converter with average current mode controlwhere the resultant filter inductor is the parallel combinationof the two output inductors. Although each inductor currentis not separately regulated, any difference between theaverage currents will be corrected by the input dc blockingcapacitor which maintains zero net dc flux within the:transformer. Th is guarantees that the two inductor currents,remain equal. Note that the effective switching frequency ofthe resultant system is twice the switching frequency for thetwo filter inductor currents are out of phase which results infrequency doubling at the o utput.Using the PWM switch model and assuming thetransformer is ideal, the equivalent small signal model of theconverter is shown in Fig. 6.

L .L =-+.+"0

Fig. 6: Small signal model of the converterHere, Rs is the sen se resistor, He(S) is the sampling gain, Fmis the modulator gain and Gc(s) is the compensation transferfunction. The sam pling and modulator gains are defined in[ 6 ] o be

where,r)

Q =- fn

0, n f, $

22

S :iH e ( $ ) = 1+-+--Q z u n OI,,

1F, =---se+s; (3)

In average current mode control, a possible currentcompensation transfer function is given by

k : .i+ - s ,(7)

This transfer function represents an integrator followed by a1ea.d-lag network. T o ensure stability, the zero should beplaced before the power stage filter frequency of the currentloop w here the phase shift of the integrator is canceled by thezero at half the switching frequency. Th e pole is normallyplaced above half the switching frequency to roll off the gainand thereby eliminate high frequency noise. Furtherm ore,this pole placement minimizes interaction with the current

By straightforward analysis, the control to output currentloop.loop transfer function is given bywhere

q (s)= R, .H, ( s ) . G,(s). , .F, (s) (1 1)

is the direct (forward) gain transfer function .'The loop transfer function for a 5kW converter werecomputed using MATLAB and the results are shown in Fig.7(see appendix A ).

Frequency ( Hz )100

- 02;1002a 200

U

c

-300101 102 103 104 105Frequency ( HzFig 7 Loop transfer function with average current control

It is clear from the above figure that the current loop canbe stabilized with proper compensator design and withoutslope compensation. In fact, the compensator gain can beadjusted in a similar fashion to adding slope compensation inpeak current mode systems. The gain margin of the currentloop is 13.5dB and the phase margin is 67.7" while thecurrent loop bandwidth is 1OkHz.

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The corresponding closed loop transfer function of thesystem is shown in Fig. 8 and the output current stepresponse is shown in Fig. 9.

1 0 2 1 0 3 IOH 105Frequency ( Hz

Frequency ( Hz )Fi g 8 Closed loo p transfer function with average current control

n o.os (1.1 0.15 0 2 (1.2s 0. 3Time (ni,xccs)Fig. 9: Output current step response with av erage current control

As expected, the output current overshoot is low (5%)and the system reaches steady state in 0.3ms.To verify the an alysis results, a SPICE average model ofthe converter was simulated. In this case, the system wasmodeled as two parallel connected buck converters with asingle output current loop. Th e resultant current looptransfer function is shown in Fig. 10while the step responseof the converter is shown in Fig. 11. It is clear from thesefigures that the simulation data match the analytical ones.Note also that the output filter current response is the sam e asthe total ou tput current.

III. Peak Current ode Control ImplementationIn applications where flux balancing is required on theprimary side of the transformer and dc blocking capacitorsare not used, peak current control can be adopted to ensurecurrent sharing between the two inductors.

Frequency In HrFi g 10 Loop transfer funcbon with average current control

c 80.00

40.00

01 I3000U D O O O U 1 S O O U 21O.OU 279.011

TIME In SecsFig. I I : Output currents step response with average current control

Unlike average current mode control, since peak currentcontrol regulates the peak of the inductor currents, theaverage output current may not be regulated. In this case, thenegative slope needs to be reconstructed or an outer averagecurrent loop can be used to regulate the output current.Th e implementation of the peak current loop control issimilar to that of average current control except that thecurrent sensing is do ne on the primary si de of the transformerand no dc blocking capacitor is used. In this case, the switchcurrents in one leg can be sensed using current transformers.This offers one more level of protection since an activeswitch current limit is implemented.The small signal equivalent circuit with peak currentmode control is shown in Fig. 12 [9]. Note that each ofinductor currents are driven at half the actual duty cycle ofthe converter. Hence, in the small signal model, the dutycycle D needs to be halved.

I IT i *Fig. 12 : Small signal model with peak current mode control

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In contrast to average current mode control small signalmodel, the peak current small signal model is more involvedin that the two co nverters are coupl~scl ia the comm on ou tputfilter capacitor. As a result , the sjstem can no longer bereduced to that of a single buck converter with peak currentcontrol. Th e equivalent control block diagram of the systernunder peak current mode is shown i n Fig. 13.

P' iJ

Fig. 13: Block diagram o f the peak current control modelThe transfer functions are computed using the averagePW M switch model as shown in Fig. 14 .

Fig.14: inal1signal cquivaleit circuit

The direct (forw ard) gain transfer function is given by [ 101

whereFij = i i / d j (14)

The cross coupled transfer function is given by

whereL,, = Ll I1L2R, = RNR ,R, = R + R,

Note that for L I = L ~ ,,, := F12 nd Fzz= F,,.To guarantee stability, each loop of the system must bestablc. Two current loops can be identified, a direct loopassociated with each current with its corresponding dutycycle and a cross coupled loop with th e ~ o ~ ~ l e r ~ e i ~ t a r yut ycycle. These loops are given by,

E k e , the negative sign of T12 and T implies that the phaselag at the cross over frequency should be less than 360" asopposed to the conventional 180".The control to output transfer function may be evaluatedas

H; Rb7 H e (23)Tlhe condition for instability of the control to output transferfunction (21) i s

which imposes an additional criteria for overall systemstability.

'The converter of appendix A was further analyzed usingMATLAB with peak current mod e control. Th e direct andcross coupled loop transfer functions are show n in Fig. IS.

Frequency ( Hz

io 102 I0 3 104 105Frequeiicy ( Hz

Fig.15: Direct and cross coupled loop gainsAs shown above, both loops can be stabilized with slopecompensation. In this case, the added slope, S e is assumed to

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be one half the down slope of the output filter inductorcurrents, Sf orL . ,LLAgain, note that the cross coupled loop phase margin is

computed in reference to 360".The stability condition of (24) was evaluated and theresults are shown in Fig. 16. The loop transfer function for asingle converte r case is overlaid for reference.

101 102 103 104 105Frequency ( Hz )

,""101 102 101 10a 105Frequency ( H z )

Fig. 16: Loop gains with peak current control, Se = -0.5 StAs expected, the loop transfer response of a single converteris stabilized with the addition of slope compensation. Unlikethe single converter case, the overall loop response of thesystem has higher gain and the phase characteristics revealthe presence of a low frequency pole and a high frequencyzero which reduces the relative stability of the of the system.To improve stability of the current loop, more slopecompen sation may be added. Figure 17 shows the loopresponse with add itional slope compensation where Se = -Sf.The resultant gain margin is 6.5dB while the phase margin is4.5'. The closed loop transfer function of the system isshown in Fig. 18.A SPICE average model of the converter was simulatedto verify the analy sis results presented abo ve. The systemwas m odeled as two parallel connected buck converters withtwo individual peak current loop s. Th e resultant closed looptransfer function is shown in Fig. 19, while the step responseof the converter is shown in Fig. 20. As shown in Fig. 19,the simulated loop response matches the analytical model ofFig. 18.

8060

5 40E:

,.-.d 20

0

10' 1 2 103 104 105Frequency ( H z )

1-1101 102 103 104 105Frequency ( Hz )

Fig. 17: Loop gains with peak current control, Se= -S t

10' 102 103 104 105Frequency ( Hz )

101 102 103 104 105Frequency ( Hz )

Fi g 18 : Closed loop gains with peak current control, Se = -St

40.00

30.00Ii am =- 20.00 :10ow

0

t I I I Iio 0 1K 10K

Frequency in Hz

Fig. 19: SPICE loop gains with peak current control, Se= -St

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-1111-2000u 6OOOU 101loIlU 14oou 18OOU

TIME in Secs

Fig 20 . Step re5ponse undcr peak carrent mode control

In this paper, the analysis and implementation of peakand average curre nt mode c ontrol teclhniques applied to a fullbridge PW M converter with two inductor rectifier werediscussed. The two inductor rectifk r circuit offers reducedsecondary side current rating compared to a full bridge orcenter tapped rectifier topology and is suitable for highcurrent applications. Furthermore, t h e two inductor rectifiercan be modeled as two parallel buck converters.In average current mode control, the two converters arereduced to a single converter o perating at twice the switchingfrequency. An integrator in series with a lead lag networkensuires stability o f the current loop. In contrast, the systemin peak cur rent mod e control cann ot b:: reduced to that of asin& buck converter. This is due io the presence of crosscoupling between the two converters for the output inductorsshare the sam e output filter capacitor. It has been shown thatunlike the single converter case, the relative stability of theoverall pea k c!Jrrcnt loop is less than that of th e single loop.As a result, m ore slope compensa tior, may be required toimprove the relative stability of the system.

N.H. Kutkut, D.M. Divan, R .W. Gascoigne, "A n Improved ZeroVoltage Switching Full Bridge DC/DC Converter IJsing A Tw oInductor Rectifier," IEEE Trans. on Industqr Applications, vol. 31, No.I , pp . 119-126, JadFeb 1995.Black, Jackson and Jackscon, Eiectricir)! mu' Mugnet i sm and Theirilppiiccrtion r Macinilan Co., 1919 , pp 4313-13 1.V. Vorpcrian, "Simplified Analysis of ITvM Converters Using theModel of PWM Switch: Parts I and 111, IEEE Trans. on Aerospacean d Electronic Systems, vol. 26, N o. 3, pp . 1.90-505, Ma y 1990.S . I-Isu, A.R. Brown, L. Rensink, R.D, Middlebrook, "Modeling andAnaly sis of Switchin g DC -to-D C Conve:rt:rs in constan t Frequen cyCurrent-Programmed Mode," IEEE PESC Conf. Rec., pp . 284-301,1979.1R.D. Middlebrook, "Topics in Multip1e-~.oOpRegulators and CurrentMode Programming," EE E PESC ConF. Rc,;., pp . 716-732, 1985.'W. Tang, F.C. Lee, R.B. Ridley, "Small-,Sipd Modeling of AverageCurrent-Mode C ontrol," E E E Trans. on Power Electronics, vol. 8, No .2, pp. 112-1 19, April 1993.

[7] R.B. Ridley, B.H . Cho, F.C.Lee, "Analysis and Interpretation of LoopGains of Multiloop-Controlled Switching Regulators," EEE Trens. onPower Electronics, vol. 3 , No . 4, pp . 489-498, Oct. 1988.K. Sin , C.Q. Lee, T.E. Wu, "Current Distribution Co ntrol of Para-llelConverters: P a t I," E E E Trans. on Aerospace and Electronic Systems,vol. 28, No. 3, pp. 829-840, July 1992.R.B. Ridley, "A New Continuous Time Model for Current ModeC,ontrol," IEEE Trans. on Power Electronics, vol. 6, pp . 271-280, April1991.

[IO] 3. Rajagopalan, K. Xing, Y. Guo, F.C. Lee, B. Manners, "Modelingand Dynamic Analysis o f Paralleled DClDC Converters with Master-Slave Current Sharing Control," IEEE APEC C onf. Rec., ppl578-684,1996.

[8]

[SI

The analyzed 5kW converter data:V,,:=320 V V,=4& v, I,=100 AR==0.55n a=2.5 fs=75 kWzLf=30PH c,,=0000pF R,=20 maR,=0.024 R,=0.045L2 V,=5V (ramp pcak)

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ieee current mode

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