Analysis of a Capacitive Loaded Buck ConverterMagnus Karlssonl , Torbjom Holmbergl , and Matz Lenells2

IEricsson AB, R&D Power Modules, Kalmar, Sweden

2The School of Mathematics and Systems Engineering, Vaxjo University, SwedenE-mail: magnus.karlsson@ericsson.com.torbjorn.holmberg@ericsson.com.andmatz.lennels@vxu.se

where

Fig. I.A principalcircuitmodelof a buck converterwhere the load is a resis­tanceR. Typicalvaluesof the components are given.

Input filter Output filter LoadFig. 2.Circuitmodelof the buck converter.

(4)

(2)

R2 = 4mO, R3 = 2mO

R4 = IOmO, Rs = 5mO

C2 = 150JlF,L = O.9JlH

Ru

First we investigate how the system is affected with a resistiveload, R. The unloaded model, assuming R = 00, yields an out­put LC-filter {L,C2 } that has a complex pole pair with its reso­nance angular frequency at 0)0 = 1/jLC; and a real zero atO)ESR = 1/(RsC2 ) · Hence, the control, Le., the duty cycle, tooutput voltage transfer function is

s + O)ESRG (s) = , (1)

D~ Vout s2+ 2<;0)0s + 0)6

II. THE CAPACITIVE LOADED MODEL

In order to obtain a more realistic model, the complexity of themodel has to be increased, as shown in Fig. 2.

~ = (5;RE)Jtis the relative damping ratio,

RE = R4 + DR 2 + (I-D)R3 , (3)

the switched average resistance, and D the duty cycle. Byincluding the resistive load R [3, 4], the resonance frequencyand relative damping ratio and changes to

0) = Io jLC;J(1 +Rs/R)/(l +RE/R)

L + C(RERs + RRs + RRE)<; = ----;:=-~====:::::=::::::=

2jLC;J(RE+ R)(R + Rs)

Typically R» max(Rs,RE) , therefore the resonance frequency isjust a few percent lower than 1/jLC; . The relative dampingratio is harder to analyze analytically, instead an example isgiven in Section lILA. The zero O)ESR does not depend on R .

I. INTRODUCTION

Switched DC/DC converters often use large banks of capaci­tors for maintaining a stable output voltage during load tran­sients or for keeping the voltage ripple at an acceptable level.The ASIC and FPGA supply voltages decrease with newCMOS processes, which leads to tougher requirements on cur­rent capabilities and voltage tolerance bands. A mix of differ­ent capacitor types is often used for optimizing the electricalperformance, and cost. In addition technical development hasimproved the electrical characteristics of the capacitors withhigher capacitance together with lower ESR [1, 2]. Hence, thecapacitive load can vary in a large range in terms of capaci­tance and ESR between different applications. The capacitiveload affects the system dynamics of the converter and must beconsidered during the control law synthesis. In literaturedynamical models of switched DC/DC-converters often onlyhave purely resistive loads, e.g. in [3, 4]. In [5, 6] forbiddenregions of the ratio of the converters output impedance and theload impedance are discussed. In [7, 8] multiple feedbackloops are used to obtain zero-output impedance converters,which virtually are load independent.

This paper presents a model of a buck converter where theload consists of a capacitor in parallel with a resistance and itanalysis how varying capacitive load affects the control loopstability. The obtained results can be generalized and applied toother converter topologies, which have an I.C filter at the out­put, e.g. forward, and half/full bridges.

A. The Resistive Loaded Model

A standard synchronous buck converter, see Fig. 1, is used asan example. The RDSon ofthe switch FET and the sync FET areR2 and R3 ' respectively. When a FET is turned off it is mod­eled as an open circuit. The output filter consists of an inductorL with its parasitic series resistance R4 and a capacitor C2with its ESR Rs .

Abstract - In this paper we study how the capacitive loadinfluences the system dynamics in switched DCIDC converters. Astudy is made about how the system dynamics depend on thevalues of the capacitance and ESR. Parallel coupling of capacitorsto achieve larger capacitance is studied from a control loopstability point of view. We define a capacitor with a givenminimum capacitance and a certain ESR range, which can beparalleled up to a given total maximum capacitance, where thecontrol loop stability margins are guarantied. This result is alsoextended for a mix of different capacitor types used in parallel.

Usually the DC/DC converter is loaded with a bank of capaci­tors with its equivalent capacitance C3 and ESR R7 • R6 andRo model the resistances in connection wires or PCB traces.

0.9

Fig. 4.Natural frequencies for the poles vs. load capacitance C3 .

The damping ratio of the poles vs. the load capacitance isshown in Fig. 5. The damping ratio of the complex pole pairincreases with increasing capacitance, green curve. Assume thecapacitance is larger than 3.5 mF. Then the damping ratio islarger than 0.7 which means that the overshoot during a tran­sient is hardly visible. At capacitances larger than 7 mF the sys­tem becomes fully damped with three real poles.

10

Real pole

Real pole

Fully dampedsystem

3 4 5 6 7Load Capacitance [mf'], ESR=IOmQ

Under damped system

Real pole

Complex pole pair

resistances and a slightly change of the resonance frequency.Hence, worst case with the smallest damping ratio is duringunloaded condition, i.e., R = 00.

B.System Poles vs. Load Capacitance

The natural frequencies of the resonant complex pole pair varywith the capacitive load as shown in Fig. 4, where theESR = lOmQ. With the natural frequency (On of a real pole p ,

we mean (On = -p which is analog with the defmition of thenatural frequency of a complex pole pair. For small capacitiveload the system has one real pole and one complex pole pair.The natural frequency of the real pole decreases about oneoctave with increasing capacitance .

III. ANALYSIS OF SYSTEM DYNAMICS

The order of the buck converter model, shown in Fig. 2, is four.The inductor L and one of the capacitors C2 or C3 , correspondto a complex pole pair or possibly two real poles, and the othercapacitor corresponds to a real pole. The values of the capaci­tances and ESR of the capacitors C2 and C3 determine whichone of the capacitors which corresponds to the pole pair andwhich one which corresponds to the real pole. The parasiticresistances ESR of the capacitors will introduce zeros in themodel. The pole and the zero of the model associated with theinput filter C) usually correspond to high frequencies and willtherefore not affect the control loop.

A.System Poles vs. Load Current

The load current determined by the resistive load R will affectthe system dynamics in the converter. For a capacitive load of470llF with an ESR of IOmQ, Fig. 3 shows the natural fre­quency and the damping ratio of the complex pole pair versusthe load current.

The inclusion of the current sink makes it possible to computeand analyze the output impedance of the system. A first orderinput filter capacitor C) with its ESR R) is also included. Val­ues of the parameters, introduced in the second version of theexample, are:Ro = O.lmQ, R) = 5mQ , C) = 30IlF, R6 = O.lmQ .

A.System Modeling

A non-linear switched state-space model of the buck convertersystem can be obtained by combining graph theory [9], passiv­ity techniques [10, 11], and handling switched electrical net­works as complementarity systems [12]. By a technique calledtime averaging, the switched model may be approximated by acontinuous time state-space model [13]. This model is herecalled the buck converter model. We will specially study thecontrol, i.e., the duty cycle, to output voltage transfer functionH(s) = HD~ V (s). Since we will use a digital control law, asampled moder'H(eJroT) , [14], will be used, where T is theswitch period.

~ "'~»,~ 6.9!s.s:

c, 6.8~

g 6.75z 0 2 4 6 8 10 12 14 16 18 20

0.8

0.7c

~~ 0.6

.~

23 0.5

0.4

0.3

0.2

103 4 5 6 7Load Capacita nce lmFJ. ESR=lOmU

0.1'--------"-_---'---_-L..-"----'_----'--_--'---_-'---------'_---'-------'o

Fig. 5.Damping ratio of the poles vs. load capacitance C 3 .

The Bode plots H(eJroT) dependency on load capacitance isshown in Fig. 6. Using load capacitances, 47 u, 470 u, 1 m,2 m(blue curves), 3.5 m (green curve), 7 m and 10 mF (red curves).The bandwidth of the system decreases with increasing capaci­tance. With increasing damping ratio follows that the phase

Fig. 3.Natural frequency and damping ratio of the poles vs.load current.

A larger load current increases the damping ratio at the reso­nance frequency due to larger voltage drops across the parasitic

....'.~""S 0.3

250.25

0.2o 2 4 6 8 10 12 14 16 18 20

Load current rA1

150100

Real po leExterna l capac itor

50

yFUllYdamped system

Co mp lex pole pairIntern al cap acitor & Indu cto r

K Comple x polc pai: : Exte rna l capa cito r &

Inductor

Real po leInternalcapac itor

IO- I L-__~-----.:._"'__ L- _____.J

o

10'

ESR [mO] of2 mF Capacitance

Fig. 8.Naturalfrequencies VS. ESR when C3 = 2mF

Using a 2 mF capacitive load, the natural frequencies vary withESR as shown in Fig. 8. When ESR < 30mQ the load capacitorcorresponds to the complex pole pair. The complex pole pairtransforms into two real poles when 30mQ:O:; ESR :0:; 40mQ .With ESR> 40mQ the internal capacitor is a part of the com­plex pole pair with a frequency >10kHz. The large load capac­itor corresponds to the lower frequency real pole which furtherdecreases its frequency with increasing ESR. With C3 > 900 J.l.Fthe system becomes fully damped when the ESR is in a certainrange. While C3 < 900 J.l.F the system always have a complexpole pair and one real pole.

The Bode plots H(ej OO T) dependency on ESR usingC3 = 470 J.l.F is shown in Fig. 9. The resonance peak isdecreased and the bandwidth is increased with increasing ESR ,blue curves. At a certain limit, in this case 65 mQ , green curve,the complex and the real poles have the same natural frequency,wherefore the system behaves like a Butterworth system, whichhas a smooth phase curve. With ESR> 65mQ , red curves, thereal pole caused by C3 does not affect Bode plots much,instead the complex pole pair caused by C2 and the inductorshows up at a higher frequency and consequently determine thesystem bandwidth . The gradients of the phase shift has a mini­mum when the ESR=65 rnQ.

10'

10'

IncreasingCapacitance

Butterw orth funct ion

Lc omPlex pole pairInterna l capac itor &Inductor

10° 10'Frequency [kHz]

Real poleInternal ca pacitor

Complex pole pairExterna l ca paci to r &Ind uctor

-200 L..-_~__",___~__",___~__":-10-1

10'

e - 50t.~ - 100

"i - ISO0..

By using a recommended minimum load capacitor with acapacitance value of approximately 2-3 times the internalcapacitance value the minimal damping ratio will be a certainvalue. Furthermore, the minimal frequency at which the phasecurve has dropped to low values will be above a certain value.Therefore, the requirement about load capacitor mentionedabove implies the control law may be substantially moreaggressive .

C.System Poles vs. ESR

The natural frequencies for the poles depend also on the ESR ,R7 , in the load capacitor. In the case of a load capacitance of470 J.l.F Fig. 7 shows the natural frequencies as functions of theESR. When the ESR < 65mQ , the larger load capacitance C3and the inductor correspond to the complex pole pair. The inter­nal capacitor C2 corresponds to the high frequency real pole,which approaches the complex pole pair with increasing ESR.With ESR>65mQ, the capacitors change roles, the internalcapacitor together with the inductor now correspond to thecomplex pole pair. With ESR=65mQ , the system behaves like aButterworth system with identical pole frequencies.

40 r-----~----~----.____,

curve becomes less steep around the resonance frequency. Thesystem bandwidth is determined by the dominant complex polepair.

Fig. 6.Bodeplots H(ej OOT) dependency on the load capacitance C3 .

10'10'Frequency [kHz]

- 20050 100

ESR [mQl of 470 IlF Capacitance

IO°L- ----'-- -'----- _

o 150

Fig. 7.Natural frequencies VS. ESRwhen C3 = 470 J.l.F . Fig. 9.Bodeplots H(ej ooT) dependencyon ESRwhen C3 = 470 J.l.F .

(7)

(9)

10'

--&- ESR 10m!!

---e-- ESR ioomrz

----e-- ESR 65mU

10'

10'

10'

10'Frequency [kHz]

- 150

';:;' - 50g

~--; - 100

£

Fig. IO.Systempolesnaturalfrequency vs. numberof 470 p,F loadcapacitorsin parallel.

Figure 11 shows the Bode plots for H(eJOlT) whenNE [1 ,2, 15,60] of 470p,F capacitors withESRtyp E {lOmQ, 65mQ, 100mQ}, with the colors red, blue,and green curves, respectively. When N ~ 3 the slowest pole ismonotonously decreasing with N, see Fig. 10. Hence, the sys­tem bandwidth decreases as well with N. The damping ratioincreases with N and thus the phase gradient decreases with N.The phase gradient also decrease with increasing ESRtyp .

When N = 1 the bandwidth has its maximum whenESRtyp = 65mQ, i.e., when all three poles has the same fre­quency. When ESRtyp < 65mQ the complex pole pair {C3,L}

becomes dominant and the damping ratio of the systemdecreases yielding a peak in the gain and a large phase gradient.When ESRtyp > 65mQ the real pole {C3,R7 } becomes domi­nant and determine the system bandwidth, the phase gradientdecreases, and the bandwidth decreases. Similar behavior isobtained for N = 2. Hence, the load capacitors ESRtyp playsan important role how the systems behaves when using only afew capacitors in parallel.

Fig. II.Bode plots H( eJOlT) dependency on the numberN of 470 p,F loadcapacitors in parallelwith differentESRtyp'

101

Number 0 1'470 ~lF capacitors in par alle l

increasing N, since the load on the internal C2 capacitordecreases.

30,-----~~~_._.,___~~~~-.---~~~,......-r----...,______,

20

~ 10

] 0·a Increasing number orcapacitors~ - 10

- 20

(6)

If we assume that we use identical capacitors with value Ctypand ESRtyp' we can solve for Z(s) yielding

ESRt 1Z(s) = =..:..:..:!.1:1+ __ •

N sCtypN

Hence, the total impedance is of order one and can be modeledas an equivalent single capacitor with a total capacitance Ctotwith ESRtot according to

c.; = NCtyp, and sss.; = ESRtypIN.

Consider the time constant 'ttot for the capacitor bankESRtyp

'ttot = CtotESRtot = NCtyp N = ESRtyp' Ctyp = 'ttyp' (8)

hence, it is independent on the number N and equal to the timeconstant 'ttyp for the single capacitor. Using capacitors with dif­ferent capacitance or ESR values will increase the order of theimpedance, see Section IV.C.

The natural frequencies of the poles versus the number N of470 p,F capacitors in parallel are shown in Fig. 10, for threedifferent values of ESRtyp E {lOmQ, 65mQ, 100mQ} , with thecorresponding colors red, blue, and green curves, respectively.The behavior using N < 3 depends on the load capacitorsESRtyp' When ESRtyp < 65mQ, the load capacitor and theinductor correspond to a dominant complex pole pair {C3, L} .With ESRtyp = 65mQ and N = 1 the system behaves almostlike a Butterworth system. When ESRtyp > 65mQ, the greencurves, the resistance ESRtot is so large so it blocks the currentto reach the load capacitor. Instead the complex pole pair corre­sponds to the pair {C2, L} . This was already shown in Fig. 7.

When N is slightly larger the resistance ESRtot does notany more block the current to reach the load capacitor, andtherefore the pair {C3, L} will correspond to the complex polepair. This will of course be even more true whenESRtyp < 65mQ. The natural frequency of the complex polepair decreases due to the increasing capacitance. Fig. 10 showsthat the relation

1 1 1(On = ~<=>log((On) = -ilog(LCtyp)-ilogN,

",LNCtyp

holds for an interval of values of N . The damping ratio of thecomplex pole pair increases with number N, as indicated inFig. 5. Using a sufficiently large number N a fully damped sys­tem with only real poles is obtained, this value of N is depen­dent on the ESRtyp' The real pole increases its frequency with

The dependency on ESR when the load capacitance isC3 = 2 mF, shows a similar behavior to the one found inFig. 9. With 30mQ ~ ESR ~ 40mQ, the system have three realpoles and the phase curve has the lowest gradient.

D.System Dynamics vs. Parallel Coupling a/Capacitors

A common way of increasing the capacitance is to use severalcapacitors in parallel. The reciprocal of the impedance for Ncapacitors in parallel including the ESR is described by

zfs) = i[ 1 IJ. (5)n= I ESRn + sC

10'

-- I ~ F

-- I OO~ F

-- 470~ F

--2m F-- I Om F-- 50mF

10'10'ESR m1l

10'Total capaci tance IJ-l F I

Fig. 13.Phasemarginvs. ESRtyp and Capacitance.

---e- 180JlF. 10m{2

---e---- 47 0JlF. IOmU

---e---- 1.5m F. IOmU

-- 180JlF. IOOmU

- 470JlF. I OOrnU

- 1.5mF. IOOmn

70

60

"0

60

40

140

120

130

120

140

';;;

~ 100c§

::'E

~ so

Fig. 14.Phasemarginvs. parallelingof N capacitorswith differentcapacitancesand ESRtyp-

By utilizing Eq. 7 and Eq. 8, capacitors outside the allowedESR tot range and lower capacitance limit can be used if the fol-

damping ratio decreases, yielding a decreasing phase margin.The phase margin increase with increasing capacitance due toincreased damping ratio of the system, in accordance withFig. 5. Hence, the minimum and maximum values of ESRtot 'together with the minimum capacitance value are importantfactors when designing the control law.

B.Design and Analysis for Parallel Load Capacitors

We use the same control law design strategy as described abovein the introduction to Section 4. Here Ctot = NCtyp' whereCtot e [Cmin, Cmaxl = [I80JlF, 30mF] andESRtot e [ESRmin, ESRmaxl = [lOmQ , 100mQl . The ESR minand Cmin correspond to an equivalent minimum time constant'tmin = CminESRmin' Figure 14 shows the phase margin versusthe total load capacitance using N capacitors in parallel withCtyp e {I80JlF, 470JlF, 1.5mF} , ESRtyp e {ESRmin,ESRmax} .The phase margin becomes limited by ESRmax using only a sin­gle capacitor, and by ESRmin when Ctot approaches Cmax'Using capacitors with Ctyp > Cmin yields a larger phase marginand the maximum total capacitance increases beyond Cmax'

15°r-;:= = = = = :;--- -.--- - - - - - ---c;::=--- - - i

10'Freq uency [kHz]

Decreasing ESR <5mQ20,--- - - - - - ----r'---r- - - - - - - - ...,------,

-200 L--~---~~..........,____--~ --_.........:"'_'_:_=

10°

Fig. 12.0pen loop Go(eJOlT) Bode plots dependency on ESRtyp using a

470 lIF load capacitance.

Figure 13 shows the phase margin versus ESR tot = ESR typ fordifferent values of the capacitance. When C3 e [Cmin, Cmax]one may use ESR typ e [2mQ, IOOmQ] . The phase marginincreases then ESRtyp increases up to about 30 mQ due to thatthe damping ratio of the resonance increases. Using a largerESRtyp the system changes its resonance frequency and the

"' 10 f------~~;;~E:::::::===~"'- r-o

] 0. ~

~ - 10

~

f - 150

'[ - 50

a,::£ - 100

IV. CONTROL LOOP DESIGN

The time discrete PID control law R(z) is designed for therange ESRtot e [ESRmin, ESR max] in the load capacitor whenC3 > O. Using phase margins requirement of 45 degrees forC3 = 0, and 60 degrees for the load capacitance in the range ofC3 e [Cmin, Cmaxl. The two real PID zeros are placed on thenatural frequencies for the complex pole pair when loaded withthe minimum and maximum capacitances with ESR min . Thegain is adjusted for fulfilling the phase margin requirementsunder the above specified component variations.

A.Design and Analysis for a Single Load Capacitor

In this design, we will use a single capacitor within the capaci­tance range [Cmin, Cmaxl = [470JlF,lOmF] and the ESR range[ESRmin, ESR max] = [5mQ, 100mQ]. Figure 12 shows a num­ber of Bode plots for the open loop transfer functionGo(eJOlT) = R(eJOlT)H(eJOlT) where the value ofESRtyp e {0.01, I, 5, 10,20,40 ,80, I50} mQ . The green curveshows the case when ESRtyp= 5mQ. Figure 7 shows that thenatural frequency of the complex pole pair is nearly constant aslong as ESR typ < 30mQ, and gradually increases its frequencywhen 30mQ < ESRtyp < 100mQ . This is in accordance with theplots of Fig. 12 where the resonance frequency changes verylittle when the value of ESRtyp is small. When the value ofESRtyp decreases the damping ratio decreases, hence the reso­nance peak increases. When the ESR gradually increases in therange 30mQ < ESR typ < IOOmQ the resonance frequencyincreases. When ESRtyp > 65mQ the smaller internal capacitorC2 and the inductor correspond to the complex pole pair. Whenusing a load capacitor of C3 = 2 mF, the behavior is similarbut the change in resonance frequency become larger.

VI. REFERENCE[I] Murata chip capacitors data sheet , www.murata.com/cap/index.html[2] OS-CON capacitors data sheet. www.edc.sanyo.com.[3] B. Johansson , "DC-DC converters , dynamic model design and experimen­

tal verification, " Dissertation LUTEDX/(TEIE-I042)/I-I94/(2004), Dep.Oflndustrial Electrical Engineering and Automation , Lund University,Lund, Sweden, 2004.

[4] Application Note 16: Digital-DCTM control loop compensation,www.zilkerlabs.com .

[5] S. D. Sudhoff, S. F.Glover, P. T. Lamm, D. H. Schmucker, and D. E. Del­isle, "Admittance space stability analysis of power electronic systems,"IEEE Trans. on Aerospace and Electronic Systems, vol. 36, no. 3, pp. 965­973,2000.

[6] X. Feng, 1.Liu, and F.C. Lee, "Impedance specifications for stable DC dis­tributed power systems," IEEE Trans. on Power Electronics, vol. 17, no. 2,pp.I57-162,2002.

[7] 1. D. Varga, and N. A. Losic, "Synthesis ofload-independent switchmodepower converters ," IEEE Industry Applicat ions Society Annual Meeting,vol. I , pp. 1128-1134, 1989.

[8] 1. D. Varga, and N. A. Losic, "Synthesis of zero-impedance converter,"IEEE Trans. on Power Electronics, vol. 7, no. I, pp. 152-170,1992.

[9] D. B West, Introduction to graph theory, Prentice Hall, 2001.[IO]R. Ortega, A. Loria, P. 1. Nicklasson , and H. Sira-Rarnirez, Passivity-based

ControlofEuler-Lagrange Systems, Springer, 1998.[II] A. van der Schaft, L2-Gainand PassivityTechniques in NonlinearControl,

Springer, 2000.[12]W. P. M. H Heemels, M. K. Camlibel , A. 1. van der Schaft, and 1. M. Schu­

macher, "Modeling, wellposedness and stability of switched electrical net­works," Lecture notes in computer science, vol 2623, pp, 249-266.Springer-verlag, 2003.

[13]R.D. Middlebrook, and S. Cuk, "A General Unified approach to modelingswitching converter power stages," IEEE Power Electronics SpecialistsConference Record, PESC-76 , pp. 18-34, 1976.

[I4]T. Glad, and 1. Ljung, Control theory, led., CRC, 2000.

V. CONCLUSION

In this paper we have modeled and analyzed the buck converterand how its capacitive load affects its dynamics. Not only thecapacitance value of the load, but also the ESR, is of majorimportance for the system dynamics.

Using a minimum recommended capacitance for the loadcapacitance that is 2-3 times the internal capacitance allowsusing a more aggressive control law. The minimum and maxi­mum ESR has also to be considered during the control law syn­thesis.

In the case for designing a control law for a wide range ofapplications, we define a typical capacitor with a specified ESRrange and a minimum capacitance . The minimum capacitanceand the minimum ESR corresponds to a minimum time con­stant, 't min . The typical capacitor can be paralleled up to a spec­ified total maximum capacitance . Capacitors with parametersoutside the specification can be used if some simple require­ments, which was given in the paper, are fulfilled. A largephase margin overhead is obtained between the extreme caseswith minimum and maximum total capacitance and ESR. Thiscan be utilized by paralleling capacitors with smaller time con­stants than t min . This makes it possible to design a low costcapacitor bank, by combining cheap capacitors with high costlow ESR capacitors and still obtain a good electrical perfor­mance.

(11)

(12)

(10)

---e--- n x Ctyp - low

---e--- n x Ctyp-low+12 x Caux

~ n x Ctyp-high

~ n x Ctyp_high+40x Caux

11 0

lowing criteria are fulfilled. Capacitors with capacitanceCtyp < Cmin can be used if NL owCap capacitors are used in par­allel with ESRtyp, where

ESRtyp ~ ; in , and NLow Cap ~ rCminl .typ Ctyp

Capacitors with ESRtyp > ESRmax can be used if N HighESR

capacitors are used in parallel, where

N > rESRtyp1 d C Cmin

HighESR - , an typ ~ N .ESRmax HighESR

Capacitors with ESRtyp < ESRmin can also be used if't min

Ctyp~ ESRtyp

capacitors are limited by the minimum time

,Fig. 15.Phase margins when using N of Ctypcapacitors in parallel

with M of Caux capacitors.

Hence, the Ctypconstant 't min .

100

70

C.Design and Analysis for Parallel Capacitors ofDifferentTypes

A low cost capacitor bank with good electrical performance isusually obtained by combining bulky cheap capacitors withhigh ESRtyp with more expensive high performance capacitorswith low ESRtyp values. Mixing capacitors increases the com­plexity of the transfer function H(s) by introducing one poleper time constant. In the former section it was shown thatbesides extreme cases an excess of phase margin is obtained.This can be utilized by adding M capacitors Caux in parallelwith N of Ctyp, which has a time constant 'ta < 't . •ux minFigure 15 shows two new plots and two old ones, see Fig. 14,of the phase margin vs. Ctot ' The first new plot shows when

Ct ot = NCtyp_low + 12MCaux' where

(Ctyp-Iow' ESRmin) = (180I!F, lOmQ) , and

(Caux,ESRaux> = {47I!F, 5mQ} . (13)

The second new plot shows when

Ct ot = NCtyp_high + 40MCaux ' where

(Ctyp-high' ESRmax> = (l80I!F, lOOmQ) . (14)

Hence, the larger phase margin using C typ with ESRmax can beutilized with a larger number M of Caux :

120i-:-------,..----r= = :::c:::c:= = = = :::;l