ISSCC95 / SESSIO RAT

TA 9.7: A Micromachined Low-Power TemperatueReguhted Bandgapvoltage Reference

Richard J. Reay, Emo H. Kiaassen, Gregory T. A. Kovacs

Center for Integrated Systems, Stanfwd University, stanford, CA

Improved voltage reference temperature stability is achieved with bandgap curvature compensation techniques and by regulating the temperature of a Zener diode reference with an on-chip heater. The heated substrate method achieves stable performance, rang- ing from 0.3ppmPC down to 0.OBppmPC 11-31. The disadvantages of this approach are power consumption up to 8OOmW, warm-up time up to 3 seconds, and specialized non-CMOS processes. This paper describes a temperature regulated bandgap voltage refer- ence fabricated in a foundry CMOS process. Using a simple post- processing micromachining step, a small portion of the chip containing the reference circuitry is thermally isolated from the rest of the silicon die. Having high thermal resistance and small thermal mass, the reference requires 200 times less power and warms up 150 times faster than previous heated-substrate cir- cuits. The reference, in a standard CMOS process, can be included on-chip with CMOS data converters and mixed-signal products.

A schematic of the bandgap reference core is shown in Figure 1. The circuit is designed for a commercial 2 p CMOS process with vertical npn transistors available in n-wells. A servo ampliiier adjusts the reference voltage until the currents in the two branches of the Brokaw cell are equal, thus generating the bandgap voltage output [41. A PMOS transistor connecting the positive supply to ground ads as a voltage-controlled heater. Resistors RI and R, are implemented on-chip with polysilicon. To demonstrate the micro- machined circuit concept, the reference core is integrated and an external CMOS chopper-stabilized amplifier is used for servo amplifier.

For efficient heating, the reference circuitry should be insulated from the substrate, minimizing heat-conduction losses. To accom- plish this, an electrochemical etch technique selectively etches exposed regions of the p-type silicon substrate, leaving n-wells suspended from silicon dioxide beams (Figure 2.) Due to the high thermal resistivity of the support beams, the circuits in these n- wells are thermally isolated from the substrate. Aluminum traces inside the oxide support beams connect the isolated circuitry to external circuits. This micromachining process is fuUy CMOS compatible,andcanbeusedatthewaferscaleorwithbondedparts having exposed metallization [51.

The reference core is contained in three closely spaced n-wells, Figure 1. The substrate region surrounding these n-wells is ex- posed silicon realized during the CMOS processing by superim- posing a device active area, contact cut, via cut and pad opening in the layout (Figure 3.) To etch the exposed substrate and undercut the reference circuitry, the packaged and bonded parts are sub- mersed in an 85°C solution of 10% tetra methyl ammonium hydroxide ("MAH) containing 32gA dissolved silicon. TMAH, a photo-resist developer is a safe, CMOS compatible silicon etchant that, when doped with silicon will not attack aluminum. To selectively etch the p-type substrate and passivate the n-wells, an electrochemical etch-stop was performed. The three n-wells are biased at 0.8V above the p-substrate, held at -1.6V relative to a silver/silver chloride reference electrode in the solution. After a three hour etch, the n-wells are completely undercut and lea suspended by two silicon dioxide beams (Figure 4.) Due to an etching phenomenon, the thin regions of p-substrate between n- wells are not etched, leaving single-crystal silicon thermal connec-

tions among the three n-wells. This creates a lumped thermal mass, ensuring isothermal operation of the reference circuitry.

The thermal properties ofthe reference structure are measured by heating the reference with the PMOS heater and observing the temperature by measuring the PTAT current of the bandgap cell. The thermal resistance is found to be 53,OOO0C/w, compared to a typical heated-substrate reference package resistance of 2OO0C/W E21. The higher isolation is attributed to the excellent insulation properties of the thin support beams, accentuated by the fact that they are 1 8 0 ~ long. The thermal time constant of the structure is measured to be 2.6ms, two orders of magnitude faster than previous heated references [2,3]. These thermal characteristics lead to signiscant reductions in heater power and warm-up time.

To measure the temperature coefficient of the reference voltage, a closed-loop control circuit uses external amplifiers (Figure 5.) In future designs, the control circuitry can be integrated along with the reference cell. As the temperature of the reference increases, the PTAT current in the reference cell rises, increasing the V, of MI. This temperature-dependent voltage is compared to a scaled version of the reference output voltage and used to drive the PMOS heater q), thus regulating the temperature of the reference. Alternatively, the PTAT current can be mirrored, passed through a resistor and directly compared to the reference voltage. The output voltage drift is measured from 0°C to 80°C with the heater offandwiththeheaterregulatingthetemperatureat 90°C(Figure 6). With incompletely characterized process and a non-optimized layout, the unregulated temperature coefficient is 40Oppml"C. With closed-loop temperature control, the temperature coefficient drops to 9ppmPC. By improving the open-loop performance of the reference, the temperature coefficient should be greatly reduced, approaching the performance of commercial heated-substrate references.

Combined with on-chip control amplifiers, the micromachined bandgap voltage reference is suited for low-power applications. Performance would be limited by the offset drift of the on-chip amplifiers, but this can be " i z e d by chopper stabilization or by including portions of the amplifier on the temperature-con- trolled membrane. Since the circuit is in standard CMOS and requires only 1Oomils2 die area, the reference can be included on the same chip with converters and other circuitry. Due to the low temperature coefficient only a single trim is required to adjust the absolute output voltage, obviating complex trims used in m a - ture-correckd references. Packaging-stress-induced drift errors

by the regulated nature of the reference and by the a r e " u e d reference circuitry not being in physical contact with the bulk Substrate.

Acknowledgments

R. Reay and E. Klaassen are supported by NSF Grad. Fellowships.

. . .

References

[ll LTZlOOO data sheet, Linear Technology Corporation, Milpitas, C h

L21 Dobkin, R., "Monolithic Temperature-Stabilized Voltage Reference with OdppmP Dxift," lsscC Digest of Technical Papers. pp. 108-109, Feb., 1976.

L31 Lade, D., et al., "6VTemperatue Regulatedvoltage Reference," IEEE

L41 Bmhw, k P., "A simple three terminal IC bandgap reference," IEEE J. Solid-state Circuits, vol. 9, pp. 388393, Dee., 1974.

L6l Reay, R., et al., 'Thermally and Electrically Isolated Single Crystal silicon stnretures in CMOS Technology," IEEE Electron Device Letters, YOL 16, pp. 399-401, Oct., 1994.

J. Solid-state Circuits, vol. 16, pp. 1070-1076, Dee., 1980.

ISSCC95 I February 16,1995 I Sunset A - D I 11:45 AM

n-wells

Oxide Support Beam Circuitry Oxide Passivation

Figure ! 3: See

Interconnect.

Oxide P a s s i v a h

Figure 1: Bandgap reference core circuit.

359.

Fieure 4:

n Fimre 2: Oblioue and side views of su

Scanning electron micrograph of the bandgap structure after

spended

etching, - - - showing single-crystal silicon suspended by oxide beams over a pit in substrate.

+ zv

I /

1.16

0 .- B 1.15 - 00

5

4

W 8 1.14

P 1.13

-well structure.

0

0 Regulation 011 (left axis) Regulation On (right axis)

0 0 0

n o 0 D 0 0

0 0

0

* *

1.1260 < a

a $

1.1255 ", 73

E. oa

s. 1.1250

v j ,

1.1245

0 20 40 60 80

Figure 6 Experimental results showing temperature Temperature (T)

Figure 5: Simplified schematic of temperature- regulated bandgap test circuit. drift with and without temperature regulation.

DIGEST OF TECHNICAL PAPERS 1 67

. ..

Figure 3: Micrograph of bandgap.

TP 10.1: A 64b 4-Issue Out-of-Order Execution RlSC Processor (Continued from page 171)

Acknowledgments

The authors acknowledge con- tributions of: C. Asato, S. Bagalkotkar, H. Berggren, J. Chang, A. Dharmaraj, M. Filardo, K. Furuya, M. Hakimi, C. Heron, C. Hong, D. Hanson, A. Ike, S. Iyen-gar, A. Katsuno, E. Li, S. Li,Y. Lu, T. Maruyama, M. Massing, M. Massoumi, 0. Moriyama, E. Opsasnick, H. Osone, M. Ramaswami, F. Sajjadian, N. Saxena, M. Shenoy, J. Szeto, and V. Thirumalaiswamy. A special thanks to M. Shebanow for sig- nificant contributions. They thank the Architecture, Design Verification, Technology, and Tools teams, and the support of Fyjitsu employees in Japan.

HaLis atrademarkofHaLCom- puter Systems, Inc. SPARC is a registered trademark of SPARC International, Inc. SPECint92 and SPECfp92 are trademarks of Standard Performance Evalu- ation Corp.

Figure 4: CPU die micrograph.

DIGEST OF TECHNICAL PAPERS 359