ieee journal of solid-state circuits, vol. 39, no. 10 ...€¦ · moonkyun maeng, soumya...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 10, OCTOBER 2004 1659

Realization of Multigigabit Channel Equalization andCrosstalk Cancellation Integrated Circuits

Cattalen Pelard, Edward Gebara, Andrew J. Kim, Michael G. Vrazel, Franklin Bien, Youngsik Hur,Moonkyun Maeng, Soumya Chandramouli, Carl Chun, Sanjay Bajekal, Stephen E. Ralph, Bruce Schmukler,

Vincent M. Hietala, Senior Member, IEEE, and Joy Laskar, Senior Member, IEEE

Abstract—In this paper, we present integrated circuit solutionsthat enable high-speed data transmission over legacy systems suchas short reach optics and electrical backplanes. These circuits com-pensate for the most critical signal impairments, intersymbol in-terference and crosstalk. The finite impulse response (FIR) filter isthe cornerstone of our architecture, and in this study we present5- and 10-Gsym/s FIR filters in 2- m GaAs HBTs and 0.18- mCMOS, respectively. The GaAs FIR filter is used in conjunctionwith spectrally efficient four-level pulse-amplitude modulation todemonstrate 10-Gb/s data throughput over 150 m of 500 MHz kmmultimode fiber. The same filter is also used to demonstrate equal-ization and crosstalk cancellation at 5 Gb/s on legacy backplane.The crosstalk canceller improves the bit error rate by five ordersof magnitude. Furthermore, our CMOS FIR filter is tested anddemonstrates backplane channel equalization at 10 Gb/s. Finally,building blocks for crosstalk cancellation at 10 Gb/s are imple-mented in a 0.18- m CMOS process. These circuits will enable10-Gb/s data rates on legacy systems.

Index Terms—Crosstalk cancellation, equalization, feedforwardequalizer (FFE), finite impulse response (FIR), near end crosstalk(NEXT), pulse-amplitude modulation (PAM).

I. INTRODUCTION

RECENT efforts to increase data throughput on legacymultigigabit systems face a number of challenges. It is

no longer sufficient to solely increase the speed of the ICsto achieve higher data rates. This is due to the emergence ofother constraints, specifically signal impairments arising fromthe transmission media, such as frequency-dependent loss andcrosstalk. Combinations of these impairments exist in a varietyof transmission systems. Two such systems considered here areshort-reach optics and electrical backplanes.

In short-reach optical links, transmission at speeds beyonda few gigabits is limited by differential modal delay (DMD).

Manuscript received January 23, 2004; revised April 29, 2004.C. Pelard, E. Gebara, A. J. Kim, M. G. Vrazel, F. Bien, S. Bajekal, and

B. Schmukler are with Quellan, Inc., Atlanta, GA 30308 USA (e-mail:[email protected]; [email protected]; [email protected];[email protected]; [email protected]; [email protected]).

Y. Hur, M. Maeng, S. Chandramouli, C. Chun, S. E. Ralph, and J. Laskarare with the School of Electrical and Computer Engineering, Georgia Instituteof Technology, Atlanta, GA 30332-0250 USA (e-mail: [email protected];[email protected]; [email protected]; [email protected];[email protected]; [email protected]).

V. M. Hietala was with Quellan, Inc., Atlanta, GA 30308 USA. He is nowwith Sandia National Laboratories, Albuquerque, NM 87185 USA (e-mail:[email protected]).

Digital Object Identifier 10.1109/JSSC.2004.833569

DMD arises from the excitation of multiple modes in the mul-timode fiber (MMF). The different modes propagate with dif-ferent velocities and arrive at the receiver at slightly differenttimes, causing detection errors. Because the received signal isa linear superposition of the different mode responses, DMDcan be well modeled as a linear filtering of the electrical signal[1] and can be compensated for by electrical equalization. Fur-thermore, the low-pass response induced by DMD varies unpre-dictably, even among fibers with the same bandwidth and launchconditions. Therefore, as described in [2] and [3], feedforwardequalizers (FFEs) are particularly well suited for compensatingDMD.

In addition to equalization, efficient modulation can beleveraged to overcome DMD-induced bandwidth limitations bydecreasing the signal spectral content. For example, four-levelpulse amplitude modulation (4-PAM) conveys two bits witheach symbol and thus requires half of the symbol rate ofconventional binary nonreturn-to-zero (NRZ) modulation. Asa result, 10-Gb/s throughput can be achieved by transmitting 5Gigasymbols per second (Gsym/s), as demonstrated in [4].

Similar to MMF, electrical backplanes exhibit frequency-de-pendent loss, however, the characteristics are different. Back-plane loss is often predominantly a function of trace geometryand board material as it is dominated by skin and dielectriclosses [5]. These losses are relatively simple to equalize due tothe smooth and predictable structure of the response. However,for thicker backplanes, the presence of open-ended vias at thelinecard-backplane interface can create reflections, which mayhave a significant impact on the channel response in the fre-quency range of interest. In such situations, the modeling flex-ibility of FFEs is needed to compensate for the unpredictablereflection effect [2], [6], [7].

Besides channel loss, backplanes are impaired by crosstalkinterference that can be severe enough to ruin the signal, even ifthe channel is perfectly equalized. Fig. 1 illustrates two commonforms of crosstalk that arise in the system interconnect. Theterm “far-end crosstalk” (FEXT) is used to describe interferencefrom an aggressor signal being transmitted on the same linecardas the victim signal. The term “near-end crosstalk” (NEXT) isused to describe the interference from an aggressor transmittedat the receiver end of the victim channel. NEXT impairment ismore severe than FEXT because the aggressor interference cor-rupts the victim signal after it has been attenuated on the back-plane channel, when it is most vulnerable. This is in contrast toFEXT where both the victim signal and the aggressor crosstalkare attenuated by the channel loss. Fortunately, the more severe

0018-9200/04$20.00 © 2004 IEEE

1660 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 10, OCTOBER 2004

Fig. 1. Illustration of how NEXT and FEXT can arise due to coupling in thebackplane-linecard connector.

NEXT problem can be solved by active crosstalk cancellation,which can be realized with the same building blocks as the FFE.

FFEs play a central role in enabling higher data rates onlegacy systems as evidenced by recent efforts in the literatureto equalize PMD in optics [8] and channel loss in backplanes[9]. Extending these efforts, we present solutions that combineFFE with multilevel modulation in optics and with NEXTcancellation on backplanes in order to further increase thechannel throughput.

The remainder of the paper is organized as follows. Section IIprovides a systems-level description of our proposed solutionsfor overcoming the barriers to increasing communications datarates. The case of short-reach optics is considered first, followedby backplane communications. Section III then presents the cir-cuits used to realize the solutions in Section II. Particular em-phasis is placed on finite impulse response (FIR) filters, whichserve as the centerpiece of both solutions. Two embodiments ofthis filter are presented. The first is fabricated in a 2- m GaAsHBT process and is used to process 5-Gsym/s throughput whilemaintaining the linearity of the signal, as required by the spec-trally efficient modulation used for the short-reach optics solu-tion. The second embodiment of the FIR filter is fabricated in0.18- m CMOS and is used to process speeds up to 10 Gsym/s.Section IV then presents system-level experimental results thatdemonstrate the benefits of the proposed solutions. The paperconcludes with Section V by summarizing the contributions anddiscussing future efforts.

II. SYSTEM ARCHITECTURE

In this section, we provide a system-level description of howthe data rate barriers described in Section I can be addressedusing solutions based on FIR filters. The two contexts of MMFand backplane communications are considered separately astheir specific characteristics are sufficiently different that theycannot be efficiently addressed with the same solution.

A. Short-Reach Optics

As stated in the Introduction, the primary speed impedimentin MMF is the bandwidth limitation associated with DMD dis-persion. The FFE is a natural choice for equalizing the highlyvariable DMD incurred over legacy MMF [2]. FFEs are FIR fil-ters [10] used for equalization. In an FFE, the received signalis delayed and summed according to controlled weightings toimplement an FIR filtering function. FFEs have a rich modeling

capacity inherited from the many degrees of freedom associ-ated with the independently controllable tap coefficients. Fur-thermore, the weighting coefficients can be controlled by adap-tive algorithms that fully exploit this richness.

The rich modeling capacity and adaptive capability of FFEsmake them a great choice for equalizing DMD. While one op-tion is to use an FFE specifically designed for 10 Gb/s NRZsignaling, in this paper, we consider how the problem can alter-nately be solved with a lower bandwidth FFE. Specifically, weconsider the combined use of an FFE and spectrally efficientmodulation. 4-PAM is selected over other advanced modulationschemes because it offers the most practical implementation. Toachieve 10 Gb/s over MMF, we use 4-PAM at a 5-Gsym/s rate.Thus, the equalizer only needs to equalize half of the bandwidththat would be required for NRZ [4].

Simulations show that a five-tap FIR filter with 100-ps spac-ings is adequate to compensate for the intersymbol interference(ISI) in a 150-m MMF link, using 4-PAM signaling to achieve10-Gb/s data throughput. Measurement results are presented inSection IV.

B. Backplanes

Backplanes suffer from two main impairments that preventhigher data rates on legacy systems, namely, channel loss andNEXT. Fig. 2 shows the channel response over a 26-in trace suf-fering primarily from skin and dielectric loss and, as a dashedline, the NEXT coupling response for a high-quality legacy in-terconnect that may be found in existing 1-Gb/s-channel back-planes. From this figure, it is clear that the NEXT has to be ad-dressed, as the channel SNR significantly decreases due to thecombined increase in channel loss and crosstalk coupling. Thechannel loss is addressed by using an FFE, while the NEXTproblem is addressed with active crosstalk cancellation basedon adaptive signal modeling.

The general idea of the crosstalk canceller can be describedas follows. As illustrated in Fig. 3, the canceller takes the sourceaggressor data and transforms the signal to emulate the couplingresponse incurred in the connector. The canceller also takes asa second input the aggressed victim signal. The emulated ag-gressor signal is subtracted from this aggressed victim to yieldthe canceller output, which represents the crosstalk-cancelledvictim signal. This compensated signal can now be passed to anFFE to correct for channel loss.

Before describing the crosstalk canceller in more detail, weconsider the modeling challenges involved. As can be seenfrom Fig. 2, the connector’s coupling response is highly erratic.Furthermore, the response is highly variable from one ag-gressor/victim pair to another. Given these two characteristics,the necessity of a flexible framework is obvious. To provide thisflexibility with minimal complexity, the proposed crosstalk can-cellation solution is based on the following modules illustratedin Fig. 3: a temporal alignment block, an FIR filter, a modelingassessment block, and a low-speed digital controller. The tem-poral alignment block is a variable delay element that delaysthe source aggressor data signal to account for the differenttrace lengths traversed by the real and modeled interferencesignal. The FIR filter serves to emulate the radiative couplingresponse within the connector. The output of the FIR filter then

PELARD et al.: REALIZATION OF MULTIGIGABIT CHANNEL EQUALIZATION AND CROSSTALK CANCELLATION INTEGRATED CIRCUITS 1661

Fig. 2. MeasuredS response of a backplane 26-in trace channel and a NEXTcoupling.

Fig. 3. Modules comprising the crosstalk canceller: temporal alignment delayblock, FIR spectral shaping filter, modeling assessment block, and a low-speedcontroller.

represents the emulated aggressor, which is subtracted fromthe received victim signal to yield the compensated signal. Themodeling assessment block monitors this compensated signaland provides a statistical measure of how much noise has beencancelled. A low-speed digital controller can then adjust thesettings of both the temporal alignment block and FIR filter tomaximize this statistical measure according to the collaborativesignal processing (CSP) framework in [2].

To demonstrate the power provided by the proposed equal-ization and crosstalk cancellation strategy, Fig. 4 shows simu-lated results for transmitting 5 Gb/s over a legacy 1-Gb/s back-plane. The channel and NEXT responses in Fig. 2 are taken asthe model for the backplane and interconnect. Fig. 4(a) showsthe eye diagram for the unequalized received signal with the ag-gressor turned off. Fig. 4(b) shows the eye diagram when an FFEconsisting of five taps separated by ps is applied toequalize the signal in Fig. 4(a). When the aggressor is activated,the signal fidelity is severely degraded, as illustrated by the eyediagram in Fig. 4(c), which shows an equalized signal subject

Fig. 4. Simulated eye diagrams for a 5-Gb/s signal communicated over a 26-inbackplane: (a) prior to equalization and without the effect of an aggressor, (b)after equalizing the unaggressed signal in (a) with an FFE, (c) after activationof an aggressor and application of the same FFE used in (b), and (d) withapplication of the proposed crosstalk cancellation solution to the signal in (c).

to NEXT. However, applying the proposed NEXT cancellationtechnique using a five-tap FIR filter with ps de-lays, the signal fidelity is dramatically restored to yield the eyediagram in Fig. 4(d) showing that 5 Gb/s is achievable using anFFE and active crosstalk cancellation.

While developed for 5 Gb/s, this approach is scalable tohigher data rates. In particular, it can be used to achieve10-Gb/s NRZ on most 1-Gb/s legacy backplane channels. Thecrosstalk cancellation strategy is also applicable to multilevelmodulation, so the combination of crosstalk cancellation with4-PAM can also be used to achieve 10 Gb/s over legacy 1-Gb/sbackplane channels.

Not only does the proposed crosstalk canceller enable5-Gb/s communication across the backplane, but it does so

without exorbitant complexity. In fact, the high-speed compo-nents of the proposed crosstalk cancellation technique are thesame as the basic components of an FFE, i.e., delay elements,summation nodes, and the FFE itself. Thus, the FIR circuitspresented in Section III can be readily leveraged to build thecrosstalk canceller.

III. CIRCUIT IMPLEMENTATION

FIR filters and their components lie at the heart of the equal-ization and crosstalk cancellation solutions proposed in the pre-vious section. Here, we focus on two implementations for FIRfilters. The first is a continuous-time 5-Gsym/s filter with fivetaps spaced 100 ps apart implemented in a 2- m GaAs HBTprocess. The second is a continuous-time 10-Gsym/s filter withfour taps spaced 33 ps apart implemented in a 0.18- m CMOSprocess. Both filters are fully differential circuits using lumpedLC delay elements and variable gain tap amplifiers. Further-more, CMOS building blocks are implemented for the NEXTcanceller IC, which include a 10-Gb/s summation node and a100-ps temporal alignment circuit.


Fig. 5. Photomicrograph of the five-tap GaAs FIR filter IC.

Fig. 6. Functional block diagram of the FIR circuit.

A. 5-Gsym/s GaAs FIR

The GaAs FIR filter consists of five taps with 100-ps spacing.Particular care is taken to design a highly linear filter. Specifi-cally, LC structures are used for delay elements and Gilbert cellmultipliers are used as coefficient amplifiers for their linear re-sponses. The delay elements and initial tap coefficients were de-termined from MMF impulse responses. A photomicrograph ofthe IC is shown in Fig. 5.

The functional block diagram and schematic diagram of the5-Gsym/s GaAs FIR are shown in Figs. 6 and 7, respectively.The desired tap spacings were realized with “mirrored” cas-cades of LC-delay elements at both the inputs and the outputsof the variable gain amplifiers (VGAs). Using 100 ps as an ex-ample of desired tap delay, the total tap delay was achieved byusing a cascade of 50-ps input delay elements and a cascadeof 50-ps output delay elements. One notable advantage of usingLC-delay elements is that the parasitic capacitances at the inputsand outputs of the VGAs are absorbed into the delay elements.

Fig. 7. Schematic diagram of the FIR filter.

The LC-delay lines are essentially high-order low-pass filtersand therefore exhibit relatively constant delay across the pass-band. Assuming constant and , the delay is approximately

(1)

where is the number of LC pairs.The characteristic resistance of the delay elements is ap-

proximately:

(2)

Both ends of the input and output delay lines must be termi-nated with in parallel with a capacitor of approximatelyfor the best frequency response. As mentioned earlier, the inputand output parasitic capacitances of the VGA can be absorbedinto the delay elements by subtracting the extracted parasiticvalue from the ideal value of .

The transistor-level circuit schematic of the VGA is shownin Fig. 8. The input is first buffered by high input-impedanceemitter follower amplifiers X1 and X2. The outputs of theemitter follower amplifiers drive transistors X3 and X4 of thestandard Gilbert cell multiplier circuit comprising transistorsX3–X8. The bases of the upper cross-connected differentialpairs are held at the desired dc gain constant. Since this circuit is


Fig. 8. Schematic diagram of the GaAs HBT variable-gain tap amplifier.

a four-quadrant multiplier, the gain coefficient can be negativeor positive. The input and output of the VGA are designed tohave high impedance so as to not disturb the input and outputdelay elements.

The resistor divider networks (see Fig. 7) scale theVGAs input drive voltages so that the desired coefficient controlrange is achieved (approximately 1 V). The output of theGilbert cell multiplier circuit is biased through and terminatedby the delay element cascade. The Gilbert cell multiplier will“see” a real load resistance of half the characteristic resistanceof the delay elements.

For this FIR filter, only one LC pair (second-order low-passfilter) per delay line was required for each tap to achieve the de-sired delay of 50 ps. The inductors were integrated spiral induc-tors with a nominal inductance of 2.7 nH. The actual loading ca-pacitor values were initially selected according to (1) to achievethe desired delay and then optimized in the actual design toachieve the best frequency response. As shown in Fig. 7, a seriesresistance was added to the loading capacitors to lower thephase peaking at the stopband edge. An additional shunt resis-tance was added to help counteract the effect of inductorloss, which makes the characteristic impedance of the delaylines complex. The addition of an appropriate shunt resistancecan cancel this effect and make the characteristic impedancereal at a target frequency. The input and output of the filter arebuffered by amplifiers to isolate the circuit from external influ-ences. Fig. 9 shows the measured delay for each tap. All gaincontrols are held at 0 V except for the respective channel undertest.

B. 10-Gb/s CMOS FIR for Backplane Channels

The implemented CMOS FIR consists of four taps with 33-psspacings. The delay elements and initial tap coefficients weredetermined from a next-generation backplane channel response.

Fig. 9. Measured delay for each tap of the GaAs FIR filter. All gain controlsare held at 0 V except for the respective channel under test.

Fig. 10. Photomicrograph of the 0.18-�m CMOS FIR IC.

Similar to the GaAs FIR, the delay lines are implemented via anLC ladder approach and its characteristic impedance is 100differential. The overall power consumption of the FIR circuitis 7.3 mW with 1.8-V power supply voltage. A photomicrographof the IC is shown in Fig. 10.

Fig. 11 shows the Gilbert-cell-based gain block of the FIR.For high-speed circuit operation, passive loads are chosen overactive loads. Despite the bandwidth advantage of the resistiveloads, the open drain connection of the conventional Gilbert-multiplier cells to the resistive load results in a voltage dropacross the passive load that increases linearly with the numberof taps. This forces the transistors (M1–M4) to operate in thetriode region. To increase the available voltage headroom ofthe conventional Gilbert-multiplier cells, a modified Gilbert cellwas used. The cell architecture uses a folded gain-control cir-cuit topology with folded bias current blocks (shown in Fig. 11).The mirror pole capacitance resulting from the proposed cell hasnegligible effect on the overall bandwidth performance sincethe gain-control signal path does not require high bandwidth.Transistors M5–M8 are used for active degeneration in orderto achieve highly linear gain performance [11]. Additionally,the gain control block includes a degeneration circuit (M11 andM12) for linear gain control.


Fig. 11. Modified Gilbert cell with folded gain-control block.

The final capacitance values of the LC delay are optimized byconsidering all input capacitances (gate-to-source capacitances)at each multiplier cell and the parasitic capacitance of the induc-tors. In this design, a 1.5-nH octagonal spiral inductor is usedand was designed using commercially available EM CAD tools.Particular care was taken in the analysis and optimization of theinductor geometry because of the critical nature of the element.The LC delay element has to provide accurate time delay overthe entire operating bandwidth ( 7 GHz) with minimal inser-tion loss per LC stage. The design calls for a high-speed accuratetime-delay structure.

Fig. 12 shows the measured delay for each tap in the filter.All gain controls are held at 0 V except for the respective tapunder test. Fig. 12 shows that a 33-ps tap spacing is achieved andFig. 13 shows the FIR measured input and output eye diagramsfor a 26-in backplane channel at 10 Gb/s, using a pseudorandombit sequence (PRBS) pattern.

C. 10-Gb/s NEXT Canceller Building Blocks for BackplaneChannels

The main function blocks for the NEXT canceller IC are theFIR filter, the summation node, and the fine-alignment delaylines. A four-tap FIR filter was implemented in 0.18- m CMOSand its performance was presented in Section II-B. In this sec-tion, we focus on the implementation in 0.18- m CMOS of thetwo other key building blocks for 10-Gb/s NEXT cancellation,namely the summation node and the fine-alignment delay line.

1) 10-Gb/s Summation Node: The summation node is com-posed of two VGAs that are tied together as illustrated in Fig. 14.

Fig. 12. Measured delay for each filter tap. All gain controls are held at 0 Vexcept for the respective channel under test.

Fig. 13. 10-Gb/s PRBS 2 � 1 eye diagram for the 0.18-�m CMOS FIR (a)before and (b) after a 26-in backplane channel.

Fig. 14. Schematic diagram of the 10-Gb/s summation node.

A photomicrograph of the IC is shown in Fig. 15. The archi-tecture of one of the VGAs is shown in Fig. 16. The VGA isdesigned to provide an externally adjustable gain controllablefrom 1 to 1 and support input signals with a bandwidth inexcess of 5 GHz for use in 10-Gb/s settings. Careful design stepsare taken in order to achieve this high-speed functionality with adynamic range of 500 mV peak-to-peak differential on both theinput and output signals. Specifically, the design distributes theVGA control headroom budget through the use of dual signalpaths and a tail current source using a pair of transistors (M1and M2). The degeneration resistor can then be tied betweenthe drains of M1 and M2 and thus do not reduce control head-room. Furthermore, the use of the pair of transistors as sourcedegeneration reduces the gain through each branch and helps toimprove linearity. The transistor size for the active load degen-eration was chosen such that the matching between input pairtransistors minimizes the offset error. The proposed design also


Fig. 15. Photomicrograph of the 0.18-�m CMOS 10-Gb/s summation nodeIC.

reduces parasitic capacitance by reducing the required transistorsize with lower current density in each branch.

This VGA is used on both the emulated aggressor lineand the received victim line forming the cancellation node incurrent domain similar to a current mode logic (CML) circuit.The VGA gain on the emulated aggressor line is adjustedso that the signal amplitude matches that of the aggressorincurred on the victim line. The VGA gain on the victimline is set to unity and is included so that the inputs to thecancellation node have identical electrical properties. This isdesired because the cancellation function is performed in thecurrent domain and thus current driver mismatch should beminimized. A load resistance of 50 is used in the biasingcircuit in conjunction with a bandgap reference voltage tocompensate for resistor process variations. This yields a robustdesign where deviations of 20% in the resistor valueaffect the output voltage swing by less than 3%.

Fig. 17 shows measured performance of the summation nodeusing 10-Gb/s patterns. The measurement is done using pulsetrains where each pulse has a duration of 100 ps. The pulsetrain applied to port 1 has a period of 800 ps, while the pulsetrain applied to port 2 has a period of 400 ps as illustrated inthe figure. The pulse trains are aligned temporally in order todemonstrate the cancellation capabilities of the IC. The signallabeled “OUT(1)” in Fig. 17 is the output signal of the summa-tion node when only the signal on port 1 is active. Similarly, thesignal labeled “OUT(2)” is the output of the summation nodewhen only the signal on port 2 is active. “OUT(2)” is the in-verted image of the pulse train applied to input 2 due to thenegation on port 2 as illustrated in Fig. 14. The “OUT(1 2)”signal in Fig. 17 shows the output of the summation node whenboth inputs are active. The gain of the VGAs were set so thatthe pulse train applied to port 1 cancels out exactly every otherpulse applied to port 2, therefore demonstrating the cancellationcapabilities of the IC.

Fig. 16. Schematic of the 10-Gb/s VGA.

Fig. 17. Summation node measured cancellation performance at 10 Gb/s.

Fig. 18. VGA measured differential output performance at 10-Gb/s usingPRBS 2 � 1. One of the summation node inputs is terminated into a 100-differential load.


Fig. 19. Photomicrograph of the fine-tune active delay line in 0.18-�m CMOS.

Fig. 20. Schematic of the active delay-line cell.

While Fig. 17 shows the summation capabilities of the de-vice, Fig. 18 is an eye diagram demonstrating the bandwidth ofthe summation node. Specifically, the eye diagram shows thesummation node output when a PRBS-23 10-Gb/s signal is ap-plied to port 1 with no input applied to port 2. The output eyeexhibits little ISI and jitter, thus demonstrating that the summa-tion node preserves the bandwidth of the input signal throughthe summation node. Consequently, the IC is capable of sup-porting data rates in excess of 10 Gb/s while consuming only57 mW of power. Additionally, the VGAs on the inputs of thesummation node, and thus the summation node itself, possess ahigh isolation of 31 dB.

2) 10-Gb/s Active Delay Line: An active delay-line teststructure is implemented on a 0.18- m CMOS process anda photomicrograph of the IC is shown in Fig. 19. The activedelay line test structure consists of eight cascaded amplifiercells accompanied with source followers for a 100-ps totaldelay, and Fig. 20 shows the schematic of the active delay-linecell. The propagation delay of the active delay line is generatedby the RC transient characteristic, i.e., the load resistances andparasitic capacitances of the differential amplifier pair cells. Itsdelay values can be changed by controlling the bias voltage ofthe active load transistor. The active delay-line approach can beused to replace the LC delay elements in the FIR filter. A favor-able characteristic of the active delay approach is that it does

Fig. 21. Fine-tune active-delay-line group delay versus frequency for differentcontrol bias.

Fig. 22. 10-Gb/s setup over 150-m MMF using 4-PAM signaling and a five-tapFIR filter as an FFE.

not introduce dc voltage drops across each stage and the overallbandwidth is maintained. The penalty over passive delay lines,however, is in increased power consumption. Finally, Fig. 21shows the performance of the active delay-line test structure.The group delay is drawn versus bandwidth for different controlvoltages and shows the fine-tuning capabilities of the circuit.

IV. SYSTEM MEASUREMENTS

System-level tests were performed to demonstrate increaseddata throughput on legacy gigabit systems. The experimentalsetups include: 1) 10-Gb/s throughput using equalization and4-PAM signaling over a 150-m MMF link and 2) 5-Gb/s equal-ization and NEXT cancellation on a 26-in FR4 backplane. Thesemeasurements validate simulations and circuit implementation.

A. MMF Link

The test setup shown in Fig. 22 was used to demonstrateequalization and 4-PAM signaling over MMF. Two indepen-


Fig. 23. Measured 4-PAM eye diagrams at 5 Gsym/s, PRBS 2 � 1 through150-m of MMF, (a) before and (b) after a five-tap GaAs FIR filter.

Fig. 24. Equalization and NEXT cancellation setup at 5 Gb/s over 20-in FR4backplane.

dent 5-Gb/s synchronous binary data streams are combined withthe proper amplitude and phase using passive components togenerate a four-level signal. The multilevel generator drives an8-GHz VCSEL, which launches the 850-nm optical signal into150 m of 500-MHz km MMF. The launch condition is over-filled and the launch power is 0 dBm. The signal is detected by a25-GHz PIN receiver. Fig. 23(a) shows the received 4-PAM eyediagram without equalization. The signal is severely impairedby ISI due to the DMD of the MMF, and it cannot be mitigatedwith additional optical power. Fig. 23(b) shows the same eyediagram after the five-tap GaAs FFE. The majority of the ISI isremoved, recovering the 4-PAM 10-Gb/s signal.

B. FR4 Backplane

The same five-tap GaAs FIR filter is also utilized to demon-strate both equalization and NEXT cancellation at 5 Gb/s ona 26-in FR4 backplane (20-in backplane trace and two 3-indaughter-card traces). We implemented the test setup shownin Fig. 24. A 5-Gb/s PRBS signal is sent through the 26-invictim channel and fed into the summation node where thenoise cancellation occurs. The output of the summation nodeis then fed into a five-tap GaAs FIR filter, used as an FFE, tocompensate for the channel loss. Another 5-Gb/s PRBS signal,used as the aggressor, is launched at the receiver end into thevictim’s closest adjacent channel in order to generate NEXT.A portion of the aggressor is tapped off and input to the NEXTcanceller. As discussed in Section II, it is critical to have aproper temporal alignment between the emulated crosstalksignal and the actual signal. This alignment is implementedwith cables and phase shifters.

The optimization of the setup is performed according to theCSP framework [2]. First, the optimal tap coefficients are foundfor the FFE, when the aggressor is turned off. Then, both PRBS

Fig. 25. Bathtub plots of a 5-Gb/s signal through a 20-in FR4 backplane:without an aggressor, with the aggressor, and with the aggressor cancelled.

sources are turned on and the tap coefficients of the cancellerFIR filter are set so that it minimizes the aggressor energy.

Bathtub plots, representing the bit error rate (BER) alongthe temporal axis of the eye diagram, are shown in Fig. 25.At 5 Gb/s, the 26-in FR4 backplane is equalized and yields aBER without any aggressor. From the bathtub plot, itis clear that the impact of a single NEXT aggressor is disastrouson the system, degrading the BER to . Our prototype canemulate this noise source and cancel it. The BER is improvedby five orders of magnitude BER , attesting that mostof the signal integrity is restored.

V. CONCLUSION

We have demonstrated the operation and utility of highlylinear, fully differential FIR filters fabricated in 2- m GaAsHBT and 0.18- m CMOS processes. The filters utilize variablegain tap amplifiers and a delay-line architecture consisting ofcascaded lumped LC delay elements. The FIR filter is a versatileand robust tool for maintaining signal fidelity in high-speed datatransmission systems, and in this paper we demonstrated its useas the central building block for both an FFE and a crosstalk can-celler, which are crucial to achieving higher data rates on legacysystems. For MMF applications, the FIR filter was used in con-junction with spectrally efficient 4-PAM signaling to demon-strate 10-Gb/s throughput across 150 m of 500 MHz km fiber.For backplane applications, the FIR filter was used to demon-strate the performance of both feedforward equalization andNEXT cancellation at 5 Gb/s. The FFE compensates for thechannel loss but cannot address crosstalk interference. To over-come this impairment, we presented a crosstalk cancellation so-lution, which leverages the FIR filter to emulate and remove theinterference. The use of the NEXT canceller improved the mea-sured BER by five orders of magnitude.

Our FIR design is readily applicable to other device technolo-gies and is scaleable for higher data rates. Of particular interestare CMOS equalizers and crosstalk cancellers for their reducedpower consumption and improved integration. We implementeda 10-Gsym/s FIR filter along with the other NEXT cancellerbuilding blocks in 0.18- m CMOS. These circuits will enable10 Gb/s over MMF and backplanes.


REFERENCES

[1] S. E. Ralph, K. M. Patel, C. Argon, A. Polley, and S. W. McLaughlin,“Intelligent receivers for multimode fiber: optical and electronic equal-ization of differential modal delay,” in Proc. LEOS, vol. 1, Nov. 2002,pp. 295–296.

[2] A. J. Kim et al., “Equalization and the evolution of gigabit communica-tions,” in Proc. IEEE GaAs IC Symp., Nov. 2003, pp. 193–196.

[3] H. Wu et al., “Integrated transversal equalizers in high-speed fiber-opticsystems,” IEEE J. Solid-State Circuits, vol. 38, pp. 2131–2137, Dec.2003.

[4] C. Pelard et al., “Multilevel signaling and equalization over multimodefiber at 10 Gb/s,” in Proc. IEEE GaAs IC Symp., Nov. 2003, pp. 197–199.

[5] J. T. Stonick, G.-Y. Wei, J. L. Sonntag, D. K. Weinlader, H.-J. Liaw, G.-J.Yeh, P. S. Chau, and G. Pitner, “An adaptive PAM-4 5-Gb/s backplanetransceiver in 0.25-/spl mu/m CMOS,” IEEE J. Solid-State Circuits, vol.38, pp. 436–443, Mar. 2003.

[6] Y. Hur et al., “4-PAM/20 Gbps transmission over 20-in FR-4 backplanechannels: Channel characterization and system implementation,” pre-sented at the IMAPS Advanced Technology Workshop, Palo Alto, CA,Oct. 2003.

[7] M. Maeng et al., “A 0.18 �m CMOS equalizer with an improved multi-plier for 4-PAM/20 Gbps throughput over 20-inch FR-4 backplane chan-nels,” presented at the IEEE Int. Microwave Symp., June 2004, Tu5A-2.

[8] B. Wedding, W. Pöhlmann, D. Schlump, E. Schlag, and R. Ballentin,“SiGe circuits for high bit-rate optical transmission systems,” in Proc.IEEE Int. Symp. Circuits and Systems, vol. 2, May–June 1999, pp.492–495.

[9] J. L. Zerbe et al., “Equalization and clock recovery for a 2.5–10-Gb/s2-PAM/4-PAM backplane transceiver cell’,” IEEE J. Solid-State Cir-cuits, vol. 38, pp. 2121–2130, Dec. 2003.

[10] E. Lee and D. Messerschmitt, Digital Communication. Boston, MA:Kluwer, 1994.

[11] F. Krummenacher and N. Joehl, “A 4-Mhz CMOS continuous-time filterwith on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 23, pp.750–758, June 1988.

Cattalen Pelard was born in Nantes, France, in1976. She received the Engineer degree in appliedphysics and the M.S. degree in microelectronicsfrom the National Institute of Applied Sciences(INSA), Toulouse, France, in 1998.

She has focused her research on developingtechnologies that increase the speed and reach ofbroadband communication channels. This includesthe design of microelectronic processes for VCSELintegration while at the Microelectronics ResearchCenter, Georgia Institute of Technology, Atlanta,

and the design of optical amplifiers while at JDS Uniphase, Eatontown, NJ,where she patented a technique to tune optical amplifiers based on temperaturecontrol. In 2001, she joined Quellan, Inc., Atlanta, where her current interestsinclude the development of alternate modulation techniques, equalization, andcrosstalk cancellation for multigigabit communications channels.

Edward Gebara received the B.S. (highest honors),M.S., and Ph.D. degrees in electrical and computerengineering from the Georgia Institute of Technology(Georgia Tech), Atlanta, in 1996, 1999, and 2003 re-spectively.

He is a currently with Quellan, Inc., Atlanta,developing new technology for next-generationadvanced interconnects, and he is also a ResearchEngineer with Georgia Tech, leading the MixedSignal team research efforts. The team researchinterest is to develop the foundation for alternate

modulation schemes (QAM, OSCM, etc.) and equalization techniques appliedto monolithic microwave IC designs for data and enterprise applications. Hiswork has resulted in more than 40 publications.

Andrew J. Kim received the B.S. degree from the Georgia Institute of Tech-nology, Atlanta, in 1995, and the S.M. and Ph.D. degrees from the Massachu-setts Institute of Technology (MIT), Cambridge, in 1997 and 2001, respectively,all in electrical engineering.

While pursuing his graduate and doctoral studies, he was a Research Assistantwith the Stochastic Systems Group, Laboratory for Information and DecisionSystems, MIT. In 2001, he joined the research staff of Quellan, Inc., Atlanta,where he develops circuit-oriented signal processing solutions for multigigabitcommunications channels. His research interest is in the field of stochastic signalprocessing with particular emphasis on high-speed communications, multiscalemodeling/processing, and radar image processing.

Dr. Kim is a member of Sigma Xi, Eta Kappa Nu, and Tau Beta Pi.

Michael G. Vrazel received the B.S. degree inphysics from the University of Alabama, Tuscaloosa,in 1997 and the M.S. degree in electrical engineeringfrom the Georgia Institute of Technology, Atlanta,in 2000, where he is currently working toward thePh.D. degree.

His area of research is in high-speed, align-ment-tolerant optoelectronic devices. Since 2001, hehas been employed at Quellan, Inc., Atlanta, devel-oping next-generation signal processing technologyfor high-speed communication systems.

Franklin Bien received the B.S. degree from YonseiUniversity, Seoul, Korea, in 1997 and the M.S.degree in electrical and computer engineering fromthe Georgia Institute of Technology, Atlanta, in2000, where he is currently working toward thePh.D. degree.

Currently, he is a Mixed-Signal IC DesignEngineer with Quellan, Inc., Atlanta, a companywhich develops high-performance analog semi-conductors that improve the speed and reach ofcommunication channels in consumer, broadcast,

enterprise and computing markets. His research interests include alternatemodulation schemes, crosstalk noise cancellation, and equalization techniquesfor 20-Gb/s+broadband communication applications.

Youngsik Hur was born in Seoul, Korea. He receivedthe B.S. and M.S. degrees in electrical engineeringfrom Hanyang University, Seoul, Korea, in 1993 and1995, respectively. He is currently working towardthe Ph.D. degree in electrical engineering at theGeorgie Institute of Technology, Atlanta, where hisresearch is focused on CMOS circuit implementationof an equalization and a noise cancellation techniquefor multi-Gb/s I/O applications.

He was with the Samsung Institute of AdvancedTechnology, Kiheung, Korea, and with Samsung

Electronics, Suwon, Korea, from 1995 to 2001. His current research interestsinclude channel characterization and system performance analysis of multilevelsignaling schemes for high-speed backplane I/O interconnections as well asmixed-signal circuit implementation of equalization and noise cancellationtechnique for broadband wired and wireless communication applications.


Moonkyun Maeng received the B.S. degree fromKwangwoon University, Seoul, Korea, in 1999and the M.S. degree from the Georgia Institute ofTechnology, Atlanta, in 2002, where he is currentlyworking toward the PhD degree in electrical engi-neering.

He joined National Semiconductor in 2003 for asummer internship, where he was involved in a Gi-gabit interconnection project focusing on circuit- andsystem-level study. His research interests are CMOSmixed-signal IC design such as FFE, DFE, CDR and

Gigabit transceivers for backplane and multimode fiber (MMF) channels. Hepreviously worked on VCSEL modeling and hybrid RF/digital communicationlinks over MMF.

Soumya Chandramouli received the B.S. degree inelectrical and computer engineering from LafayetteCollege, Easton, PA, in 1998. She is currentlyworking toward the Ph.D. degree in electrical andcomputer engineering at the Georgia Institute ofTechnology, Atlanta, where her research interestsinclude CMOS circuit design for comparators andanalog-to-digital converters with applications inGigabit transceivers.

Carl Chun was born in Honolulu, HI. He receivedthe B.S.E.E. degree from the University of Hawaii atManoa in 1994 and the M.S. degree in electrical en-gineering from the Georgia Institute of Technology,Atlanta, in 1999, where he is currently working to-ward the Ph.D. degree.

From 1998 to 2003, he worked for the fabless de-sign company RF Solutions as a Design Engineer. Hehas worked on wireless products ranging from WANreceivers to WLAN power amplifiers. His previousresearch interests include device modeling and dis-

tributed amplifiers. He is currently researching high-speed analog CMOS de-sign.

Mr. Chun is a member of Eta Kappa Nu.

Sanjay Bajekal received the B.S. degree fromBanglaore University, India, and the M.S. degreefrom Rutgers University, New Brunswick, NJ, bothin electrical engineering.

He has worked in the communications industrysince 1986. He is currently Director, Signal Pro-cessing at Quellan, Inc., Atlanta, GA. Prior toQuellan, he was with the StarCore Design Centerevaluating signal processing requirements of wire-line and wireless standards.

Stephen E. Ralph received the B.E.E. degree in elec-trical engineering degree (with highest honors) fromthe Georgia Institute of Technology (Georgia Tech),Atlanta, in 1980, and the Ph.D. degree in electricalengineering from Cornell University, Ithaca, NY, in1998. His research focused on the optical detectionof highly nonequilibrium transport in heterojunctiondevices.

In 1988, he began a postdoctoral position at AT&TBell Laboratories. In 1990, he joined the IBM T. J.Watson Research Center, Yorktown Heights, NY. In

1992, he joined the faculty in the Physics Department, Emory University, At-lanta, GA. In 1998, he became an Associate Professor of Electrical and Com-puter Engineering with Georgia Tech, where his work currently focuses on thedevelopment of ultrafast optical devices for telecommunications.

Dr. Ralph is a member of the American Physical Society, the IEEE Lasersand Elecro-Optics Society, and the Optical Society of America.

Bruce Schmukler earned the B.S., M.S., and Ph.D.degrees in electrical engineering from the Universityof Illinois at Urbana-Champaign in 1984, 1985, and1989, respectively.

He joined Watkins-Johnson in 1989. There heworked as a GaAs device engineer and designedvoltage-controlled oscillators and synthesizers forwireless communications. From 1995 to 2001, hewas with RF Micro Devices. He engaged in RFICdesign for the wireless and broadband markets inGaAs HBT, BiCMOS, and CMOS as a Design

Engineer and Design Manager. In 2001, he joined Quellan, Inc., Atlanta, GA,as the Director of Product Design Engineering. He is currently the leader of ICdevelopment, working on gigabit CMOS designs.

Vincent M. Hietala (S’85–M’85–SM’98) receivedthe Ph.D. degree in electrical engineering from theUniversity of Minnesota, Minneapolis, in 1988.

In 1988, after a short period as a Research Sci-entist with Honeywell, Inc., Minneapolis, MN, hejoined Sandia National Laboratories, Albuquerque,NM. As a Principal Member of Technical Staff inthe Microsystems Science and Technology Centerat Sandia, his research activities included customGaAs IC development, wireless systems, opto-electronic and high-speed electronic component

development (traveling-wave photodetectors, guided-wave photonic ICs,RTDs, and pHEMTs). In 2001, he joined Quellan, Inc., Atlanta, GA, wherehe is the Director of Advanced Circuit Development. His technical interestsinclude high-speed electronic and optoelectronic circuits and devices andmicrowave/millimeter-wave measurement techniques. His current primarytechnical activity is the development of custom ICs for high-speed telecommu-nication applications. He holds 13 patents and has authored and/or coauthoredmore than 100 technical papers/presentations.


Joy Laskar (S’84–M’85–SM’03) received the B.S.degree in computer engineering (highest honors)from Clemson University, Clemson, SC, in 1985 andthe M.S. and Ph.D. degrees in electrical engineeringfrom the University of Illinois at Urbana-Champaignin 1989 and 1991, respectively.

Prior to joining the Georgia Institute of Tech-nology (Georgia Tech), Atlanta, in 1995, he heldfaculty positions at the University of Illinois and theUniversity of Hawaii. At Georgia Tech, he holds theJoseph M. Pettit Professorship of Electronics and

is currently the chair for the Electronic Design and Applications TechnicalInterest Group, the Director of Georgia’s Electronic Design Center, andthe System Research Leader for the NSF Packaging Research Center. Hisresearch has focused on high-frequency IC design and their integration. AtGeorgia Tech, he heads a research group with a focus on the integration ofhigh-frequency electronics with optoelectronics and the integration of mixedtechnologies for next-generation wireless and optoelectronic systems. He hasauthored or coauthored more than 200 papers, several book chapters (includingthree textbooks in development), numerous invited talks, and has more than 20patents pending. His research has produced numerous patents and transfer oftechnology to industry. Most recently, his work has resulted in the formation oftwo companies. In 1998, he cofounded an advanced WLAN IC Company, RFSolutions, which is now part of Anadigics. In 2001, he cofounded a next-gen-eration interconnect company, Quellan, Inc., Atlanta, GA, which is developingcollaborative signal processing solutions for enterprise applications.

Dr. Laskar was the recipient of the Army Research Office’s Young Investi-gator Award in 1995, the National Science Foundation’s (NSF) CAREER Awardin 1996, the NSF Packaging Research Center Faculty of the Year in 1997, andthe NSF Packaging Research Center Educator of the Year in 1988. He was thecorecipient of the IEEE Rappaport Award (Best IEEE Electron Devices SocietyJournal Paper) in 1999, the faculty advisor for the 2000 IEEE MTT IMS BestStudent Paper award, the 2001 Georgia Tech Faculty Graduate Student Mentorof the year, recipient of a 2002 IBM Faculty Award, the 2003 Clemson Univer-sity College of Engineering Outstanding Young Alumni Award, and the 2003 re-cipient of the Outstanding Young Engineer of the Microwave Theory and Tech-niques Society. For the 2004–2006 term, he has been appointed an IEEE Distin-guished Microwave Lecturer for his seminar entitled “Recent Advances in HighPerformance Communication Modules and Circuits.”

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