ieee journal of solid-state circuits, vol. 43, no. 6, … · 1342 ieee journal of solid-state...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008 1341

Wideband Balun-LNA With Simultaneous OutputBalancing, Noise-Canceling and Distortion-Canceling

Stephan C. Blaakmeer, Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE,Domine M. W. Leenaerts, Fellow, IEEE, and Bram Nauta, Fellow, IEEE

Abstract—An inductorless low-noise amplifier (LNA) with activebalun is proposed for multi-standard radio applications between100 MHz and 6 GHz. It exploits a combination of a common-gate(CG) stage and an admittance-scaled common-source (CS) stagewith replica biasing to maximize balanced operation, while simul-taneously canceling the noise and distortion of the CG-stage. Inthis way, a noise figure (NF) close to or below 3 dB can be achieved,while good linearity is possible when the CS-stage is carefully op-timized. We show that a CS-stage with deep submicron transistorscan have high IIP2, because the cross-term in a two-di-mensional Taylor approximation of the � � charac-teristic can cancel the traditionally dominant square-law term inthe � � relation at practical gain values. Using standard65 nm transistors at 1.2 V supply voltage, we realize a balun-LNAwith 15 dB gain, NF 3.5 dB and IIP2 �20 dBm, while simul-taneously achieving an IIP3 0 dBm. The best performance ofthe balun is achieved between 300 MHz to 3.5 GHz with gain andphase errors below 0.3 dB and 2 degrees. The total power con-sumption is 21 mW, while the active area is only 0.01 mm�.

Index Terms—CMOS integrated circuits, distortion canceling,linearity, low noise, low-noise amplifiers (LNAs), low-power elec-tronics, noise canceling, noise cancellation, wideband LNA, wide-band matching.

I. INTRODUCTION

UPCOMING software-defined and multi-standard radio ar-chitectures may cover all major communication bands inuse today up to 6 GHz [1]. This puts interesting demands on theradio and its low-noise amplifier (LNA). The wanted frequencyspan can be chopped into smaller bands which then can be pro-cessed by several dedicated, possibly tuned, LNA circuits. Theother extreme is a single LNA, which then obviously needs tohave wide bandwidth. In contrast to a multi-LNA solution, thesingle wideband LNA is flexible and efficient in terms of area,power and costs. Single-ended input LNAs are preferred to saveI/O pins and because antennas and RF filters usually producesingle ended signals. On the other hand, differential signalingin the receive chain is preferred in order to reduce second-orderdistortion and to reject power supply and substrate noise. Thus,at some point in the receive chain a balun is needed to convertthe single-ended RF signal into a differential signal. Off-chip

Manuscript received July 23, 2007; revised March 4, 2008.S. C. Blaakmeer, E. A. M. Klumperink, and B. Nauta are with University of

Twente, CTIT Institute, IC Design Group, Enschede, The Netherlands (e-mail:[email protected]).

D. M. W. Leenaerts is with NXP Semiconductors, Research, 2525 AE Eind-hoven, The Netherlands.

Digital Object Identifier 10.1109/JSSC.2008.922736

Fig. 1. The basic common-gate–common-source topology in which the noiseof the CG-transistor can be canceled.

baluns with low losses are typically narrowband so that severalbaluns would be required in case of wideband operation. On theother hand, wideband passive baluns typically have high loss,degrading the overall NF of a receiver significantly.

Combining the balun and LNA functionality into a single in-tegrated circuit seems an attractive option to realize a widebandlow-noise receiver front-end. However, only a few CMOS wide-band LNA-balun combinations with sufficient low noise figurefor multiband receivers (3–4 dB) have been published [1]–[3].These circuits all exploit the noise canceling topology publishedin [4, Fig. 4b], shown in Fig. 1. This is one of the noise can-celing topologies discussed in [5]. Although these circuits havea single-ended input and differential output, the (im)balance ofthe output signal is not reported. We will show that this imbal-ance can be significant, e.g., about 6 dB in [1, Fig. 8a]. Nextto this, the circuits in [1]–[3] all use integrated inductors. Asin newer CMOS technologies the area-costs increase, area-con-suming integrated inductors become increasingly expensive. Fi-nally, we prefer to use baseline transistors at the standard supplyvoltage of 1.2 V instead of thick oxide transistors at 1.8 V [2] or2.5 V supply [1]. This is challenging with respect to achievingsufficient gain and good linearity.

In this paper, we present an inductorless balun-LNA with awell-balanced output signal, and will show that it can achievewideband amplification at low noise in a baseline 65 nm CMOSprocess with standard 1.2 V supply voltage, while also achievinggood linearity. The measurements on this circuit were publishedin [6]. This paper gives an in-depth analysis of the design op-tions, the noise behavior and distortion behavior of the usedcircuit topology. Furthermore, to the authors’ knowledge, thisis the first paper in which it is recognized that cross-terms inthe characteristic of modern submicron CMOS

0018-9200/$25.00 © 2008 IEEE

1342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008

Fig. 2. Small signal equivalent of a CG-stage.

transistors can be exploited to obtain an amplifying stage withlow second-order distortion.

The balun-LNA circuit topology is depicted in Fig. 1. Thiscommon-gate (CG) stage in parallel to a common-source (CS)stage is a well-known structure. Actually, there are at least 15 to20 year old references [7], [8, Figs. 2 and 3], and possibly evenolder ones. Later, this structure has been used in the “micro-mixer” circuit [9] and the LNA in [1]. However, all these circuitsuse CG and CS devices with identical size and bias. As will beshown in Sections II and III, identical devices cannot simulta-neously bring the benefits of output balancing, noise cancelingand distortion canceling. This paper provides insight in circuitdimensioning trade-offs and reveals new ways to exploit the cir-cuit to maximize performance. To this end, Section II derivesconditions for simultaneous output balancing, noise cancelingand distortion canceling. Section III details the noise analysisand motivates why appropriate scaling of the CS-stage is neededto exploit noise canceling most effectively and obtain a noisefigure in the order of 3 dB or lower. Apart from noise, the circuitalso simultaneously renders distortion canceling of the (CG-)matching-device nonlinearity [4]. However, to benefit from this,the CS-stage needs to have low distortion too. Therefore, weanalyze distortion in detail in Section IV, focusing on shortchannel devices. The distortion generated by these devices isnot only due to nonlinearity of their transconductance andof their output conductance , but also due to the depen-dence of on the drain-source bias voltage. We will show thata (cross-) term describing this dependence can be used to cancelthe dominant second-order distortion due to . Together withthe distortion canceling of the CG-stage this results in a highoverall IIP2. In Section V we describe the actual balun-LNAcircuit design, to validate theory and set an expectation for themeasurements. Section VI presents measurements and bench-marks the LNA to previous designs, while Section VII presentsa summary and conclusions.

II. SIMULTANEOUS BALANCING ANDNOISE/DISTORTION CANCELING

In the sections below we will briefly derive the conditionsfor simultaneous balancing, noise canceling and distortion can-celing. We will neglect capacitive effects for simplicity, andverify the validity of this assumption later via measurements.

A more detailed discussion on high frequency limitations androbustness for component variations can be found in [5].

A. Balancing (Balun Operation)

The common-gate stage in Fig. 2, biased with a currentsource, has a straightforward relation between its voltage gain

and its input impedance . The signal currentflowing through the load resistor has to be equal

to the signal current flowing at the input , as there is noalternative path to ground. Thus,

(1)

As a result, the input impedance of the CG-stage can be ex-pressed as

(2)

For an ideal transistor, having infinite output resistance, thisis obvious. In that case the input impedance can be written as

and the gain equals .However, (1) and (2) are equally valid when the finite outputresistance and the body-effect of a real transistor are taken intoaccount.

For an impedance match at the input, the input impedance ofthe CG-stage should equal the source resistance ,thus the gain of the CG stage becomes

(3)

To create a balun, the gain of the CS-stage in Fig. 1 should beequal, but have opposite sign, thus,

(4)

B. Noise Canceling

The noise generated by the CG-transistor in Fig. 1 can berepresented by a current source . This current generates botha voltage at the input-node and a fullycorrelated anti-phase voltage at the CG-output

. The factor equals the voltage division betweenthe input resistance and the source resistance ,which equals 1/2 in case of impedance matching:

(5)

The noise at the CS-output equals the CG-output noise, when the CS-gain

satisfies (4). Thus, the noise contribution of the CG-transistorcan be canceled, as it becomes a purely common-mode signalat the differential output . This proofs that simultaneouslybalancing of the output signal and noise canceling is obtained.

C. Distortion Canceling

As derived in [4], not only the noise of the impedancematching device is canceled, but also its nonlinearity, assuming

BLAAKMEER et al.: WIDEBAND BALUN-LNA WITH SIMULTANEOUS OUTPUT BALANCING, NOISE-CANCELING AND DISTORTION-CANCELING 1343

it can be modeled as a current source between drain and source,controlled by the gate-source voltage. We will take this onestep further here, by also taking into account the influenceof the drain-source voltage on the drain current. This allowsthe modeling of the nonlinear output conductance and othersecond-order effects like Drain Induced Barrier Lowering(DIBL), which become more prominent in modern CMOSprocesses.

Fig. 2 shows a model of the CG-stage. Weakly nonlinearbehavior is assumed, modeled by a drain-source currentwhich depends nonlinearly on both voltage variations and

around their DC bias points.1 The source signal causesa nonlinear drain-source current which is converted intoa nonlinear voltage at the input via the (linear) sourceresistor . The nonlinear input voltage can be writtenas a Taylor expansion of the signal source voltage :

(6)

where the ’s represent Taylor coefficients and contains allunwanted nonlinear terms and the first Taylor coefficientis defined in (5).

The output voltage of the CG-stage (see Fig. 2) can be writtenas

(7)

where (6) is used. The output voltage of the CS-stage can bewritten using (4) as

(8)

The difference in sign of the wanted signal and unwantedsignal in (7) and (8) can be exploited: after subtraction onlythe linear signal remains

(9)

In conclusion, all noise and distortion currents generatedby the CG-transistor can be canceled, irrespective whetherproduced due to nonlinearity of the transconductance or non-linearity of the output conductance. The gain required in theCS-stage to cancel the distortion products of the CG-transistorequals the gain required to obtain output balancing, leading tothe conclusion that simultaneous balancing and cancellation ofunwanted noise and distortion currents of the CG transistor ispossible. As the distortion due to the CG-transistor is canceled,while is normally quite linear, the CS-stage will determinethe overall linearity of the complete LNA. The linearity of theCS-stage will be analyzed in Section IV-B. The final noiseis determined by together with the CS-stage, as will beshown in the next section.

III. NOISE ANALYSIS

In this section, we analyze the noise figure of the basic CG-CSLNA (Fig. 1) for three different design options. To simplify

1Also the body-effect can be accounted for, by observing that � � ��for a CG-transistor with its bulk node �� connected to ground.

the calculation, transistors are assumed to have infinite outputimpedance and the bias current source of the CG-transistor isassumed to be ideal. Furthermore only the thermal noise of theresistors and of the transistors is takeninto account assuming , which is known to be opti-mistic for short channel devices. These assumptions will over-estimate the gain and underestimate the NF. However, the calcu-lation is useful to compare the different design options and sim-plifies comparison to previously published results using similarassumptions. The output noise power of the circuit elements inFig. 1 can be calculated, and divided by the noise contributionof the signal source, leading to the noise factor:

(10)

where the second part is the contribution from the CG-transistor,the third part from the CS-transistor and the last part from theload resistors, while the voltage gain equals

(11)

Three different design options of the CG-CS circuit are nowconsidered, as follows.

1) The transconductances of the CS and CG transistors areequal and the load resistors are equal, thus:and (the traditional way to implement anactive balun [7], [8], using a CG-CS amplifier).

2) The transconductance of the CS transistor is times biggerthan the CG-transconductance and the load resistors areequal, thus: and (designoption used in [1]).

3) The CS-transconductance is times bigger than theCG-transconductance and the CS-resistor is timessmaller than the CG-resistor, thus: and

(characterizes the design presented in thispaper).

The ratio of the voltage gain of the CS- and the CG-stage isdefined as the gain imbalance:

(12)

The noise figure, voltage gain and gain imbalanceof the three design options are plotted versus the

impedance scaling factor in Fig. 3. In all three cases theCG-transconductance is assumed to be: , tohave input impedance matching and to have areasonable gain of the CG-stage.

Option 1) gives horizontal lines, as it does not depend on thefactor . The NF equals 3.4 dB, the voltage gain 18.1 dB (8 )and the output signal is perfectly balanced dB .Although the noise of the CG-transistor is fully canceled, thiseffect is not exploited to achieve a NF below 3 dB. The noisegenerated by the CS-stage is significant because of its low


Fig. 3. Noise figure (NF), voltage gain �� and gain imbalance �� versus impedance scaling factor ‘�’ for three different cases.

transconductance and the voltage division of1/2 by and magnifies its contribution.

Option 2) shows a decreasing NF and an increase in voltage-gain with increasing . These two positive effects are howevercountered by an increase in gain imbalance. As increases,the voltage gain of the CS-stage gain increases whereas theCG-voltage gain remains constant.

The last option, 3), shows an even faster decrease of NFthan in option 2). In contrast to option 2), the noise of theCG-transistor is fully canceled. Next to this, the contribution ofthe CS-transistor decreases with a factor for increasing ,whereas in option 2) this contribution decreases at a rate slowerthan . The voltage gain remains constant for option 3). Boththe transconductance and the resistance of the CS-stage arescaled simultaneously (admittance scaling [10]). Thus the gainof the CS-stage remains constant and no gain imbalance occurs,i.e., the balun functionality is maintained for all values of .

Now some more attention is given to design option 2)as published in [1]. Both in the calculation above and in[1] the load resistors have a value of .The transconductance-scaling factor in [1] is estimated tobe in the range –3, using the square-law MOS-model

. This translates into a gainimbalance between CG- and CS-stage of 6–9.5 dB and (10)gives a NF between 2.8 and 2.5 dB. The remarkably low NFreported in [1, Figure 8b] of about 2.2 dB is a simulation resultwhere is assumed (instead of , or higher) [11].In the abstract of [1] a much higher NF of 3–3.5 dB is given.

Overall, we conclude that admittance scaling of the CS-stage(option 3) is the best way to achieve low noise figure in theorder of 3 dB or below, while simultaneously achieving goodoutput balancing. It is possible to get more gain using option 2

[1], but this comes at the cost of suboptimal noise behavior andsignificant unbalance in the output signal.

IV. LINEARITY ANALYSIS

In this section we will analyze the nonlinearity of thebalun-LNA proposed in the previous section and see howwe can exploit the distortion cancellation property. However,before we do so, we first want to introduce the IIP2 problem ofwideband LNAs.

A. Linearity Requirements for Wideband Receivers

Like a narrowband zero-IF or near zero-IF receiver, awideband receiver is sensitive to the second-order intermod-ulation product generated by an AM modulated carrier viaAM detection. However, a wideband receiver may also sufferfrom second-order intermodulation generated by interferersthat have a sum or difference frequency equal to the wantedRF-input signal. The response to a modulated carrier can besuppressed by placing a high-pass filter (i.e., AC-coupling)between the LNA-output and mixer-input and by driving anddesigning the mixer in a well-balanced way [12]. However,the intermodulation product generated at a frequency equal tothe frequency of the wanted signal cannot be separated fromthe signal. Especially standards that operate on large band-widths, like DVB-H (470–862 MHz) [13] or WiMedia UWB(3.1–10.6 GHz) [14], have a high probability that a certaincombination of interferers renders an in-band intermodula-tion product. A receiver designed for these standards shouldhave an LNA with sufficiently high IIP2 (and IIP3) in orderto handle strong interferers like WLAN (IEEE 802.11a/b/g)and the GSM standards. The required intercept points dependstrongly on the assumed interferer scenario and the assumed


amount of pre-filtering of the interfering signals. For a Wi-Media UWB receiver the required IIP2 is above 20 dBm andIIP3 above 9 dBm as derived in [15, sec. II]. For a DVB-Hreceiver, consider a GSM interferer (1.8 GHz, 30 dBm at0.2 m distance) and a WLAN interferer (2.4 GHz, 20 dBmat 1 m) that generate second-order intermodulation productin the DVB-H band at 600 MHz. The received interfererpower levels will be 7 dBm (GSM) and 20 dBm (WLAN).For a decrease in sensitivity of 3 dB, the maximum allow-able interference level in a DVB-H receiver is 105 dBm[13]. Without filtering the required IIP2 would becomeIIP2 dBm .Assuming that both (out-of-band) interferers can be filteredwith 35 dB attenuation brings the required IIP2 back to a morerealistic value of 22 dBm.

B. Distortion of the CS-Stage

As the distortion of the CG-stage can be canceled in theparallel CG- and CS-stage amplifier (Section II-C), the dis-tortion performance of the total amplifier is determined bythe distortion behavior of the CS stage. For distortion calcula-tions often only the nonlinearity of the transconductance of atransistor is taken into account. However, as in [16], [17], wefind that the nonlinearity of the output conductance cannot beneglected anymore in modern CMOS processes. The drain cur-rent as function of the gate-source voltage and thedrain-source voltage can be written as a two-dimensionalTaylor approximation:

(13)

where the Taylor coefficients can be derived from the largesignal relations between , and :

(14)

Notice that in (13) not only depends on powers of andbut also on cross-terms ( , , etc.) of and . The cross-term can be described as the dependence of the transconduc-tance on the drain-source bias voltage. One of the rea-sons for this dependence is the drain induced barrier lowering(DIBL) effect. The terms , , etc. are higher order deriva-tives of . The cross-terms will prove to be very important forthe linearity in modern short-channel CMOS processes. In [18]the importance of these cross-terms was shown for MESFETtransistors, which have linearity characteristics that are some-what similar to MOSFETs. The linearity of a resistively loadedCS-transistor ( and in Fig. 1) is calculated. The varia-tion of the drain source voltage is set by the output currentof the transistor and the load resistor . Using this and(13) can be expressed in a Taylor approximation of :

(15)

Fig. 4. � and � versus � of a resistively loaded CS-stage.

with the following Taylor coefficients:

(16)

To demonstrate the importance of the coefficients in (16),they have been derived from simulations. The circuit parame-ters of the simulated CS-stage are: m mand . MOS model 11 [19], known for its accuratelinearity modeling, is used for the transistor model. Fig. 4 showsthe drain-source current and the drain-source voltage

versus the gate-source bias voltage . In the insetof Fig. 5 the linear voltage gain of the CS-stage versus

is plotted. The second-order coefficient is proportionalto the derivative of , thus it equals 0 at the maximum gainpoint ( at ). The three contributions thatsum up to in (16) are also shown in Fig. 5. In the lower rangeof , where the transistor is in saturation, the second-orderdistortion due to the cross-term is in the same order (butwith opposite sign) as the second-order coefficient generatedby the transconductance nonlinearity . These two termscancel each other around the maximum in gain .The contribution due to the output conductance in this

range is small. As increases (and decreases)the transistor goes into linear operation, which results in lowertransconductance nonlinearity . However, the outputconductance nonlinearity increases significantly above

due to the decreasing . The contribution dueto the cross-term remains relatively constant over a broad rangeof values.

Fig. 6 shows the IIP2 and IIP3 versus of the resistivelyloaded CS-stage. These graphs were derived from the Taylorcoefficients , and using

IIP2 dB

IIP3 dB (17)


Fig. 5. Simulated second-order nonlinearity coefficient �� and individualcontributions due to the transistor coefficients (� , � and � ). Inset: lineargain coefficient �� of the CS-stage.

Fig. 6. Simulated IIP2 and IIP3 of a resistively loaded CS-stage.

where the factor 10 dB accounts for the conversion from peak-voltage to power in dBm in 50 . This shows that the resis-tively loaded CS-stage is capable of achieving an IIP2 higherthan 20 dBm with an IIP3 higher than 2 dBm when it is bi-ased close to the point where it reaches a maximum in gain.

V. CIRCUIT DESIGN

Fig. 7 shows the balun-LNA circuit, the circuit inside thedashed box is implemented on silicon. The voltage gains of theCG- and CS-paths are designed to be equal, giving the balunfunction. However, the CS-stage is scaled up n times by admit-tance scaling to achieve lower noise (see Section III). As a resultthe output impedance of the CG and CS-stage are not equal. Tosolve this, the outputs of both amplifier paths are buffered byidentical source-followers, both having 50 output impedance.These source-followers are currently also used as measurementbuffers; in a complete receiver design they can drive a mixer,usually at a higher impedance level and reduced current. Tomaximize balanced operation, the DC-levels at the gates of thesource followers are chosen equal. This is achieved by AC-cou-pling the output of the CS-stage to its source-follower and gen-

Fig. 7. Schematic of the wideband balun-LNA; the circuit within the dashedbox is integrated on chip.

Fig. 8. Die photo of the bonded wideband balun-LNA.

erating the DC-level by a scaled replica of the CG-stage(see Fig. 7). The cut-off frequency of the AC-coupling is de-signed to be at 10 MHz. This is more than a decade below the in-tended minimum operation frequency, which keeps the error inphase difference of the two paths within a few degrees of 180 .The transconductance of is chosen 5 times higherthan to limit its noise contribution (see Section III). Theresistor acts as a current source and is chosen 7 times higherthan , thereby limiting its noise contribution to about 0.3 dB.

VI. MEASUREMENTS

The LNA, which has an active area of only 110 m 80 m,has been fabricated in a baseline 65 nm CMOS process and ismounted on a PCB, see Fig. 8. For quick prototyping only themost critical connections for the RF performance, the inputs andoutputs, are bonded. The supply and bias are applied using aprobe. By using adequate on-chip decoupling, the effects due toinductance in the supply lines are suppressed.

A. Gain, Input-Match and Isolation

Fig. 9 shows the measured single-ended input to differentialoutput S-parameter gain, . This parameter characterizes


Fig. 9. Simulated and measured S-parameters, � (Gain: single-ended in,differential out) and � .

Fig. 10. Measured noise figure, simulated NF and NF of the complete LNA.

the gain of the LNA using a 50 single-ended input port anda 100 differential output port. In practical use, the LNA willusually be followed by an on-chip mixer with a voltage-typeinput, and matching to 50 at the outputs is not needed. Themost meaningful gain parameter is then the (unloaded) voltagegain. To convert into voltage gain, 6 dB needs to be addedto account for the voltage-halving at the matched output, and anadditional 3 dB to take the conversion from 50 input to 100output into account. Thus, the voltage gain is within 15.1 dB0.5 dB from 100 MHz up to 2.5 GHz. The 3 dB bandwidth is5.2 GHz.

The -network formed by an external capacitor (600 fF), theinput bondwire inductance ( 1 nH) and the input capacitanceof the circuit gives a broad input match. Fig. 9 shows thatis below 10 dB up to 6.2 GHz. The influence of the groundinductance is included in this measurement, as a Ground-Signal-Ground configuration has been used to bond the input.

The common and differential output to single-ended inputisolations ( and , not shown) are better than 30 dBup to 10 GHz.

Fig. 11. Gain imbalance, simulated and measured (20 samples).

Fig. 12. Phase imbalance, simulated and measured (20 samples).

B. Noise Figure

Fig. 10 shows that the measured noise figure (NF) is below3.5 dB from 0.2 to 5.2 GHz and below 4 dB from 0.1 to 6 GHz.Another advantageous property of the noise canceling techniqueis that the power and noise matching can be obtained simultane-ously [4]. Indeed, the simulated NF equals the simulated NFof the complete LNA over a large bandwidth and only starts todeviate at higher frequencies due to the increasing impedancemismatch at the input. The increase of NF at low frequen-cies is due to noise, and the increase at high frequencies isdue to the drop in gain.

C. Gain and Phase Imbalance

The balun performance was characterized on 20 samples atnominal bias conditions, equal to the simulation conditions.These measurements were performed using wafer-probing. Thegain and phase imbalance measurements are shown in Fig. 11and Fig. 12. The gain imbalance is within 0.7 to 0.3 dBfrom 100 MHz to 5.2 GHz and even within 0.3 dB in theband 180 MHz–3.5 GHz. The phase imbalance remains within

2 degrees from 250 MHz to 6 GHz. The somewhat largerspread in phase difference in the 300–800 MHz range is causedby a resonance-effect in the output cables and non-optimal


TABLE ICOMPARISON OF BALUN-LNAS, PASSIVE BALUNS AND INDUCTORLESS SINGLE-ENDED LNAS

Fig. 13. IIP2 and IIP3 versus intermodulation frequency �� .

probe contacting. If desired, fine tuning of the balun function-ality is possible, e.g., via the bias of the CS or GS stage or viathe bulk of the CG transistor.

D. Linearity

Fig. 13 shows the second-order and third-order interceptpoints versus the frequency of one of the intermodulation tones.To determine the IIP2, one fixed 900 MHz tone (e.g., GSM) isused, whereas another input tone is swept in frequency from100 MHz to 9.1 GHz. For intermodulation frequencies below900 MHz the difference frequency is taken, for frequenciesabove 900 MHz the sum frequency is taken as the intermodu-lation frequency. An IIP2 of more than 20 dBm over the full100 MHz–10 GHz range is achieved. This shows that using thecombination of distortion canceling of the CG and the optimum

bias for the CS around the gain maximum (see Section IV-B),gives low overall second-order distortion.

The spread of IIP2 was measured on 20 samples, whilekeeping the biasing fixed. The worst case was found to be

18 dBm while other samples showed an IIP2 as high as34 dBm. To improve this IIP2 value further, and guarantee it

over temperature and process spread, it is beneficial to applycalibration techniques, as is more and more done in mixers[20], [21]. An effective approach is for instance to useto tune the gain of the CS-stage, while using the bulk of theCG-stage to equalize the gain of the CG- and CS-stage. Simu-lations show a gain error 0.1 dB for all process-corners anda temperature range of 40 to 100 C, with a worst caseIIP2 23 dBm for fast N, fast P at 40 C and a best caseIIP2 33 dBm for nominal process at 40 C (nominal caseIIP2 27 dBm at 27 C).

The IIP3 is determined using two closely spaced tones andis around 0 dBm. The increase in IIP3 with frequency can beexplained by the increasing impedance mismatch at the input.The capacitance at the input of the chip input shunts the signalto ground at higher frequencies. Consequently, for the sameinput power there is less voltage swing on the input-transistorsat higher frequencies than in the lower frequency range. Thisresults in less distortion and an increased IIP3.

Overall, the results show that capacitive effects in thebalun-LNA play only a minor role over most of the bandwidth.

E. Benchmarking to Other Designs

Table I shows a comparison of the balun-LNA to three otherwideband CMOS active baluns [1]–[3], two passive balunsimplemented in CMOS [22] and GaAs [23] and two wideband


inductorless single-ended LNAs [4] and [24]. The proposedbalun-LNA is more wideband than the passive integrated baluns[22], [23] while showing smaller gain and phase imbalances.The LNA performance of the implemented circuit is competi-tive to non-balun LNAs [4] and [24]. The circuit is integratedin a digital baseline 65 nm process using baseline transistorsand a 1.2 V supply voltage. Still, at this low supply voltage, itachieves high linearity and the active area is small, as no inte-grated inductors are required. In contrast to [1] the balun-LNApresented in this work simultaneously achieves impedancematching, noise canceling and a well-balanced output.

VII. CONCLUSION

In this paper we analyzed the performance of a parallelcommon-gate (CG) and common-source (CS) stage for opera-tion as a wideband balun-LNA. We showed that it is possibleto achieve simultaneous output balancing, noise cancelingand distortion canceling. This requires admittance scaling ofthe CS-stage with respect to the CG-stage. Compared to atraditional balun design with equally sized CG and CS de-vices this circuit achieves better noise. Compared to equalload impedance designs, output balancing is achieved and alower noise figure can be achieved. Moreover, we show thatvery good linearity can be achieved if the CS-stage has goodlinearity. In particular, it is shown that an interesting optimumIIP2 point exists in which the cross-term cancels thetraditionally dominant square-law term. Table I shows thatthis leads to a balun-LNA with very competitive performancein terms of output balancing, noise figure and linearity, whileusing standard 65 nm transistors at the standard 1.2 V supplyvoltage.

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Stephan C. Blaakmeer (S’00–M’08) was born inStiens, The Netherlands, in 1976. He received theM.Sc. degree in electrical engineering from theUniversity of Twente, Enschede, The Netherlands,on the subject of RF-CMOS ring oscillators, in2001. He joined Ericsson Eurolab, Emmen, TheNetherlands, in 2001, where he worked on CMOSradios for Bluetooth. In 2003, he returned to the ICDesign group of the University of Twente to worktoward the Ph.D. on the subject of wideband receivertechniques in CMOS.

He recently joined Axiom IC, Enschede, The Netherlands, where he isworking on RF transceivers. His interests are RF and analog circuits in generaland more specifically in circuits for wireless transceivers.


Eric A. M. Klumperink (M’98–SM’06) was bornon April 4, 1960, in Lichtenvoorde, The Netherlands.He received the B.Sc. degree from HTS, Enschede,The Netherlands, in 1982. After a short period inindustry, he joined the Faculty of Electrical Engi-neering of the University of Twente (UT), Enschede,in 1984, participating in analog CMOS circuit designand research. This resulted in several publicationsand a Ph.D. thesis, in 1997 (“Transconductancebased CMOS circuits”).

After his Ph.D., he started working on RF CMOScircuits, and he is currently an Associate Professor at the IC-Design Laboratorywhich participates in the CTIT Research Institute (UT). He holds several patentsand has authored or co-authored more than 80 journal and conference papers.

In 2006 and 2007, Prof. Klumperink served as Associate Editor for IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS, PART II, and since 2008 for IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS, PART I. He was a co-recipient ofthe ISSCC 2002 Van Vessem Outstanding Paper Award.

Domine M. W. Leenaerts (M’94–SM’96–F’05)received the Ph.D. degree in electrical engineeringfrom Eindhoven University of Technology, Eind-hoven, The Netherlands, in 1992.

From 1992 to 1999, he was with EindhovenUniversity of Technology as an Associate Professorwith the Micro-electronic Circuit Design group. In1995, he was a Visiting Scholar with the Departmentof Electrical Engineering and Computer Science,University of California, Berkeley. In 1997, he wasan Invited Professor with the Technical University

of Lausanne (EPFL), Lausanne, Switzerland. From 1999 until 2006, he waswith Philips Research Laboratories. Since 2007, he has been with NXPSemiconductors, Research, as Senior Principal Scientist, involved in (CMOS)RF integrated transceiver design. He has published over 150 papers in scientificand technical journals and conference proceedings and holds more than 20 USpatents. He has co-authored several books, including Circuit Design for RFTransceivers (Kluwer, 2001).

Dr. Leenaerts served as IEEE Distinguished Lecturer in 2001–2003 andserved as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS ANDSYSTEMS, PART I during 2002–2004. Since 2005 he is the IEEE Circuitsand Systems Society Member representative in the IEEE Solid-State CircuitsSociety Administrative Committee. Since 2007, he has served as an AssociateEditor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He is a member of thetechnical program committees of ISSCC, ESSCIRC, and RFIC.

Bram Nauta (M’91–SM’03–F’08) was born inHengelo, The Netherlands, in 1964. In 1987, hereceived the M.Sc. degree (cum laude) in electricalengineering from the University of Twente, En-schede, The Netherlands. In 1991, he received thePh.D. degree from the same university on the subjectof analog CMOS filters for very high frequencies.

In 1991, he joined the Mixed-Signal Circuitsand Systems Department of Philips Research,Eindhoven, The Netherlands, where he worked onhigh-speed AD converters and analog key modules.

In 1998 he returned to the University of Twente, as a Full Professor headingthe IC Design group, which is part of the CTIT Research Institute. His currentresearch interest is high-speed analog CMOS circuits. He is also part-timeconsultant in industry, and in 2001 he co-founded Chip Design Works. HisPh.D. thesis was published as the book Analog CMOS Filters for Very HighFrequencies (Springer, 1993).

Dr. Nauta received the Shell Study Tour Award for his Ph.D. work. From1997 to 1999, he served as an Associate Editor of IEEE TRANSACTIONS ONCIRCUITS AND SYSTEMS, PART II: ANALOG AND DIGITAL SIGNAL PROCESSING.After this, he served as Guest Editor, Associate Editor (2001–2006), and from2007 as Editor-in-Chief for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. Heis also member of the technical program committees of the International SolidState Circuits Conference (ISSCC), the European Solid State Circuit Confer-ence (ESSCIRC), and the Symposium on VLSI circuits. He is a co-recipient ofthe ISSCC 2002 Van Vessem Outstanding Paper Award, and is a distinguishedlecturer of the IEEE and elected member of IEEE-SSCS AdCom.

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