ieee paper on power optimization of bist circuit using low power lfsr

International Journal of Computer Trends and Technology- volume2Issue2- 2011

ISSN: 2231-2803 http://www.internationaljournalssrg.org Page 5

Power optimization of BIST circuit using low power LFSR

PRATHYUSHA NAYINENI S.K. MASTHAN M.Tech,

M.TECH(VLSI), ASSOCIATE PROFESSOR,

Jayamukhi institute of technological sciences, Jayamukhi institute of technological sciences,

Warangal, Andhra Pradesh. Warangal, Andhra Pradesh.

Abstract: In most number of electronic systems that are used in safety critical applications circuit testing has to be performed periodically. For these systems power dissipation due to BIST [built in self test] represents a significant percentage of overall power dissipation. The power dissipation during the test mode is 200% more than in normal mode. So, to reduce the power dissipation during the test mode for BIST circuit, we are using a low power LFSR. The correlation between consecutive patterns are higher in normal mode than during testing so, by using LPLFSR we are reducing the transitions between consecutive patterns generated by the conventional LFSR.

1.INTRODUTION

Now a days many circuits include on chip structures that enable self testing known BIST. The power dissipation during the test mode 200% more than in normal mode. hence it is an important aspect to optimize the power during testing.

The main sources of power dissipation in CMOS devices are summarized by the following expression

P = 0.5.C.VDD2.f.N+QSC.VDD.f.N+Ileak.VDD…eqn(1)

Where, p denotes the total power, vdd is the supply voltage and f is the frequency of operation.

The first term in equation(1) corresponds to the power involved in charging and discharging circuit nodes. C represents the node capacitance and N is the swiching activity i.e., the number of gate output transitions per clock cycle(also known as transition density)is the energy involved in charging or discharging a circuit with node capacitance C and is the average number of times per second that the node switches.

The second term in (1) represents the power dissipation due to current flowing directly from the supply to ground. During this period that the pull-up

and pull-down networks of the CMOS gate are both conducting when the output switches. This current is often called short circuit current. The factor represents the quantity of charge carried by the short circuit current per transition.

The third term in (1) is related to the static power dissipation due to leakage current. The transistor source and drain diffusions in a MOS device from parasitic diodes with bulk regions. Reverse bias current in these diodes dissipate power.

These 3 factors for power dissipation are often referred to as dynamic power, short-circuit power and leakage current power respectively. It has been shown[2] that during normal operation of well designed CMOS circuits the switching activity power accounts for over 90% of total power dissipation. Thus power optimization techniques at different levels of abstraction targets minimal switching activity power.

In equation(1), the power dissipation can be reduced if we reduce the supply voltage or clock frequency. But this will degrade the performance of the system. C is the function of process technology and therefore not under the control of designer. So the power dissipation is directly proportional to the switching activity.

The reasons for increased power in test mode are:

1) To test the large circuit, the circuits are partitioned to save the test time, but the parallel testing results in excessive energy and power dissipation.

2) Due to lack of at speed equipment availability, the delay is introduced in the circuit during testing. This will cause the power dissipation.

3) Due to lack of correlation between the successive patterns, there exist a large



switching activity in test mode. Since the power dissipation in CMOS circuits is directly proportional to the switching activity, so, the excessive switching activity may be responsible for cost, reliability, performance verification and technology related problems.

For testing complex circuits, hierarchical approach is used. The advantage of hierarchial approach is that, every block is tested separately. That is test input is given to each block and output of each block is observed and verified. DFT(design for testability) is a technique used in chip design process to enhance the ability to generate the test vectors, to achieve measured quality level and to reduce the cost of testing. Generally, we use the conventional DFT approaches such as scan and BIST.

In this paper, a modified LFSR is proposed which reduces the number of transitions in the test patterns. The remaining paper is organized into 5 sections. Section2 describes the previous work, section3 describes proposed work, section4 describes the simulation results section5 describes conclusions and future work.

2. PRIOR WORK

Linear Feedback Shift Register is a circuit consisting of flip-flops connected in series with each other. The output of one flip-flop is connected to the input of the next flip flop and so on. The feedback polynomial which is also known as the characteristic polynomial is used to determine the feedback taps which in turn determines the length of the random pattern generation.

An example below in Figure 2.1 is used to illustrate a correlation between the LFSR, its characteristic polynomial and matrix theory. In the circuit the feedback taps are shown to be from the output of the 4th and 1st register.

tap1 tap4

o/p LSBIT CLOCK Figure 2.1 Conventional LFSR or XOR LFSR These taps are indicative of the generator polynomial. Using the matrix theory the companion matrix required for relating the present to the next state is depicted. The actual sequence of the LFSR is

represented as BT, BT2, BT3, ….where B is the seed vector. The determinant of the T matrix is called the characteristic polynomial and the generator polynomial is the inverse of the characteristic polynomial. The increased power consumption by the device in the manufacturing test environment therefore can in most cases exceed the maximum power consumption specification of the IC resulting in un-repairable device failures begins with a pattern generated using a conventional LFSR causing significant loss of yield. Earlier Techniques for reducing the power dissipation during testing are

RSIC (random single input change) test generation, which is used to generate low power test pattern. In this method power consumption is reduced but at the additional cost is between 19% and 13%.

Another technique was proposed in [3] that is Low transition LFSR for BIST applications. This reduces the average and peak power of circuit during testing.

In [4], a Fault model& ATPG algorithm is chosen first, and then test patterns are generated to achieve the desired fault coverage.

F.corno et al proposed a Low power test pattern generation for sequential circuit in [5]. In this paper redundancy is introduced during testing. This will reduces the power consumption without affecting the fault coverage.

3. PRESENT WORK

The components of BIST architecture is given below.

1. Test pattern generator(TPG): it generates test patterns for CUT. It is generally a LFSR or ATPG.

2. Circuit under test(CUT): it is the circuit to be tested. It can be either combinational, sequential or memory.

3. Multiple input signature register(MISR): it is designed for signature analysis, which is a technique for data compression.

4. Test response analysis(TRA): it compares the value of primary output with the expected output.

D Q

D Q

D Q

D Q



5. BIST control unit(BCU): it controls the test execution and manages all the components of a BIST circuit. And it is activated by a go/no go signal.

In this paper a low power LFSR is proposed for BIST applications.

Figure3.1 BIST architecture

3.1. ALGORITHM FOR LOW POWER LFSR

LFSR is a shift register which consists of series of flip flops and is used to generate test patterns for BIST externally. The initial value of LFSR is called seed value. It poses a significant effect on energy consumption [6]. The output that influences the input is called tap. LFSR is represented by a polynomial known as characteristic polynomial, which is used to determine appropriate feedback taps.

Figure 3.2 proposed algorithm for low power LFSR

A common clock signal is applied to the flip flops which enable the propagation of bits from input to output of flip flops. The correlation between the bits

can be achieved by adding more number of test vectors which reduces the switching activity so that the power consumption is reduced.

In the proposed approach, 3 intermediate vectors are generated between every 2 successive vectors say T1, T2. The total number of signal transitions occurs between these 5 vectors are equal to the number of signal transitions between T1 and T2. Hence the power consumption is reduced. Additional circuitry is required is required to generate 3 intermediate vectors

The EDA tool is used in which conventional and low power LFSR is coded in verilog hardware description language Xilinx 10.1. The outputs of 36-bit LFSR is used as inputs to C432 ICSAS-85, a benchmark interrupt controller. In this c432 is used as CUT. The RTL view of LP LFSR with c432 circuit is shown in figure3.

4. SIMULATION RESULTS

The results obtained from Xilinx 10.1 will be implemented on xc3s200-4pq208.

VCD file is generated after post simulation. X power is used to calculate the power consumption. Assume the seed value to the 36-bit LFSR is (01001010010110101101001O100101101011).

Figure4. 1 simulation results

LFSR- TPA

MISR

TRA

CUT

CONTROL UNIT



Figure4.2 RTL view of LP LFSR with c432 bench mark circuit

Comparison of Results of results of conventional and low power LFSR is shown in table4.1

Power/parameters LP-LFSR(mW)

Xor-LFSR(mW)

Vccint 1.20v 19 75

Vcc Max 2.50v 38 38

Vcc 025 2.50v 0 0

inputs 1 15

Clocks, signals 0 42

Quiescent 1.20 18 18

Total 57 112

Table4.1. comparison of conventional and LP LFSR

5. CONCLUSION AND FUTURE WORK

It is observed that total power consumed in modified LFSR is 46% less than the normal LFSR. And dynamic power is decreased by 44.6%[7]. It is concluded that low power LFSR is very much useful for power optimization of BIST.

5.1 FUTURE WORK

Power dissipation in BIST can also be test pattern reordering with the purpose of reducing the amount of power dissipated during circuit testing. By

reordering test patterns one is able to find test sequences for which power dissipation is minimized.

REFERENCES

[1] F. Najm, “Transition Density, A New Measure of Activity in Digital Circuits”, in IEEE Transaction on computer Aided Design no.2, vol.12, pp.310-323, February 1993.

[2] A. Chandrakaran, T. Sheng and R.Brodersen, “Low Power CMOS Digital Design”, in IEEE Jounal of Solid State Circuits,

[3]. Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed, “Low Transition LFSR for BIST-Based Applications

[4]. Fulvio Corno, Paolo Prinettom, Matteo Sonzar Forda “testability Analysis and ATPG on Behavioral RT- Level VHDL”,

[5]. F.Corno, M.Rebaudengo, M.Sonza Reorda, “A Test Pattern Generation Methodology for Low Power Consumption”, pp.1-5, 2008.

[6]. Dr. K. Gunavathi, Mr. K. Paramasiva, Ms.P. Subashini Lavanya, M.Umamageswaram, “A Novel BIST TPG for Testing of VLSI Circuits”,

[7]. Balwinder Singh, Arun Khosla, Sukhleen Bindra, “ power optimization of LFSR for Low Power BIST”, IEEE International conference 2009, pp. 311-314.

ieee paper on power optimization of bist circuit using low power lfsr

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