ieee transactions on power electronics, vol. 23, no. 4, july 2008 1649 open-loop ... loop co… ·...

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008 1649

Open-Loop Control Methods for InterleavedDCM/CCM Boundary Boost PFC Converters

Laszlo Huber, Member, IEEE, Brian T. Irving, and Milan M. Jovanovic, Fellow, IEEE

Abstract—Open-loop interleaving methods for PFC boost con-verters operating at the boundary of discontinuous-conductionmode and continuous-conduction mode with a master-slave re-lationship are analyzed. It is shown that the only method thatresults in stable operation is the synchronization of the slaveconverter to the turn-on instant of the master converter, whereeach converter operates with current-mode control. Effects ofmismatched inductances, phase-shift error, switching-frequencylimit, and valley switching on the quality of the input current arediscussed in detail.

Index Terms—Interleaved boost, open-loop control, powerfactor correction (PFC), variable frequency, zero-voltage switching(ZVS).

I. INTRODUCTION

I N off-line power supplies that require active power factorcorrection (PFC), a boost converter operating at the

boundary of discontinuous conduction mode (DCM) andcontinuous conduction mode (CCM) is a widely employedtopology at low-power levels (up to 200–300 W) because itis more efficient and more cost effective than the CCM boostPFC converter [1]–[4]. These benefits are brought about bythe elimination of the reverse-recovery losses of the boostdiode and by turning on the boost switch with zero-voltageswitching (ZVS) or near ZVS (also called valley switching).Neither the CCM nor the DCM boost PFC converter, whichoperate with a constant switching frequency, can achieve ZVSwithout an additional active snubber circuit. Other benefits ofthe DCM/CCM boundary boost PFC converter compared tothe constant-switching-frequency DCM boost PFC converterare a lower total-harmonic distortion (THD) of the line current,and a smaller peak inductor current resulting in lower turn-offswitching losses and lower conduction losses [5]. Although theDCM/CCM boundary boost PFC converter exhibits a smallerpeak inductor current than the DCM boost PFC converter, itspeak inductor current is still twice its average current, whichoften necessitates a large differential mode (DM) electromag-netic interference (EMI) filter [11]. Another drawback is thatits switching frequency, which changes with the instantaneousline voltage and the output power, varies over a wide range.In order to prevent excessive switching losses, a maximumswitching-frequency limit is often implemented.

Manuscript received March 14, 2007; revised July 26, 2007. Published June20, 2008. Recommended for publication by Associate Editor B. Fahimi.

The authors are with Delta Products Corporation, Power Electronics Labora-tory, Research Triangle Park, NC 27709 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2008.924611

Fig. 1. Basic topology of two interleaved PFC boost converters.

Generally, the input current ripple and, consequently, theinput DM-EMI filter can be significantly reduced by inter-leaving two or more boost PFC converters as shown in Fig. 1[6]–[19]. In addition, the output current ripple can be alsosignificantly reduced, resulting in a reduced equivalent-se-ries-resistance (esr) loss of the output capacitor, and possibly areduction in capacitor volume. Another benefit of interleavingis that the efficiency at lighter loads can be increased byemploying phase shedding, i.e., by progressively turning offconverters as the load is decreased.

By interleaving two or more DCM/CCM boundary boost con-verters, the benefits of DCM/CCM boundary boost PFC con-verters mentioned above can be extended to higher power levels.However, since the switching frequency is variable, the synchro-nization of interleaved DCM/CCM boundary boost PFC con-verters presents a challenging task.

Very few implementations of the interleaved DCM/CCMboundary boost PFC converters have been published in theliterature [11]–[19]. All previously published implementationsare based on a master-slave relationship, where the masterconverter operates as a stand-alone converter, whereas, theslave converter(s) is partially controlled by the master in orderto achieve proper interleaving, i.e., a proper phase shift withrespect to the master. It has been shown that the slave convertercan be synchronized to the master converter with an open-loopmethod [11]–[16], i.e., by generating a time delay equal to halfthe switching period of the master determined from its previousswitching cycle, or with a closed-loop method [17]–[19], i.e.,by measuring the phase difference between the convertersand adjusting the phase of the slave based on the phase error.The slave converter with open-loop synchronization can besynchronized to the turn-on instant of the master converter[12]–[15] or to the turn-off instant of the master converter [11],[16]. The slave converter with closed-loop synchronizationhas been synchronized to the master converter by using aphase-locked-loop (PLL) approach and adjusting the turn-offinstant of the slave converter [17]–[19].

0885-8993/$25.00 © 2008 IEEE

1650 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 4, JULY 2008

Fig. 2. (a) Basic control circuit and (b) key waveforms of two interleavedDCM/CCM boundary boost PFC converters with current-mode control, withmatched inductances, when the slave is synchronized to the turn-on instant ofthe master.

However, none of these papers [11]–[19] offers a completeanalysis of the behavior of the interleaved converters. Specifi-cally, no analysis of the effect of components mismatching onsteady-state and transient performance is given. In addition, forthe open-loop synchronization methods, the response of the in-terleaved converters to phase-shift disturbances has not been ad-dressed at all. As a result, practical limitations of some of theproposed implementations have not been properly recognized.

This paper is focused on the analysis of the open-loop syn-chronization methods of the slave converter to the master con-verter. In Section II, synchronization of the slave converter tothe turn-on instant and to the turn-off instant of the master con-verter for both current-mode and voltage-mode control is ana-lyzed with respect to inductor tolerances and interleaving sta-bility. It is shown that among the open-loop synchronizationmethods, the only method that results in stable operation is thesynchronization of the slave converter to the turn-on instant ofthe master converter, where each converter operates with cur-rent-mode control. In Section III, the open-loop method wherethe slave is synchronized to the turn-on instant of the master isfurther analyzed with respect to the input current ripple. The ef-fects of limiting the switching frequency and maintaining valleyswitching on both the input-current ripple and input-current dis-tortion are also discussed.

II. ANALYSIS OF OPERATION WITH OPEN-LOOP

SYNCHRONIZATION METHODS

As mentioned in Section I, with open-loop synchronization,the slave converter can be synchronized to the turn-on instant orto the turn-off instant of the master converter. In both cases, theconverters can operate either with current-mode control or withvoltage-mode control.

A. Synchronization of Slave to Turn-On Instant of Master

The basic control circuit and key waveforms when the slaveconverter is synchronized to the turn-on instant of the masterconverter are shown in Figs. 2 and 3 for current-mode andvoltage-mode control, respectively. It is assumed in Figs. 2 and3 that the inductances of the master and slave converters arematched, i.e., . It is also assumed that the resonant

Fig. 3. (a) Basic control circuit and (b) key waveforms of two interleavedDCM/CCM boundary boost PFC converters with voltage-mode control, withmatched inductances, when the slave is synchronized to the turn-on instant ofthe master.

interval, during which the voltage of a boost switch resonatesdown to its valley is negligible compared to the switchingperiod.

In both Figs. 2 and 3, the master is turned on by zero-cur-rent-detection pulse ZCD-M, and the slave is turned on afterdelay with respect to the turn-on instant of the master. Delay

is equal to half the switching period of the master determinedfrom the master’s previous switching cycle. ZCD-M signal goeshigh once master inductor current decreases to zero. Boththe master and slave are turned off by their own PWM, whichcompares a ramp signal to a feedback signal. In the case ofcurrent-mode control, shown in Fig. 2, the ramp signal is in-ductor current and the feedback signal is the sinusoidal refer-ence current , which is proportional to the output of thevoltage-loop error amplifier. In the case of voltage-mode con-trol, shown in Fig. 3, the ramp signal is ramp voltage ,which has a constant slope and which is synchronized to the in-dividual boost turn-on instant. The feedback signal is the outputvoltage of the voltage-loop error amplifier, .

The key difference between current-mode and voltage-modecontrol circuits shown in Figs. 2 and 3 is that the slope of theramp in current-mode control, i.e., , changes proportionallywith the voltage across inductor , and inversely with the induc-tance of inductor , whereas, the slope of the ramp in voltage-mode control is always constant. This difference results in verydifferent operation when the inductances are mismatched, orwhen delay time is perturbed.

If the inductances of the master and slave with current-modecontrol are mismatched, the boost switch of the slave will loseZVS turn-on. In fact, if , the slave will operate inDCM, as shown in Fig. 4(a) and, if , the boost switchof the slave will alternately turn on with hard switching and inDCM, i.e., the slave will operate with a subharmonic oscillation,as shown in Fig. 4(b). With voltage-mode control, if the induc-tances of the master and slave are mismatched, the ZVS turn-onof the slave switch will not be disturbed, as shown in Fig. 5. Itcan be seen in Fig. 5 that although the slope of the slave’s in-ductor current changes, the on-time of the slave does not changebecause it is determined by the slave’s voltage ramp which has

HUBER et al.: OPEN-LOOP CONTROL METHODS FOR INTERLEAVED DCM/CCM BOUNDARY BOOST PFC CONVERTERS 1651

Fig. 4. Inductor current waveforms of the master and slave operating with cur-rent-mode control, with mismatched inductances, when the slave is synchro-nized to the turn-on instant of the master: (a) L < L and (b) L > L .

Fig. 5. Inductor current waveforms of the master and slave operating withvoltage-mode control, with mismatched inductances, when the slave is synchro-nized to the turn-on instant of the master.

a constant slope. The current sharing error in Fig. 5 can be de-termined as

(1)where is the ratio of the boost inductances; whereas,and are respectively the master and slave inductor cur-rents averaged over a switching cycle . Typically, the toler-ance of the boost inductances is 5%, which results in a currentsharing error of 10%. However, if the mismatch of the boost in-ductances is 10%, the current sharing error is 20%.

To prevent the turn-on of the boost switch of the slave withhard switching in current-mode control and, consequently, anincreased switching loss, the slave’s reference current can be re-duced with respect to the master’s reference current, as shownin Fig. 6(a) [14]. Unfortunately, by reducing the slave’s refer-ence current, the current sharing between the master and slavebecomes significantly worse. As shown in Fig. 6, the current-sharing error is the worst when the slave current reference isoptimally lowered to ensure that the slave’s boost switch neverturns on with hard switching. The worst-case current sharingerror is determined as

(2)

Fig. 6. Inductor current waveforms of the master and slave operating with cur-rent-mode control and with the slave synchronized to the turn-on instant of themaster, when the slave’s reference current is reduced with respect to the master’sreference current.

For 5% and 10% mismatch of the boost inductances, thecurrent sharing error is 29.8% and 58.5%, respectively.

A better approach to prevent the turn-on of the boost switch ofthe slave with hard switching in current-mode control is to iden-tify the master and the slave during the initialization phase, i.e.,to ensure that the inductance of the slave is always smaller thanthe inductance of the master. In that case, the inductor currentsof the master and slave with mismatched inductances follow thewaveforms shown in Fig. 4(a) and the current sharing error is de-termined with the same expression as (1). For 5% and 10%mismatch of the boost inductances, the current sharing error is10% and 20%, respectively.

Effects of the delay-time perturbation on the operation ofthe slave with current-mode control and with voltage-modecontrol are shown in Figs. 7 and 8, respectively. As shown inFig. 7, the slave with current-mode control always returns tonormal operation after one or two switching cycles. In fact, theslave with current-mode control returns to normal operationafter one switching cycle when the perturbed delay time issmaller than , as shown in Fig. 7(a) and 7(c), and aftertwo switching cycles when the perturbed delay time is greaterthan , as shown in Fig. 7(b) and 7(d). However, the slavewith voltage-mode control cannot always returns to normaloperation, as shown in Fig. 8. When the perturbed delay timeis smaller than , the slave with voltage-mode controlreturns to normal operation by the next switching cycle, asshown in Fig. 8(a) and 8(c). When the perturbed delay time isgreater than , the slave with voltage-mode control cannotreturn to normal operation, as shown in Fig. 8(b) and 8(d).

B. Synchronization of Slave to Turn-Off Instant of Master

The basic control circuit and key waveforms when the slaveis synchronized to the turn-off instant of the master are shown inFigs. 9 and 10, respectively, for current-mode and voltage-modecontrol. It is assumed in Figs. 9 and 10 that the inductances ofthe master and slave are matched, i.e., . It followsfrom Figs. 9(a) and 10(a) that the current-mode or voltage-modecontrol is only relevant for the operation of the master, whereas,the operation of the slave is identical in both control modes.Unlike in Figs. 2 and 3, the slave is turned on by zero-current-detection pulse ZCD-S, which goes high once slave inductorcurrent decreases to zero. The slave is turned off with a


Fig. 7. Effect of delay-time perturbation on the operation of the slave with cur-rent-mode control, when the slave is synchronized to the turn-on instant of themaster: (a) D > 0:5, T < T =2, (b) D > 0:5, T > T =2, (c) D < 0:5,T < T =2, and (d) D < 0:5, T > T =2.

delay with respect to the turn-off instant of the master. Delayis equal to half the switching period of the master determined

from the master’s previous switching cycle. The operation ofthe master is identical to that when the slave is synchronizedto the turn-on instant of the master described in the previoussubsection. Both the master and slave turn on with ZVS.

If the inductances of the master and slave with either cur-rent-mode or voltage-mode control are mismatched, the ZVSturn-on of the slave switch will not be disturbed, as shown inFig. 11. The current sharing error, defined in (1), for 5% and

10% mismatch of the boost inductances is 10% and 20%, re-spectively.

Effects of the delay-time perturbation on the operation of theslave are shown in Fig. 12. Since the operation of the slave isidentical in both current-mode and voltage-mode control, theeffects of the delay time perturbation on the operation of theslave shown in Fig. 12 include both control modes. As shown inFig. 12(a) and (b), if the duty cycle is greater than 0.5, the slavereturns to normal operation after a few switching cycles. It canbe seen in Fig. 12(a) and (b) that the error between the disturbedand nondisturbed inductor currents of the slave continuouslydecreases with each switching cycle. However, if the duty cycleis smaller than 0.5, the slave cannot return to normal operationand, in fact, oscillates, as shown in Fig. 12(c) and (d). It can beseen in Fig. 12(c) and (d) that the error between the disturbedand nondisturbed inductor currents of the slave continuouslyincreases with each switching cycle.

A summary of open-loop synchronization methods is pre-sented in Table I. The only open-loop method that results instable operation at any duty cycle is the synchronization of the

Fig. 8. Effect of delay-time perturbation on the operation of the slave withvoltage-mode control, when the slave is synchronized to the turn-on instant ofthe master: (a) D > 0:5, T < T =2, (b) D > 0:5, T > T =2, (c)D < 0:5, T < T =2, and (d) D < 0:5, T > T =2.

Fig. 9. (a) Basic control circuit and (b) key waveforms of two interleavedDCM/CCM boundary boost PFC converters with current-mode control, withmatched inductances, when the slave is synchronized to the turn-off instant ofthe master.


Fig. 10. (a) Basic control circuit and (b) key waveforms of two interleavedDCM/CCM boundary boost PFC converters with voltage-mode control, withmatched inductances, when the slave is synchronized to the turn-off instant ofthe master.

Fig. 11. Inductor current waveforms of the master and slave operating witheither current-mode control or voltage-mode control, with mismatched induc-tances, when the slave is synchronized to the turn-off instant of the master.

Fig. 12. Effect of delay-time perturbation on the operation of the slave withcurrent-mode control or voltage-mode control, when the slave is synchronizedto the turn-off instant of the master: (a) D > 0:5, T < T =2, (b) D > 0:5,T > T =2, (c) D < 0:5, T < T =2, and (d) D < 0:5, T > T =2.

slave converter to the turn-on instant of the master converter,where each converter operates with current-mode control.

III. ANALYSIS OF INPUT CURRENT WAVEFORM

In this section, the open-loop method where the slave is syn-chronized to the turn-on instant of the master and where eachoperates with current-mode control, is further analyzed with re-spect to the input-current ripple and the input-current distortion.To limit the current sharing error below a reasonable 20%, it isassumed that the master and the slave are identified during theinitialization phase. As a result, the reference current of the slaveis identical to the reference current of the master. For an addi-tional safety margin, the reference current of the slave can beslightly reduced (0.5%–1%) compared to the reference currentof the master.

A. Input-Current Ripple

The inductor currents of the master and slave for the idealcase when the inductances of the master and slave are matchedand the slave is 180 phase shifted with respect to the masterare shown in Fig. 13. Fig. 13 also shows the sum of the in-ductor currents, , i.e., the unfiltered input current,which has a frequency equal to twice the switching frequencyand has a peak-to-peak current ripple significantly smallerthan the ripple of the individual inductor currents . Gen-erally, input-current ripple is minimal when the phase shift is180 and maximal (twice ) when the phase shift is 0 . Theinput-current ripple is dependent on the duty cycle, convertertolerances, e.g., tolerance of the boost inductances, as well asan improper phase shift between the converters. The input-cur-rent ripple normalized to the peak inductor current is de-termined as

for

for(3)

The normalized input current ripple as a function of duty cycleis shown in Fig. 14(a).The filtered input current, , is obtained by averaging the

unfiltered input current over a switching period , i.e.,. It can be easily shown that the filtered input

current is equal to the peak inductor current, i.e., .The filtered input current and the unfiltered input current over

a half line cycle for the ideal case of matched inductances and180 phase shift of the slave versus master are presented inFig. 14(b). The unfiltered input current is presented with itsupper and lower envelope. Both the filtered and unfiltered inputcurrent in Fig. 14(b) are normalized to the peak value of the fil-tered input current, . The input-current ripple in Fig. 14(b) isobtained from (3) by substituting the variation of the duty cycleduring a half line cycle, i.e., in(3). It follows from Fig. 14(b) that the input-current ripple ismaximal at , where .

Component tolerances, particularly the tolerance of boostinductance , lead to a mismatch between the boost stagesand, therefore, increase input-current ripple , as shown inFig. 15. The normalized input-current ripple as a function ofduty cycle for three different tolerances of the boost induc-tances is shown in Fig. 15(a). Unfortunately, the relationship

cannot be expressed in a closed form. Itshould be noted in Fig. 15(a) that the perfect ripple cancellationat is lost for any inductance mismatch. The unfiltered


TABLE ISUMMARY OF OPEN-LOOP SYNCHRONIZATION METHODS

Master and Slave are identified during the initialization phase (always L < L )

Master and Slave are NOT identified during the initialization phase (L � L or L � L )

Fig. 13. Boost inductor currents for matched inductances with 180 phase shiftand duty cycle greater than 0.5.

Fig. 14. Input-current ripple for the ideal case of matched boost inductanceswith 180 phase shift: (a) normalized input-current ripple as a function of dutycycle and (b) upper and lower input-current envelopes for V = 230V

and V = 385 V.

input current, corresponding to Fig. 15(a), is presented inFig. 15(b). For the worst case in Fig. 15, when ,the maximal input-current ripple is , which isa 29% increase compared to the ideal case.

Fig. 15. Input-current ripple of mismatched boost inductances: (a) normalizedinput-current ripple as a function of duty cycle and (b) upper and lower input-current envelopes for V = 230V , V = 385 V, P = 250 W, andL = 230 �H.

If the slave has a turn-on delay of , i.e., if the phase shiftis greater than 180 , the normalized input-current ripple can bederived in a closed form, i.e.,

for

for(4)

In (4), is the switching period determined as

(5)


Fig. 16. Input-current ripple of matched boost inductances with slave turn-ontime delay for V = 230V , V = 385 V, P = 250 W, and L =

230 �H: (a) normalized input-current ripple as a function of duty cycle and (b)upper and lower input-current envelopes.

where and represent the output power of a single boostconverter and the total output power of both boost converters, re-spectively, and is the boost inductance of a single converter.The normalized input-current ripple (4) versus duty cycle andthe corresponding filtered and unfiltered input currents over ahalf line cycle are presented in Fig. 16 for three different turn-ondelays at , , and .For the worst case in Fig. 16, when (i.e.,195 phase shift), the maximal input-current ripple is

, which is a 10% increase compared to the ideal case. Again,it should be noted in Fig. 16(a) that the perfect ripple cancella-tion at is lost for any turn-on delay of the slave.

B. Effect of Frequency Limit and Valley Switching onInput-Current Ripple

The switching frequency of the DCM/CCM boundary boostPFC converters, which is a function of both line voltage andload current, can vary over a very wide range. To prevent ex-cessive switching losses (e.g., gate-drive loss and turn-off lossof the main switch), it is beneficial to limit the switching fre-quency. The switching losses can be further minimized by en-suring valley switching, i.e., turning on the boost switch whenits voltage is minimum, under all conditions. The consequenceof the switching-frequency limit and the valley switching is thatthe turn-on moment of each boost switch is dependent on, first,reaching the minimum switching period and, then, if not coin-cidental with the valley, waiting an additional resonant periodbefore turning on the switch.

Fig. 17 shows key switching waveforms obtained throughSIMPLIS simulation for both the master and slave converters

Fig. 17. Key switching waveforms of both master and slave boost converteroperating with switching-frequency limit and valley switching.

operating with switching-frequency limit and valley switching.It should be noted that the boost converters are identical (i.e.,equal inductances, resistances, etc.), with the exception that theslave reference current level is set 0.5% lower than the masterreference current level. This gives an additional safety marginto ensure that the slave converter operates with a slightly higherswitching frequency when operating without synchronization.

Generally, the master switch is turned on with a preset delayto achieve valley switching once the master-valley-OK and min-imum-period-OK signals are both high. Once the master switchis turned on, the period ramp is reset and then linearly increasesuntil the master switch is turned on again at the start of thenext switching cycle. Since the slope of the period ramp is con-stant, the peak of the period ramp is proportional to the masterswitching period. The peak of the period ramp from the pre-vious switching cycle is sampled, divided by two, held for oneswitching cycle, and compared with the period ramp in the cur-rent switching cycle to determine the proper interleaving phaseshift of the slave converter.

As shown in Fig. 17, as the switching period of each con-verter approaches the minimum switching-period limit, valleyskipping begins to occur. Since the interleaving phase shift isdetermined by sampling the previous switching period of themaster, and since the master is jittering between its first andsecond valley, an improper phase shift and, therefore, an in-creased current ripple occurs, as shown in Fig. 18(b). Duringtime interval in Fig. 17, the master converter turnson at its second valley, which increases its switching period and,therefore, increases the peak of the period ramp. The increasedpeak of the period ramp is sampled, divided by two, and ap-plied in the next switching cycle. However, during time interval

, the master once again turns on at its first valleyand, as a result, an improper phase shift occurs. Although the


Fig. 18. Effect of frequency limit and valley switching on input-current ripple.

interleaving phase shift is initially poor at the onset of the fre-quency limit, the tendency of the circuit is to correct itself, asshown in Fig. 18(a). It should be noted that since the slave nat-urally operates with a higher switching frequency when oper-ating without synchronization, it reaches the minimum-periodlimit before the master, as shown in Fig. 17. In this example, themaster converter begins to switch on at its second valley imme-diately after the slave. However, as the mismatch between theconverters increases, it may happen that the master reaches theminimum period limit well after the slave converter.

C. Effect of Frequency Limit on Input-Current Distortion

It is well known that in a boost converter operating at theDCM/CCM boundary, PFC is achieved by keeping switchon-time constant during a half line cycle, which forcesthe inductor current averaged over a switching cycle, ,to be proportional to instantaneous input voltage , i.e.,

, where the resonant period is consid-ered much shorter than switching period . Since the twoconverters are interleaved, the input current averaged over aswitching cycle is simply twice the average individual inductorcurrent. By limiting the maximum switching frequency, theboost converters effectively operate in DCM for a portion of theinstantaneous input voltage. The average current is therefore nolonger proportional to instantaneous input voltage , i.e.,

(6)

When the resonant period is taken into consideration, an abruptchange in the average input current can occur when the switchturn-on moment skips from one valley to the next. As a result,current distortion is introduced as shown in Fig. 19, which leadsto a further degradation in power factor. Fig. 19 is obtainedthrough SIMPLIS simulation using a 250-kHz frequency limit.However, it should be noted that although power factor PF is lessthan 0.99, total harmonic distortion THD indicates that the cur-rent harmonics are well below the EN61000-3-2 limit. It should

Fig. 19. Input current and voltage with and without frequency limit.

be also noted that the waveform of the input current with fre-quency limit at in Fig. 19 is similar to the linecurrent waveform of a DCM boost PFC converter operating witha constant switching frequency presented in [5].

IV. SUMMARY

In this paper, four open-loop interleaving methods forDCM/CCM boundary boost PFC converters with a master-slaverelationship are thoroughly analyzed.

With open-loop synchronization, the slave converter can besynchronized to the turn-on or to the turn-off instant of themaster converter. In both cases, the converters can operate ei-ther with current-mode or voltage-mode control.

It is shown that the only open-loop method that results instable operation is the synchronization of the slave converter tothe turn-on instant of the master converter, where each converteroperates with current-mode control.

To limit the current-sharing error below a reasonable 20%,which corresponds to 10% tolerance of the boost inductances,the master and the slave should be identified during the initial-ization phase. Otherwise, the current sharing error can be as highas 60%, which is practically unacceptable.

Effects of mismatched inductances, phase-shift error,switching-frequency limit, and valley switching on the inputcurrent ripple and input current distortion are discussed indetail.

REFERENCES

[1] J. S. Lai and D. Chen, “Design consideration for power factor correc-tion boost converter operating at the boundary of continuous conduc-tion mode and discontinuous conduction mode,” in Proc. IEEE AppliedPower Electronics Conf. (APEC), Mar. 1993, pp. 267–273.

[2] J. W. Kim, S. M. Choi, and K. T. Kim, “Variable on-time control ofthe critical conduction mode boost power factor correction converterto improve zero-crossing distortion,” in Proc. IEEE Power Electronicsand Drive Systems Conf. (PEDS), Nov. 2005, pp. 1542–1546.

[3] Y.-K. Lo, J.-Y. Lin, and S.-Y. Ou, “Switching-frequency controlfor regulated discontinuous-conduction-mode boost rectifiers,” IEEETrans. Ind. Electron., vol. 54, no. 2, pp. 760–768, Apr. 2007.


[4] M. M. Jovanovic and Y. Jang, “State-of-the-art, single-phase, activepower-factor-correction techniques for high-power applications—Anoverview,” IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701–708, Jun.2005.

[5] K. H. Liu and Y. L. Lin, “Current waveform distortion in power factorcorrection circuits employing discontinuous-mode boost converters,”in Proc. IEEE Power Electronics Specialists Conf.(PESC)., Jun. 1989,pp. 825–829.

[6] B. A. Miwa, D. M. Otten, and M. F. Schlecht, “High efficiency powerfactor correction using interleaving techniques,” in Proc. IEEE AppliedPower Electronics Conf. (APEC), Feb. 1992, pp. 557–568.

[7] L. Balogh and R. Redl, “Power factor correction with interleaved boostconverters in continuous-inductor-current mode,” in Proc. IEEE Ap-plied Power Electronics Conf. (APEC), Mar. 1993, pp. 168–174.

[8] C. H. Chan and M. H. Pong, “Input current analysis of interleavedboost converters operating in discontinuous-inductor-current mode,” inProc. IEEE Power Electronics Specialists Conf. (PESC), Jun. 1997, pp.392–398.

[9] P.-W. Lee, Y.-S. Lee, D. K. W. Cheng, and X.-C. Liu, “Steady-stateanalysis of an interleaved boost converter with coupled inductors,”IEEE Trans. Ind. Electron., vol. 47, no. 4, pp. 787–795, Aug. 2000.

[10] G. Yao, A. Chen, and X. He, “Soft switching circuit for interleavedboost converters,” IEEE Trans. Power Electron., vol. 22, no. 1, pp.80–86, Jan. 2007.

[11] J. Zhang, J. Shao, F. C. Lee, and M. M. Jovanovic, “Evaluation of inputcurrent in the critical mode boost PFC converter for distributed powersystems,” in Proc. IEEE Applied Power Electronics Conf. (APEC), Feb.2001, pp. 130–136.

[12] T. Ishii and Y. Mizutani, “Power factor correction using interleavingtechnique for critical mode switching converters,” in Proc. IEEE PowerElectronics Specialists Conf. (PESC), May 1998, pp. 905–910.

[13] T. Ishii and Y. Mizutani, “Variable Frequency Switching of Synchro-nized Interleaved Switching Converters,” U.S. Patent 5 905 369, May18, 1999.

[14] B. T. Irving, Y. Jang, and M. M. Jovanovic, “A comparative study ofsoft-switched CCM boost rectifiers and interleaved variable-frequencyDCM boost rectifier,” in Proc. IEEE Applied Power Electronics Conf.(APEC), Feb. 2000, pp. 171–177.

[15] C. M. de Oliveira Stein, J. R. Pinheiro, and H. L. Hey, “A ZCT auxil-iary commutation circuit for interleaved boost converters operating incritical conduction mode,” IEEE Trans. Power Electron., vol. 17, no.6, pp. 954–962, Nov. 2002.

[16] T. F. Wu, J. R. Tsai, Y. M. Chen, and Z. H. Tsai, “Integrated circuitsof a PFC controller for interleaved critical-mode boost converters,” inProc. IEEE Applied Power Electronics Conf. (APEC), Feb. 2007, pp.1347–1350.

[17] M. S. Elmore, “Input current ripple cancellation in synchronized, par-allel connected critically continuous boost converters,” in Proc. IEEEApplied Power Electronics Conf. (APEC), Mar. 1996, pp. 152–158.

[18] M. S. Elmore and K. A. Wallace, “Zero Voltage Switching SuppliesConnected in Parallel,” U.S. Patent 5 793 191, Aug. 11, 1998.

[19] A. Jansen, “Master-Slave Critical Conduction Mode Power Converter,”U.S. Patent Application 2006/0077604, Apr. 13, 2006.

Laszlo Huber (M’86) was born in Novi Sad, Yu-goslavia, in 1953. He received the Dipl. Eng. degreefrom the University of Novi Sad in 1977, the M.S.degree from the University of Nis, Nis, Yugoslavia,in 1983, and the Ph.D. degree from the University ofNovi Sad in 1992, all in electrical engineering.

From 1977 to 1992, he was an Instructor at theInstitute for Power and Electronics, University ofNovi Sad. In 1992, he joined the Virginia PowerElectronics Center at Virginia Tech, Blacksburg, asa Visiting Professor. From 1993 to 1994, he was

a Research Scientist at the Virginia Power Electronics Center. Since 1994,he has been a Senior Member of the R&D Staff at the Power ElectronicsLaboratory, Delta Products Corporation, Research Triangle Park, NC, the Ad-vanced R&D unit of Delta Electronics, Inc., Taiwan, one of the world’s largestmanufacturers of power supplies. His 30-year experience includes the analysis,simulation, and design of high-frequency, high-power-density, single-phaseand three-phase power processors; modeling, simulation, evaluation, andapplication of high-power semiconductor devices; and modeling, simulation,analysis, and design of analog and digital electronics circuits. He has publishedover 80 technical papers and holds four U.S. patents.

Brian T. Irving was born in Ossining, NY, in 1973.He received the B.S. degree in electrical engineeringfrom the University of Binghamton, Binghamton,NY, in 1998.

From 1996 to 1998, he was an Engineer at Ce-lestica Inc., Endicott, NY, where he designed PFCboost circuits for server power supplies. Since 1998,he has been a Member of R&D Staff at the PowerElectronics Laboratory, Delta Products Corporation,located in Research Triangle Park, NC. His researchinterests include high-density, single-phase PFC cir-

cuits, control techniques, current sharing, modeling, and simulation.

Milan M. Jovanovic (F’01) received the Dipl. Ing.degree in electrical engineering from the Universityof Belgrade, Belgrade, Serbia.

Presently, he is the Chief Technology Officer of thePower Systems Business Group of Delta Electronics,Inc., Taipei, Taiwan, R.O.C.

ieee transactions on power electronics, vol. 23, no. 4, july 2008 1649 open-loop ... loop co… ·...

Documents