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176 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 4, APRIL 2001

Improved Inversion Channel Mobility for 4H-SiCMOSFETs Following High Temperature Anneals in

Nitric OxideG. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. K. Chanana, Robert A. Weller, Member, IEEE,

S. T. Pantelides, Leonard C. Feldman, Member, IEEE, O. W. Holland, M. K. Das, and John W. Palmour, Member, IEEE

AbstractResults presented in this letter demonstrate that theeffective channel mobility of lateral, inversion-mode 4H-SiC MOS-FETs is increased significantly after passivation of SiC/SiO

2

inter-face states near the conduction band edge by high temperature an-neals in nitric oxide. Hilo capacitance-voltage (CV) and ac con-ductance measurements indicate that, at 0.1 eV below the conduc-tion band edge, the interface trap density decreases from approx-imately

2 1 0

1 3 to2 1 0

1 2 eV 1 cm 2 following anneals innitric oxide at 1175 C for 2 h. The effective channel mobility forMOSFETs fabricated with either wet or dry oxides increases by anorder of magnitude to approximately 3035 cm2 V-s following thepassivation anneals.

Index TermsInterface states, mobility, MOSFETs, nitridation,oxidation, silicon carbide.

I. INTRODUCTION

S ILICON carbide is the only wide band gap semiconductorthat has a native oxide, and metal-oxide-semiconductorfield effect transistors (MOSFETs) have been fabricated using

both 4H- and 6H-SiC. The 4H polytype has higher bulk carrier

mobility [1], and is hence the polytype of choice for power

MOSFET fabrication. However, reported channel mobilities for

4H n-channel, inversion mode devices are substantially lower

than for 6H-MOSFETs. For power device applications, the

advantage provided by 4H-SiC of lower epilayer resistance for

a given operating voltage is compromised by the low channel

mobility. Schorner, et al. [2] attribute the poorer performance

of 4H devices to a large, broad interface state density located

at approximately 2.9 eV above the valence band edge in both

Manuscript received November 17, 2000; revised December 27, 2000. Thiswork was supported by DARPA Contract MDA972 98-1-0007 and EPRI Con-tract W0806905. Research at Oak Ridge National Laboratory sponsored bythe Division of Material Sciences, U.S. Department of Energy, under ContractDE-AC05-00OR22725 with UT-Battelle, LLC. The review of this letter was ar-

ranged by Editor T.-J. King.G. Y. Chung, C. C. Tin, and J. R. Williams are with the Physics Department,Auburn University, AL 36849 USA (e-mail: williams@physics.auburn.edu).

K. McDonald and R. K. Chanana are with the Department of Physics andAstronomy, Vanderbilt University, Nashville, TN 37235 USA.

R. A. Weller is with the Department of Electrical Engineering and ComputerScience, Vanderbilt University, Nashville, TN 37235 USA.

S. T. Pantelides and L. C. Feldman are with the Department of Physics andAstronomy, Vanderbilt University, Nashville, TN 37235 USA. They are alsowith Oak Ridge National Laboratory, Oak Ridge, TN 37831 USA.

O. W. Holland is with the Solid State Division, Oak Ridge National Labora-tory, Oak Ridge, TN 37831 USA.

M. K. Das and J. W. Palmour are with Cree Research, Inc., Durham, NC27713 USA.

Publisher Item Identifier S 0741-3106(01)02864-6.

polytypes. More of these states lie in the band gap for 4H-SiC

eV compared to 6H-SiC eV where they

act to reduce channel mobility through field termination,

carrier trapping and Coulomb scattering. Afanasev, et al. [3]

proposed that interface states in SiC/SiO structures result from

carbon clusters at the interface and defects in a near-interface

sub-oxide that is produced when the oxidation process is

terminated. The large interface trap density near the conduction

band edge proposed by Schorner, et al. has been observed ex-perimentally for both n-SiC [4], [5] and p-SiC [6]. Li, et al. [7]

originally reported improvements in the electrical performance

of dry oxides on 6H-SiC annealed in nitric oxide (NO). We

have recently annealed wet oxides in NO [8] and found that

the interface state density near the conduction band edge in

n-4H-SiC can be reduced to levels comparable to the interface

state density near the conduction band edge in 6H-SiC. Results

presented in this letter show that the effective channel mobility

for inversion-mode 4H-SiC MOSFETs improves significantly

following high temperature anneals in nitric oxide.

II. EXPERIMENT

Five micron 4H-SiC -epilayers cm

on n -substrates were oxidized for MOS capacitor fabrication

using standard, wet oxidation techniques that have been de-

scribed elsewhere [9]. Dry oxide layers were also grown using

identical procedures except that the TCA and H O bubblers

were bypassed. Following oxidation (wet or dry) to produce

40 nm oxide layers, samples were annealed in a second fur-

nace in NO (1 atm, 0.5 l/min, 1175 C, 2 h). Molydenum was

sputter-deposited to form oxide gate contacts, and large area

backside ohmic contacts were formed to the substrates using

Ag colloidal paste. Standard high frequencylow frequency

(1 MHz/quasistatic) capacitancevoltage (CV) and ac conduc-

tance techniques were used for interface state density measure-ments near the conduction band edge.

Lateral 4H-SiC MOSFETs were also fabricated with either

3 m cm or 10 m cm -4H-epilayers.

All dry and wet oxide layers (thickness 40 nm) were grown

and passivated at either Auburn or Vanderbilt except for one

control wafer with 3 m epi that was oxidized at Cree, Inc. A

40 nm oxide layer was grown on this control wafer using Crees

standard oxidation process1200 C dry O for 2.5 h, 1200 C

Ar for 1 h and 950 C wet O for 3 h. Lateral MOSFETs were

fabricated and characterized at Cree on the control wafer and

07413106/01$10.00 2001 IEEE

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CHUNG et al.: IMRPOVED INVERSION CHANNEL MOBILITY FOR 4H-SiC MOSFETS FOLLOWING HIGH TEMPERATURE ANNEALS IN NITRIC OXIDE 177

Fig. 1. Interface state density for n-4H-SiC MOS capacitors before and afteranneals in NO at 1175 C for 2 h. The hilo CV measurements were madeat room temperature and confirmed with AC conductance measurements.Re-ox refers to samples that were not annealed in NO. In agreement with thesuppositions of Schorner, et al. [2], the passivation anneal is noticeably moreeffective for 4H-SiC.

on a second wafer (also with 3 m epi) that was oxidized at

Auburn using the wet 1100 C oxidation process described in

[9] and subsequently passivated with NO at Vanderbilt. Nitrogensource/drain implants for both wafers were activated at Cree

with a 3 h, 1200 C Ar anneal. Sputtered Mo was patterned to

form MOSFET gates with dimensions 250 m 250 m.

Lateral MOSFETs with dry oxides were processed entirely at

Auburn starting with 10 m -epilayers. These devices had a

gate length of 120 m and source/drain dimensions of 200 m

(length) 400 m (width). Molydenum was sputter-deposited

for gate contacts. Nitrogen source/drain implants were annealed

at 1575 C for 30 min inside a polycrystalline SiC pillbox in

1atm of flowing Ar. Nickelwas depositedon thesource/drain re-

gions; however, the contacts were not annealed prior to making

channel mobility measurements.

III. RESULTS AND DISCUSSION

The results of standard hilo (quasistatic) CV measure-

ments for -4H-SiC MOS capacitors following NO passiva-

tion anneals of 2 hr at 1175 C are shown in Fig. 1. Re-ox

refers to samples that were not annealed in NO. Re-oxidation

is a standard wet oxidation termination step [10] that is carried

out at several hundred degrees below the oxidation temperature

of 1100 C in order to reduce the interface state density near

mid-gap for -SiC/SiO [4], [10], [11]. As shown in Fig. 1, NO

passivation reduces the interface state density significantly. The

trap density at 0.1 eV below the conduction band edge decreases

by approximately one order of magnitude (from aboutto eV cm after NO annealing. AC conductance

measurements performed at Cree for similar samples confirm

the CV data presented in Fig. 1.

The results of mobility measurements for a lateral 4H-SiC

MOSFET fabricated with a dry oxide are shown in Fig. 2. The

device hasa peak channel mobility of approximately 30 cm /Vs,

and shows a 14 improvement in peak mobility as a result of

the NO passivation anneal. Similar results are obtained for wet

oxide MOSFETs. Fig. 3(a) shows a plot of drain current versus

gate voltage that was used to determine a peak effective mo-

bility of 5 cm /V-s for a device fabricated with Crees standard

drywet oxide. Fig. 3(b) shows the improvement in mobility

Fig. 2. Field effect mobility for dry oxide 4H-SiC MOSFETs fabricated withand without an NO passivation anneal at 1175 C for 2 h.

Fig. 3. (a) Drain current as a function of gate voltage for a MOSFETfabricated with Crees standard, drywet oxidation procedure. Analysis( @ I = @ V ; V = 5 0 mV ) resulted in a peak effective mobility of 5 cm /Vs.(b) Mobility versus gate voltage and I 0 V characteristics for a devicefabricated with a wet oxide grown at Auburn and an NO anneal performed atVanderbilt. I 0 V characteristics for the standard device are included forcomparisons that show reduced threshold voltage and significantly improvedturn-on behavior for the passivated MOSFET.

that can be achieved with NO passivation. Drain current-gate

voltage characteristics are also plotted in Fig. 3(b) for the stan-dard and passivated MOSFETs. The standard device exhibits the

soft turn-on, high threshold, and single digit mobility [Fig. 3(a)]

typical of 4H-SiC MOSFETs. However, the MOSFET annealed

in NO has a 5 V threshold, relatively sharp turn-on, and a peak

channel mobility of 37 cm /Vs.

The characteristics of both the dry and wet oxide devices are

consistent with a lower interface state density near the conduc-

tion band edge. Also, the mobility versus gate voltage behavior

for both the wet and dry oxide devices is similar to that of sil-

icon MOSFETs [12] with only a 1520% reduction in mobility

at the higher gate voltages where the devices will typically be

operated. However, unlike silicon, the mobilities reported here

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178 IEEE ELECTRON DEVICE LETTERS, VOL. 22, NO. 4, APRIL 2001

for SiC are a much smaller fraction of the bulk mobility (10%

for SiC compared to 50% for Si). This difference can be at-

tributed to the fact that, even after NO passivation, the interface

state density near the conduction band edge is still ten times

higher for SiC compared to Si. Full wafer testing for the wet

oxide devices resulted in a yield of 90% and an average effec-

tive mobility of 33 cm /Vs. Furthermore, every working device

on the 3.5 cm diameter wafer had a peak mobility greater than30 cm /Vsan indication that the NO passivation process was

very uniform.

Measured channel mobilities for lateral 4H-SiC MOSFETs

fabricated with standard epilayers and standard thermal ox-

idation techniques are typically well below 10 cm /Vs. A

number of attemptsincluding the NO passivation process

reported hereinhave been undertaken in an effort to improve

the effective channel mobility. Sridevan, et al. [13] reported

n-channel mobilities as high as 165 cm /V-s for deposited

oxides subsequently annealed in wet and Ar. Ogino, et al.

[14] observed significant improvements in mobility (as high as

99 cm /V-s) following low dose N implants into the channel

region that were designed to adjust device threshold voltage.Yano, et al. [15] fabricated MOSFETs with wet thermal oxides

grown on the (11 0) face of 4H-SiC and reported effective

channel mobilities of around 30 cm /Vs. However, to our

knowledge, the results reported in this letter are the first to

show substantial improvement in the inversion channel mo-

bility for lateral n-channel MOSFETs fabricated with standard

thermal oxidation techniques and standard 4H-SiC. Whether

used separately or in conjunction with other techniques such as

low dose implantation, the NO passivation process represents

significant progress in 4H-SiC MOSFET development.

REFERENCES

[1] J. B. Casady and R. W. Johnson, Status of silicon carbide (SiC) as awide band gap semiconductor for high temperature applications: A re-view, Solid-State Electron., vol. 30, no. 10, pp. 14091422, 1996.

[2] R. Schorner, P. Friedrichs,D. Peters, and D. Stephani, Significantly im-proved performance of MOSFETs on silicon carbide usingthe 15R-SiCpolytype, IEEE Electron Device Lett., vol. 20, pp. 241244, May 1999.

[3] V. V. Afanasev, M. Bassler, G. Pensl, and M. Schulz, IntrinsicSiC/Si Ointerface states, Phys. Stat. Sol. (A), vol. 162, pp. 321337, 1997.

[4] G.Y. Chung,C. C.Tin, J.H. Won, and J.R. Williams, Theeffect ofSi:Csource ratio on SiC/Si O interface state density for nitrogen doped 4Hand 6H-SiC, Mater. Sci. Forum, vol. 338342, pp. 10971100, 2000.

[5] M. K. Das, B. S. Um, and J. A. Cooper Jr., Anomalously high densityof interface states near the conduction band in Si O /4H-SiC MOS de-vices, Mater. Sci. Forum, vol. 338342, pp. 338342, 2000.

[6] N. S. Saks, S. S. Mani, and A. K. Agrwal, Interface trap profile nearthe band edges at the 4H-SiC/Si O interface, Appl. Phys. Lett., vol. 76,pp. 22502252, 2000.

[7] H. Li, S. Dimitrijev, H. B. Harrison, and D. Sweatman, Interfacial char-acteristics ofN O and NOnitridedSi O grownon SiCby rapid thermalprocessing, Appl. Phys. Lett., vol. 70, pp. 20282030, 1997.

[8] G. Y. Chung et al., Effect of nitric oxide annealing on the interface trapdensities near the band edges in the 4H polytype of silicon carbide,

Appl. Phys. Lett., vol. 76, pp. 17131715, 2000.[9] G. Y. Chung et al., Interface state densities near the conduction band

edge in n -type 4H- and 6H-SiC, in Proc. 2000 IEEE Aerospace Conf.,vol. 1, 2000, pp. 10011005.

[10] L. A. Lipkin and J. W. Palmour, Improved oxidation procedures for re-ducedSi O /SiCdefects,J. Electron.Mater., vol.25, pp.909915, 1996.

[11] M. K. Das, J. A. Cooper, and M. R. Melloch, Effect of epilayer charac-teristics and processing conditions on the thermally oxidized SiO /SiCinterface, J. Electron. Mater., vol. 27, pp. 353357, 1998.

[12] S. C. Sun and J. D. Plummer, Electron mobility in inversion and ac-cumulation layers on thermally oxidized silicon surfaces, IEEE Trans.

Electron Devices, vol. ED-27, pp. 14971508, Aug. 1980.[13] S. Sridevan and B. J. Baliga, Lateral n-channel inversion mode 4H-SiC

MOSFETs,IEEE ElectronDevice Lett., vol.19, pp.228230, July1998.[14] S. Ogino, T. Oikawa, and K. Ueno, Channel doped SiC MOSFETs,

Mater. Sci. Forum, vol. 338342, pp. 11011104, 2000.[15] H. Yano et al., Anisotropy of inversion channel mobility in 4H- and

6H-SiC MOSFETs on (1120) face, Mater. Sci. Forum, vol. 338342,pp. 11051108, 2000.

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