ilfa-the future of the pcb

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The Future of the PCBArnold Wiemers

Introduction Preliminary information:

The CAD layouters and the assembly developers may practicallyreceive any PCB quality they demand.

The PCB manufacturers as well do not have to worry: The PCB willalso be in demand in future.

The tendency is evident: The PCB will become more complex andmore universal (figure 1, figure 2). However, already at this point,the first drop of bitterness casts a cloud over the enthusiasm: ThePCB will also become more sensitive and more expensive.

To explain the technological developments, I would like to give youan overview of the essential aspects by which the production ofmultilayer boards is influenced. This overview will indicate whichvariation ranges of materials, galvanic surface-finishes, mechani-cal treatments and image structures are available. It will reveal in-dispensable organization principles to be exactly considered, if theconstruction and specification of a PCB by a layouter is to be suc-cessful.

Figure 1: Development of the conductive pattern structures

Year

300

250

200

150

100

50

Con

duct

ive

patte

rn s

truc

ture

s in

µm

89 90 91 92 93 94 95 96 97 98 99

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The Future of the PCB

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Figure 2: Development of the pad and track geometries

We do not talk about the really big sensations here, but the stand-ard products are interesting which will define the daily work of thelayouter, of the PCB manufacturers and of the assembly providersin one or two years.These products will be 4, 6, or 8-layer boards as carrier for COB orMCMs or simply as normal, real PCBs.

One interesting aspect is the indication of the actual possibilites ofthe development of 200 µm to 150 µm, 100 µm and finally 50 µm-structures (figures 3 and 4).

The reference is an assumed PCB, a multilayer board with a con-ductive pattern structure of a track-width and of a track-distance of150 µm.

Due to the current discussions concerning high-technology in thefield of the PCB production, a 150 µm-PCB should nowadays be acommon standard product for each PCB manufacturer. The tech-nical specification of an assembly of such parameters as wellshould not cause any problems for the CAD designers.

However, we will see: There are some questions which still requiresome answers.

Pad and track geometries (µm)

300 200 200 200 100 80

1600 600 500 400 200 100

SIL/DIL SMD Fine-Pitch MCM/COB

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Figure 3: Carrier module for COB / flip-chip

Figure 4: Switching module with COB

MFT: Example: flip-chip

Flip-chip on carrier module

80µm

MFT: Example: COB-module

Switching module with COB

80µm

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Base materials The appropriate material for an electronic circuit has actually to bechosen BEFORE starting with the layout.The discussions regarding electromagnetic compatibility, high-speed circuits and impedance-control has already been linked withthe technical features of the material assuming that the layouter isfamiliar with material parameters like Tg-value (glass transitiontemperature), eR-value (dielectric feature) and material composi-tion (glass fabric, resin content, chemical classification of matter.The layouter must also know the prices (figure 5).

Figure 5: Base materials for PCBs

The PCB manufacturer's logistics has to ensure a stockpiling intime. This is not a simple task because the variety of materialtypes, material thicknesses and copper clads may lead to an ex-ploding stock.

Group Composition Tg εr Relative costs

BT Bismaleinimide triazine resinwith silica glass

180-220

3.9-4.9

5.3

CE Cyanate ester with silica glass 230 3.6 4.5

CEM1 Paper phenolic core with FR4-outer layers

130 4.7 0.95

CEM3 Glass mat (or glass felt) core with FR4-outer layers

130 5.2 0.95

FR2 Phenolic resin paper 105 4.7 0.73

FR3 Epoxy paper 110 4.9 0.85

FR4 Epoxy glass fibre laminate135-170

4.71Reference

FR5 Epoxy glass fibre laminate with crosslinked resin system

160 4.6 1.4

PD Polyimide resin with aramide-reinforcement

260 3.5 6.5

PTFE Polytetrafluoroethylenewith glass or ceramics

240-280

2.2-10.2

32-78

CHn High-interlaced hydrocarbons with ceramics

3004.5-9.8

90

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The list of possible inner layer combinations makes this aspectmore obvious (figure 6). However, if these stocks can be reduceddue to future orders, will become more and more doubtful.

Whereas base laminates are durable for years, some prepregtypes can only be stockpiled for several months. If the prepregs arenot used within this period of time, they will have to be eliminated.Over-stock prepregs would produce a delamination of the multilay-er board and the product could therefore not be used.

A far more complex task for the PCB manufacturer is to adapt theproduction processes to the different characteristics of the basematerials which are based on the altered combination of chemicalbasic substances.It cannot be taken for granted that the contacting of complex multi-layer levels on FR4 (glass) is of the same quality than on PTFE(glass/ceramics) or on PD (polyimide + aramide). In particular, ifthe frequently very different and decisive resin proportions andqualities of the materials are also taken into account.

Figure 6: Laminates for multilayer board inner layers

Multilayer board laminates

Laminates are indicatedwithout Cu-clad

0.0500.0600.0750.1000.2000.2500.3600.4600.7100.9301.0001.1301.4301.8601.9302.330

0.0500.0600.1000.200

0.0050.0090.0170.0350.0700.105

Laminate Prepregs Cu-clad

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It can also not be taken for granted that these different materialscan be drilled without reducing the quality of the hole walls andwithout reducing the reliability of the solder resists to adhere to thesurface.

The fact that base materials for PCBs can be produced in such anindividual form is very much a point in the favour of the PCB man-ufacturers. The actual solution, however, was found by the part-ners of the PCB manufacturers, the chemical and materialmanufacturers. Their contribution to this success was the most im-portant one.

Conductive pattern structuring

The miniaturization of the components also requires miniaturizedconductive pattern resolutions. The structure exposure therefore be-comes a considerable challenge.

In the general opinion, if the problem is solved to expose track-widths and track-distances of 80 µm or even 50 µm, all subsequentproduction steps are inferior.

This is unfortunately NOT the case.

The laminating of the photo laminate (before) and the etching of thestructures (afterwards) belong to the production process of the con-ductive pattern structuring.

Films (standard), glass master plates (scarcely) and laser machines(even more rarely) are available as exposure tools. If diazofilms(copies of the original plot) were used in the past, black films (origi-nal plots) are now commonly used. The extraordinary quality ofthese films allows structures up to 60 µm. If this threshold range can-not be reached, the common hardware (exposure devices) and theambient conditions (clean-room conditions) are often the reason forthis.

In case of laser machines, the limit is near 40 µm. Decisive for thebetter results of the laser exposure, compared with the film, is theregister accuracy to the drilling pattern (optical registration), the fea-sibility of reproduction (no misalignments), the generally smaller me-chanical tolerances (reception systems, no vacuum fixing), and thefact that some production steps are no longer needed (figure 7).

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The photo laminate has to take up the image structure during the ex-posure and must completely "store" it. Due to the exposure process,the molecular structure of the laminate changes - it cures. It is nec-essary that the curing is effected homogenously over the total thick-ness of the photo laminate to receive a fine, sharp-contouredconductive pattern which is also stable at the edges.An increase in the light energy (scattering) is not sufficient. Thinnerphoto laminates with a thickness of 20 up to 25 µm (the standard is38 µm) will ensure these demands. Unfortunately, these thin lami-nates are only rarely available at the moment (figure 8).

Figure 7: Comparison between diazofilm, black film and laser direct imaging

Time 24h 10h 3h

Tolerance 0.1mm 0.1mm 0.03mm

Expose conductive pattern � � �

Register film � � ❍

Laminate PCBs � � �

Plate PCBs � � �

Drill PCBs � � �

Retouch diazofilm � ❍ ❍

Produce diazofilm � ❍ ❍

Measure film � � ❍

Verify film � � ❍

Develop film � ❍ ❍

Produce photo plots � � ❍

Documentation � � �

CAM processing � � �

� required❍ not required

Diazofilm Black film Laser

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Figure 8: Comparison between 38 µm and 20 µm laminate

Finally, the etching process decides, if the structuring of the con-ductive pattern is successful. This production step is the most un-popular one for each PCB manufacturer, if the layout demandstracks and distances smaller than 150 µm. The defined application(spraying) of the liquid etchant on the PCB and the subsequent re-moval (washing) cannot be carried out so precisely as demandedeven by computer-controlled machines. The losses of 10 up to 30µm regarding structures to be produced are definitly unpleasant insuperfine-line or in super-microfine-line technology.

Holes + vias The drilling of PCBs is THE current subject, i.e, the connection ofselective layers of a multilayer board (figure 9). The discussion in-dicates the necessity to assign at least a rough classification sys-tem to the circulating terms.

Functional classes

"Holes" are used for the reception of components or for the fixingof the future assembly (either in the terminal device or in the as-sembly machine).A hole goes through every layer of a PCB.A hole may take over the function of a via.

Structure exposure

38 µm photo laminate17 µm copper clad

100 µm inner layers

200ym 200ymExposureStandard

Superfine-line

20 µm photo laminate5 µm copper clad

50 µm inner layers

100ym 100ymExposure

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Figure 9: Different via types for PCBs

„Vias ensure the signal flow over several layers of a PCB.A via connects at least 2, more than 2, but at best all layers of aPCB.A via should never take over the function of a hole.

If a via connects ALL layers of a PCB, then it is called a "through-via".

If a via connects two or more than two layers but not all layers of aPCB, it is called a "partial via".

There are two variants of partial vias: as "blind via" or as a "buriedvia".

Blind vias ALWAYS connect one or several - but not all - inner lay-ers of a multilayer board to an outer layer.

Buried vias connect 2 or more layers inside the multilayer board,however, they NEVER produce any contact to an outer layer.

Via types in UTMs for MFT

1.0

0.8

0.6

0.4

0.2

0.0

BS

I2

I3

I4

I5

LS

Via 0.25 up to 0.10 mm

Standard Buried Vias Blind Vias

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Mechanical classes

The term "micro via" indicates that the mechanical diameter of thisvia is considerably smaller than 100 µm. The threshold range is ap-prox. 50 µm.

From 100 µm on vias are called “via”.

Production technological classes

"Laser vias" are partial vias which are technically produced by a la-ser. Two adjacent layers may be connected. This technology canbe applied for common base materials. Through-vias are not pos-sible.

"Photo vias" are partial vias which are produced by the phototech-nical structuring and the subsequent galvanotechnical build-up ofthe laminate between adjacent layers. The isolation of the individ-ual, electronically active layers is effected by the laminate. Thepossible applications and the stability of this technology are subjectto intensive research.

"Plasma etching" in a plasma atmosphere produces partial vias, ifappropriate materials are used. This technique cannot be appliedfor standard base materials.Through-vias are not possible.

"Micro holes" are mechanically produced as usual. Available drill-ing tools have diameters up to minimum 0.1 mm. Therefore, bothpartial and through-vias can conventionally be drilled.

These technologies are altogether a treasure of alternatives at thedisposal of the PCB manufacturer and among which the CAD de-signer may have the choice. -

Or so it seems at first sight.

In practice, the via technologies have only the value of the sphereto which they are related. Regarding blind vias, a rule says that thevia-depth should not exceed the via-diameter. Otherwise, the gal-vanotechnical connection of the individual signal levels is problem-atic and not reliable. Due to this reason, the via-depth and the via-diameter must also be adapted to each other in case of "through-vias" (relation approx. 6 : 1).

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In case of laser vias, photo vias or during plasma etching, only twoadjacent layers may be connected. Necessary vias over more than2 layers or required through-vias must still be drilled mechanicallyso that a combination of technologies becomes necessary.

Without doubt, all connecting processes contribute to a considerableincrease in the density of image structures on the PCB.

Surface-finishes Additional connection technologies regarding the classic solderingprocess are nowadays the bonding and - relatively new - the glue-ing of components on the PCB. For each individual technology,there are very good solutions.

The requirements, however, increase, if different connection tech-niques are to be combined on one PCB because the componentsare not otherwise available or the reduced space requires suchmeasures. A variety of surface-finishes with different features areavailable (figure 10). Due to SMD components with fine-pitch dis-tances, plane surface-finishes are required. When choosing a sur-face-finish, the costs should not be neglected.

The good, old "tin lead" surface-finish cannot be recommended an-ymore, because the surface is too bended. This surface-finish isnot expensive, it should, however, only be used for THT compo-nents or in combination with SMD components in a grid distancenot less than 1.27 mm.

"Hot-air-leveling" is still a favourable alternative as well for standardSMDs (pitch-distance = 1.27 mm), with its process related surfaceroughness of 10 - 20 µm, however, too undefined.

"Nickel" is an alternative in case of mechanically loaded surface-finishes, if switching functions are directly guided via the surface.The soldering behaviour, however, is always temperamental.

"Copper" is generally not worth discussing. The advantage of theOSP variant "Entek+" is that it is not expensive.

"Immersion tin" offers a plane surface and is inexpensive. Theprocess can be easily handled within the production, the results,however, are not completely free of surprises.

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„"Immersion gold" and "galvanic gold" offer a considerably betterquality of the surface-finish.

The gold layer is 0.05 - 0.2 µm in case of immersion gold and 1.5µm in case of galvanic gold. The gold is applied on nickel. Both var-iants are easy to be soldered. Immersion gold is suitable for bond-ing aluminium wires which are adapted ON the nickel surface-finish. Gold will then be the corrosion protection.These surface-finishes are extraordinarily suitable for the glueingtechnique, if bright-copper is applied beneath the gold layer be-cause therefore the surface roughness is improved from > 4µm to< 1 µm.

"Immersion bond gold (reductive)" and "galvanic bond gold" areespecially adapted to the bonding technique. The thickness of thegold layers is 0.3 - 0.6 µm in case of "immersion bond gold" and 1- 2 µm in case of "galvanic bond gold".The bonding is carried out by gold wires IN the gold surface-finish.This gold as well is applied on nickel.

Figure 10: Galvanic surface-finishes for PCBs

In addition to the general definition of galvanic surface-finishes,there are also several metallizations which mainly take over thefunctions of solder depots completely replacing the solder pasteprint before the assembly process.

Galvanic surfaces Connection technique Relative costsSol-

deringBon-ding

Glu-eing

Tin lead + - - 1.00

Bond gold (immer-sion) + Au+ + 1.50

Bond gold (galvanic) + Au+ + 3.00

Entek+ + - - 1.00

Gold (immersion) + Al+ + 1.15

Gold (galvanic) + Al+ + 1.70

Hot-Air leveling + - - 1.00

Copper + - - 0.90

Nickel + - - 1.00

Tin (immersion) + - + 0.90

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Surface-finish combinations, "tin lead" for example with "partialgilding", are more rarely used at present. The reduced costs do notjustify the the complicated production process, especially in caseof smaller series.

All things considered, the scope of galvanic surface-finishes is suf-ficient. In the opinion of the PCB manufacturers, the problems canbe found during the further processing in the assembly technology.The variety of the surface-finishes consequently requires a varietyof assembly preparations and of soldering techniques to be used.There is still a demand for harmonization.

Lacquers + pastes The lacquers used in the PCB production are wrongly in the shad-ow of the ubiquitously discussed high-technology.

The solder mask is generally assumed as a kind of solder resist.

Its technical features, however, are considerably more impressing.The lacquers have a high density, they are resistant to scratchesand have a sparkover voltage up to the range over 100KV/mm.The dielectric characteristics of these substances are frequently ig-nored. On an epoxy basis, they have an eR-value of approx. 4.5which is a constructive quality regarding EMC requirements. Thephototechnical treatment allows a structural resolution with link-widths about 100 µm (figure 11) so that the sensitive spaces of a400µm-pitch of SMD-ICs may be covered which considerably con-tributes to the prevention of short-circuits.

The limit of the silkscreen is now 1.0 mm for text height-sizes and180 µm for text line widths. An identification print would otherwisebe impossible for many SMD layouts.

Also printable on the PCB is the "peelable solder resist" for protect-ing zones which are not allowed to absorb tin during the solderingprocess, the "via filling mask" for stabilizing the depression duringthe in-circuit test and the "carbon conductive lacquer" for the partialconductivity of the PCB's surface-finish. The "solder paste mask"is generally used for SMD-PCBs for applying the solder before thereflow soldering process.

Less known is the print of "resistances" and "capacities" in discretevalues directly on the inner layers of multilayer boards.

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Within permissible tolerances, component and assembly costs aretherefore saved. Moreover, additional space is gained on the outerlayers. The techniques are well-tested, however, there are only eco-nomical in case of larger series.

Figure 11: Threshold ranges for the application of solder mask

Testability The electronic test of the PCB without assemblies is now a weakpoint in the production process since the image structures havebeen reduced to 150µm and even less.

The reason for this is not the continuously repeated discussion, ifand how it is possible to test against Gerber data. This would bethe second step anyway. The dilemma is revealed in the first step,the mechanical adaptation of the PCB to ensure the contact be-tween the PCB pads and the testing machine.

The "pin adapter" has been a good solution for a long time. Eachpad is contacted with the tip of a pin which basis is situated withinthe test field of the machine. The test field contains pins in a grid of 1.27 mm. If the distancefrom pad to pad on a PCB smaller than 1.27 mm, the pins will haveto be aligned to the adjacent grid point within the test field.

Solder mask

0.6m

m

100ym470ym

0.3m

m

1.27mm 0.635mm

50ym235ym

0.2m

m

50ym100ym

0.4mm

Standard Superfine-line

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In case of a pad distance smaller than 0.8 mm or in case of denselypacked high-performance ICs, the excursion of the pins is so im-mense that the contact between PCB and test field is interrupted.Or, the pins are so dense that they touch and therefore provoke in-correct error-messages.

A pin adapter for a high-dense PCB is really a little piece of art. Thetest time of 1 - 2 seconds is unequalled. The production costs of1.000 - 3.000,- DM are, however, too high for prototypes and small-er series, and too much time as well, one or several days, is need-ed for installing the device.

An alternative for the complete and simultaneous test of all con-nection points is the "translator". The adaptation is effected via afoil "translating" between test piece and machine. The foil is elec-trically neutral, it becomes however conductive due the the pres-sure in the Z-axis.Since the pads on the PCB are 20 - 30 µm above the PCB level,the required conductive compaction is partially produced. The con-tact to the testing machine is mechanically established via an inter-mediate adapter. This method is well-tested, good and quick.However, it is too complicated and not economical in case of pro-totypes and smaller series.

An elegant solution would be the "flying-probe" or "finger tester".One or several motor pairs each control a contact pin and place iton the PCB pad. The pads to be tested are activated one after theother and measured against each other or against a fixed ref-erence. The adapter exists only virtually in this system as asoftware programme, no mechanical installation is required. Thetime needed for preparations is 1 - 3 hours and fine-pitch compo-nents can be reliably tested. However, a relatively long test time isrequired: For complex boards 30 minutes or even more may benecessary. And even this system must be correctly aligned if theareas to be tested are below 100 µm because the tolerance of thepositioning accuracy will then lead to misleading error messages.

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In order to recognize production errors even in advance, "AOI-test-ers" are increasingly used. These devices compare the image of aPCB or of an inner layer of a multilayer board with a stored refer-ence or with stored data by means of optical record systems. Thefinal product, the complete multilayer board, can therefore not betested.

The PCB manufacturer has to cope with the deficit that the testingtechnology is not perfect. However, to be able to offer a sufficienttesting in spite of this fact, the strategy of combined tests is used.This may signify that high-density zones are tested by a finger-test-er and zones of lower densities by a pin adapter. It may also be ap-propriate to test dense zones by an automatic device and high-density zones manually and optically by a camera system.

It is not very pleasant if zones which cannot be tested are ignored.

Special PCBs Representing numerous unspectacular innovations, the efforts inthe fields of the sensor and cooling technology should be men-tioned.

There are different possibilities to control the heat development onan active assembly. The heat transfer via a loop of liquids WITHINthe PCB is the general option. In combination with a micro pump, theheat is absorbed by the liquids in the heat-generating zones, trans-ported to cooling zones and carried-off to the ambient air by control-led thermovias.

For measuring and generating defined electromagnetic fields, sen-sor coils on thin laminates are appropriate.The production of thesecoils and sensors can be realized with considerable smaller toler-ances by means of PCB technologies than by the conventionalwinding technique.It is also remarkable that PCBs will have quite a different quality inthis case. They are not only carriers for component but a compo-nent themselves.

Tolerances The official (acc. to DIN) tolerance of 100 µm is permissible in thePCB production. The conductive pattern and the solder mask mayhave this misalignment to the drilling pattern reference.

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Many elementary design-rules are based on this tolerance defini-tion.

"100 µm" do not seem very impressing. In connection with otherrules for the qualitative judgement of a PCB, however, the result maybe some remarkable restrictions.

Example:"Annular rings of vias". Basically, an annular ring around a via hasto be closed and has to be 100 µm at the thinnest section. To en-sure that in case of a misalignment of 100 µm, the annular ring isstill 100 µm wide, the annular ring must be defined with 200 µm.

Since the ring is circulatory, the result for a pad to a via is that it hasto be 400 µm larger than the via diameter to be drilled (figure 12).

Due to these defaults, there is an inappropriate loss of space forthe tracks in case of vias < 0.4 mm. This tolerance must be reducedat least to the half. Therefore, the standards have to be changedfrom 100 µm to 50 µm and the register accuracy during the produc-tion of PCBs must be improved from 100 µm to 50 µm.

Figure 12: Tolerances for the annular rings of vias

Fit-tolerances for vias

Via0.5 - 0.6mm

Pad0.9 - 1.0mm

Via0.2 - 0.3mm

Pad0.4 - 0.5mm

200µm100µm

100µm50µm


Tolerance 50 µmTolerance 100 µm

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Second example:The "pressing of multilayer boards". The tolerance is ± 10 % of thetotal thickness and does not determine how these 10 % are to bedistributed on the laminates and prepregs. According to this defini-tion, a multilayer board with an intended thickness of 1.5 mm willbe o.k, if the final thickness is in the range between 1.35 and 1.65.This may be accepted from the mechanical point of view, but therewill be considerable restrictions, if impedances are taken into ac-count because the optimum operation range is exceeded from athickness tolerance of 7 % on.Therefore, the pressing tolerance must not exceed ± 7%.

Filing systems The technical discussions being in the centre of attention usuallyconceal the requirement regarding strict, reliable, reproducable fil-ing systems in the background.

The PCB may NOT follow its way, if the data storage, the documen-tation, the design-rules, the operating instructions, the file-logisticsor the multilayer board construction instructions are incorrect.Without any systems, the necessary arrangement and coordina-tion cannot be successful neither between customer and manufac-turer nor within the production process.

Many manufacturers have an archive of 20,000 jobs with approx.400,000 individual data sets. Each data access has therefore to beunequivocal. There are different possible solutions to create a filesystem to meet this requirement (figure 13).

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Figure 13: File syntax for CAM / data processing archives

In case of multilayer boards, the freedom to combine the materialin nearly any desired stack-up has caused a variety of constructiontypes for the design (figure 14). There is no clear registration ofthese construction types, there are no official rules and hardly pub-lished catalogues. The PCB manufactures are mostly surprised bythe speed of this development. However, it is mainly their job to in-form their clients about possibilities and impossibilities regardingthe individual case.

ILF5D044.MBFile name . Extension

ILF5D044.MBILF5D044.I2

Both files belong to the same layout(solder mask and inner layer).

WIE6B124.LSABC4H069.LS

The files belong to different layouts, however, they both describe the conductive pattern for the solder side

Extension Contents Format

ABVBDBMB, MBNBS, BSNI2, I2NI3, I3NI4, I4NI5, I5NI6, I6NI7, I7NI8, I8NI9, I9NLS, LSNML, MLNDLVLALZ1/Z2UMZZMDRI/NDK

Peelable sold. resist comp. sideVia filling mask comp. sideSilkscreen comp. sideSolder mask comp. sideConductive pattern comp. sideConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern inner layerConductive pattern solder sideSolder mask solder sideSilkscreen solder sideVia filling mask solder sidePeelable sold. resist solder sideDrilling programmeOutline planDimensioned outline planDrilling programme

Gerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mmGerber 3.2mm

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Figure 14: Example of a multilayer stack-up

Conclusion No. 1 If you have been involved with PCBs for years and if you have wit-nessed its technological evolution, you are fascinated if you lookback.

Once called simple and being very unpopular as an additional costfactor within the calculation system of an assembly, the PCB hasmade its way.

It does practically not exist anymore as a pure component carrier.The PCB itself became a component of complex electronics a longtime ago and its technical features cannot be exchanged at will anylonger. The PCB requires and deserves our attention, our sympa-thy, our understanding and, last but not least, our respect.

Multilayer stack-up plan

Pressed 1.18 - 1.33 mm Final thickness Tin lead 1.26 - 1.42 mm (incl. solder mask) Hot-air 1.29 - 1.45 mm Gold 1.25 - 1.41 mm

mm Material File Mounting(0.050 HFPrepreg type : 106)(0.060 Prepreg type : 1080)(0.100 Prepreg type : 2125)

A1

A2

B

0.017 Copper *.BS

0.017 Copper *.LS

0.050 FR4

A3

0.060 Prepreg

0.100 Prepreg

0.050 HFPrepreg0.017 Copper *.I4(N)

0.250 FR4

0.017 Copper *.I5(N)



0.100 Prepreg

0.060 Prepreg

0.250 FR4

0.100 Prepreg

0.060 Prepreg



Multilayer construction type 8M13FR4I5I25K17K35

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If you nowadays design an electronic circuit without showing thisrespect towards the PCB, you will act with negligence or, in anycase, not very clever.

You will ignore the possibilities resulting due to the numerous vari-eties of the materials, surface-finishes, conductive pattern structur-ings and of the connecting alternatives.

The miniaturization with tracks and vias to 100, 80 or even 50 µmregularly produces speculations: What will come next? - 20 µm? 10or even 5 µm?

Maybe!I do not guess so.

The PCB is not the missing link to the hybrid circuit or to the micro-chip of the 70s. It will always do what has marked its character: tokeep together autonomous components as a whole and to createconnections.

This will also be the case, when its status as a mechanical-electronicprecision component is generally accepted by everyone. This willprobably be the last milestone of its evolution.

Afterwards, different things will come with different names.

The question regarding "the future of the PCB" has therefore foundseveral answers.

However, there are obviously still two further questions to be an-swered.

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The first question is:

What is the future of the PCB manufacturer?

The PCB manufacturers do not welcome the present technologicaldevelopment with arms wide open. The lean years seem to be overbut even the best enterprises did not escape unscathed. The de-mand of the market for variety, quality and short deadlines creates anincredible pressure.

Some manufacturers still guess, others already know: To be in theposition to offer all variants of the new PCB, investments will haveto be made which seem completely absurd regarding the (almost)empty tills and the moderate profits. It is not only necessary to re-place existing, old machines against new ones which do the same,of course better, quicker and less expensive (figure 15).

This cycle is not new and the PCB manufacturers are quite used tothis process.Now it is also necessary to invest in machines which have not beenused and which will become necessary IN ADDITION to the othermachinery.

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Figure 15: Machines and investments

A simple example is the contour treatment. It is common to millcontours. Now, the scoring of contours is also a variant. The scor-ing maching, however, may not replace the milling machine which,some years ago, replaced the parallel shears. Now, a scoring ma-chine AND a milling machine is necessary. Only then, the custom-ers demand for a combined scoring-milling assembly panel can besatisfied.

Second example: A pin tester is required for the electronic test.But, IN ADDITION; a flying-probe tester is necessary in case of mi-crofine-line PCBs.These examples depend on the investment capacity of an enter-prise.

Production technology

to be used for


Super-microfine-

lineCNC without Z-axis control yes Partially noCNC with Z-axis control yes yes yes

X-ray drilling machine yes yes yes

Film exposure yes Partially noGlass master exposure yes yes PartiallyLaser direct imaging yes yes yes

Clean-room technology yes yes yes

AOI-tester yes yes yes

Standard multilayer press yes Partially noProcess-controlled multilayer press yes yes yes

Standard electroplating yes Partially noProcess-controlled electroplating yes yes yes

Etching (alkaline) yes Partially PartiallyEtching (acid) yes yes yes

Solder mask (screen printing) yes Partially noSolder mask (film/foil) yes yes yes

Pin adapter, resolution 1/10" yes no noPin adapter, resolution 1/20" yes Partially noElectronic test (translator/probe) yes yes yes

Machines and technology for super-microfine-lines

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The requirements on the galvanotechnical surface-finish variantsare totally different. Galvanic baths are very susceptible to rest pe-riods. They cannot be activated or deactivated within a longer pe-riod of time to quickly carry out a gilding or a tinning. If these bathsare only rarely used, their balance will be upset. They cannot beused any longer and economical deficits will be the consequence.

If the PCB manufacturer intends to follow the way of the product,there will be only one alternative: Cooperation!

This is very hard for an industry which was able to produce inde-pentently for decades and which procured base materials but nev-er needed considerable industrial services. But that is not all: Manyservices cannot be obtained neutrally but only by a competitor whowas a fierce rival in the fight for customers not long ago. Theseservice enterprises must now be logistically integrated in the inter-nal organization. Many company policies will therefore be turnedupside down.

Other companies take another appropriate measure as a result ofthese changes and start to specialize. They either produce onlysingle-sided or double-sided PCBs, or only multilayer boards oronly 6 or 8-layer board or only rigid-flexible circuits or only up to anumber of 100 pieces or from 100 pieces on.

This is very economical because the machines are used in the bestpossible way.It is obvious that a specialist for single-sided PCBs is always less ex-pensive than a company which also produces multilayer boardswhich require a perfect plating, measuring places and laser directimaging systems which have to be sufficiently used and correctlymaintained and serviced.

Parallel to the investment and specialization concerning machines,the most urgent problem ist the training and further education of thepersonnel. The technical sequences change, it would be fatal, if thestaff did not. The requirements on the CAM data processing are con-siderable. They cannot be fulfilled, if there are no instructions basedon generally accepted and respected design-rules.

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Conclusion No. 2 Gently but firmly, the PCB takes along on its way its own manufac-turers and designers. Its sensitivity, differentiation and variety istransferred to the people who have to deal with it and to the enter-prises which are connected to it.

The necessity to cooperate, however, offers the chance of a newenterprise culture. The PCB manufacture changes from a productto a project which can be only carried out successfully, if it is basedon a partnership.

No, it would definitely not be easier; neither for the PCB manufac-turer, nor for the customers. The current calculations DM*dm2 arenow invalid. This kind of specification is too superficial.

Even the wish that PCB types, if single or double-sided, in anyquantities, if protoype or series, are available from one manufac-turer cannot be fulfilled any longer on a long term basis. The nec-essary specialization will not allow this anymore.

In many fields, the specialization itself will require new coopera-tions. The series manufacturer has to find an arrangement with theprototype manufacturer because it is appropriate to have the pro-totype data as a basis as these data have been tried and tested inthe pre-production. Therefore, a data exchange is necessary. Thisrequires though a clear coordination during the formal transfer andan agreement regarding common design-rules and a commondata format.(I will not comment the subject "common data format". Everyoneknows that I prefer the "Gerber" format.)

Of course, the PCB will become more expensive. The investmentsin expensive machinery which can not be fully used because thereare too many product variants hardly leave no other choice.

However, there will also be no reduced delivery times. The timesaved by technology and rationalization get lost on the way to andfrom the external service companies.

Regarding these aspects, that's all for the PCB and the manufac-turers. However, one authority is still missing.

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The second addtional question:

"What is the future of the CAD layout designer?"

The conflict exists. On its way, the PCB has taken along the lay-outer more than he/she is actually aware of.

Basic decisions, for which there are partially or completely no cur-rent experience values, must be made with every new layout.The combination between mechanics, electronics, EMC, functionand costs will be so individual that the original task, the layout, willalmost be inferior.

The most important support is surprisingly the component manu-facturer. They have ensured the constant reduction of the pin dis-tances for the last years. However, the escape to MCMs and COBindicates that the development of the mechanical adaptation hascome to an end. The bonding of chips on carriers makes the limitsobvious. The opposite force of the possible measures are the ap-propriate measures.

Regarding the layout, the problems are concentrated on the selec-tion of the correct material appropriate for the surface-finish, appro-priate for the track-width, appropriate for the vias and appropriatefor the multilayer construction type. The freedom of the layouter isdetermined by the function, on the one hand, and by the costs ofthe assembly, on the other hand.

The layouter will not be in the position to decide independently. Thedecisions will depend as well more than ever on the constructivecooperation with the PCB manufacturer and with the assembly pro-ducer and on the internal organization.

The layouter will be in charge of the classification of layouts and ofthe precise technical specification of the PCB.

The layouter has to adopt the sensitivity of the functional compo-nent "PCB".

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Conclusion No. 3 Paradoxically, the layouter is restricted by the variety of options.

There is finally the material with the correct εr-value, but it cannotbe used because it is too expensive.

There is eventually enough space due to signal lines of 150 µm.But there is also a power supply on the same layer always placedon 70 µm of copper, which now cannot exceed 17 µm.

Now, the optimal multilayer stack-up is available for the layouterwith 50 µm-laminates, which offers an excellent broadband decou-pling, however, just his/her supplier is (still) not able to processthese laminates.

More?

Multilayer boards out of favourable CEM material? It does not work because it is a compound laminate.

Bondpads which are tested by the manufacturer by means of pinadapters? It does not work because the surface-finish of the pads will be dam-aged by the adaption.

Tracks with widths of 100 µm in 35 µm copper? It does not work because it cannot be etched.

A 10-layer board, 1.8 mm thick with through-vias of 0.1 mm?It does not work because it cannot be reliably plated.

Then, is there at least some help, a training, further education?

This is also not possible, there is none.

But that is a completely different story.

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Final word The way the PCB, its manufacturers and its designers will have togo, will be paved with all technical extras. Many of them are neces-sary, progressive and rightly successful.

However, the question "how many varieties are actually neces-sary?", is legitimate.

It must be possible to discuss if the faith in an increasing technicalcomplication as the best solution, will sometimes unnoticed turninto a superstition.

Therefore, the miniaturization of the components is generally indi-cated as the cause for the miniaturization of the vias and of theconductive patterns.

That is not completely true!

Decisive is, how the connections between the individual compo-nents are made. This task is often completely left to the autoroutersof the CAD system.

The machines are certainly quicker than we are, but, I do not be-lieve that they are more intelligent.

It is absolutely important to talk about technolgy.

However, do not let us completely ignore the strategies, the ideasand the creativity which - also - distinguishes us as human beings.

WgdL23.08.1999

ilfa-the future of the pcb

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