ime_design rules for silicon photonics prototyping v1_2008(1)

7/29/2019 IME_design Rules for Silicon Photonics Prototyping V1_2008(1)

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Property of Institute of Microelectronics. Copyright 2008

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Design Rules for Silicon PhotonicsPrototyping

Version 1 (released February 2008)

Introduction

IMEs Photonics Prototyping Serviceoffers 248nmlithography based fabrication technology for

passive Silicon-on-insulator photonic circuits at a cost affordable to research groups andcompanies.

This document briefly describes:1) Key fabrication process of this technology,2) Guidelines for the design and fabrication of passive Silicon-on-insulator photonic circuits

through this technology,3) Design rules for the mask files.

Technology Key Aspects

200 mm Silicon-on-Insulator wafer: typically,220nm top silicon, 2000nm buried oxide 248nm deep UV lithography Typical/minimum pitch [nm]: 450 / 400 (binary mask) Typical/minimum line width [nm]: 220 / 170 (binary mask)

(Phase Shift Mask is optional for structures with feature size smaller than above spec., Pleasecontact coordinator for detailed information.)

Use of Tip couplers

Coordinator Contact

Patrick Lo Guo QiangInstitute of Microelectronics, Singapore

[email protected]: +65-6770-5705


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Contents

1. Description of Key Fabrication Process

1.1 Fabrication Process flow 31.2 Wafer Specification 31.3 Lithography 31.4 Etching 41.5 Mask Technology 41.6 Facilitating Measurements 4

2. Design Rules

2.1 Minimum Feature Sizes 52.2 Multiple Structure Design 52.3 Multiple Circuit Design 62.4 Appendix: Exposure Latitude for Some Critical Structures 6

Photonic Crystal Holes 6Isolated Lines (photonic wires) 7

Gap Width 8Tip Coupler Design 8

3. Mask File

3.1 Mask File Format 93.2 Hierarchy 93.3 Software 93.4 Dark Field/ Light Field 103.5 Layer Structure 103.6 General Layout Rule 11


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1. Description of Key Fabrication Process

1.1 Fabrication Process Flow

The standard fabrication process flow IME uses for photonic passive device andcomponents are schematically shown as below (here 248nm lithography is used):

(a) Bare Si-substrate wafer-- Si-substrate

-- Buried SiO2 (2 m)-- Top Si Layer (220nm)

(b) Bottom AR coating (BARC)(c) Photo-resist (PR) coating and soft bake(d) Exposure(e) Post-exposure bake

(f) Development

(g) BARC & Silicon etch

(h) Photo-resist strip & clean

(i) Si-surface Treatment

1.2 Wafer Specification

The wafers are Silicon on Insulator (SOI), typically with 220nm top silicon layer and2000nm buried oxide.

1.3 Lithography

The standard lithography process used for nanophotonic structures makes use of 410 nmthick Shipley UV210 resist with a bottom antireflective coating; exposed with illuminationconditions of numerical aperture of 0.68 and a spatial coherency factor of 0.31.

Si

SiO2

Si

Si

SiO2

Si

Si

SiO2

Si

Si

SiO2

Si

PRBarc

PRBarc

Si

SiO2

Si

PRBarc

Si

SiO2

Si

Si

SiO2

Si


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1.4 Etching

ICP low pressure/high density etch system with a chemistry based on SF6 /C4F8 /O2 is usedto etch only the top Silicon layer.

Prior to hardmask and Si etching, BARC etch is performed using plasma etching that alsosmoothen the sidewall of resist to reduce roughness (refer to process flow). BARC etch canalso be used to compensate for a feature size bias between litho and etch.

1.5 Mask Technology

The mask will be a binary Chrome Mask (without Phase Shifting features). The defaultpolarity of the masks are dark-field, which means that all features defined on the mask willbe transparent and therefore etched away (refer to 3.4 Dark Field/ Light Field for details).

The mask will have a useful area roughly 10 x 13.2 cm2, with a reduction factor of4 .

Mask shop will be appointed by IME.

(For users who require Phase Shift Mask for special design, please contact coordinator for moreinformation.)

1.6 Facilitating Measurements

IME provides deep trench etch process using deep reactive ion etch (DRIE) to facilitateoptical measurements, without additional effort of polishing after wafer dicing.

IME also provides wafer dicing and packaging services.

Please contact the technical coordinator for more information:

Patrick Lo Guo QiangInstitute of Microelectronics, [email protected]: +65-6770-5705


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2. Design Rules

2.1 Minimum Feature SizesThe minimum feature size that can be fabricated depends on the type of structure needed(i.e., dependent on pattern density, shapes etc). To provide some guidelines for design,the following table lists some of the minimum feature sizes that can be fabricated within aperiodic pattern. For users with more complex design requirements, kindly contact thetechnical coordinator for more information.

Periodic structure Feature Minimum Size Typical SizePitch > 400nm > 450nmLines Width > 170nm > 220nmLine spacing > 180nm > 220nmTriangular Holes Diameter > 190nm > 220nmTriangular Holes Spacing > 200nm > 240nm

For feature sizes smaller than the above listed specifications, resolution enhancement by useof Phase Shift Masking may be used. Kindly contact the coordinator for more information.

2.2 Multiple Structure Design

Fabricated feature size varies as a function of exposure dose, which is typically expressedin mJ/cm2; quantifying the amount of light projected onto the photo-resist. E.g. holes willbecome larger for a higher exposure dose, while lines will become smaller. The dose usedto fabricate structures at the desired size is called best exposure dose. However, in

general, structures of different types (holes vs. lines) and even structures of the same typewith different feature/pitch size will have different best exposure dose. Therefore, oneshould take special care when incorporating structures of different types (e.g. photonicwires and photonic crystals) on a single mask design.

Usually a sweep of the exposure dose is performed to estimate the best exposure dose ofthe most critical structure(s). The results are summarized in the Figures of2.4 Appendix.Some mask design bias may be designed based on the data provided in these figures.The following example illustrates a possible mask design bias:

Example 1: when incorporating a photonic crystal structure with triangular holes of diameter350nm and pitch of 500nm, together with an isolated line (photonic wire) of 500nm width ona single mask design, best exposure dose for holes is 40 mJ/cm2 (see Figure 1 in 2.4

Appendix). However, at this dose, the isolated line will print at 410nm width instead of theintended 500nm width, giving off-target results (see Figure 3 in 2.4 Appendix).

While it is most recommended that there should be only one critical structure on each layer,i.e. for instance in example 1, either the hole size of the photonic crystal structure or thewidth of the coupling wire should be critical; a work-around solution to get both features toprint on-target in this case would be to adjust one or more structures size in order that theyprint correctly at the same exposure dose. That is, in this case, the layout of the isolatedline on the mask can be increased to 580nm (to give the necessary 80nm design bias), sothat both photonic crystal structures and isolated line (photonic wire) can print correctly atthe same exposure of 40 mJ/cm2.


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In conclusion for this example, it should be noted that while such straight forward designbias works well for simple structures, more complicated designs require more advance

compensation techniques such as placement of scattering bars etc for design of maskbiases. For such jobs, kindly contact the coordinator for more information.

2.3 Multiple Circuit Design

When incorporating multiple circuits with different best exposure dose, one can have allcircuits on the same wafer, but on different dies if the various best exposure dose, are nottoo widely spread. Otherwise, different circuits will be fabricated on more than one wafer.

2.4 AppendixPhotonic Crystal Holes

Figure 1 shows the measured diameter of holes patterned in a triangular hole array (onwafer) as a function of lithographic exposure dose for a variety of pitch and diameter (onmask).

20 30 40 50 60 70 80901000

100

200

300

400

500

600

Triangular hole diameter vs Exposure dose

Design diameter:pitch [nm]

350:450

240:400

270:450300:500

350:500

MeasuredHoleDiame

ter[nm]

Exposure Dose [mJ/cm

2

]

Figure 1


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Figure 2 shows the measured diameter of holes patterned in square lattice array (on wafer)as a function of lithographic exposure dose for a variety of pitch and diameter (on mask).

Isolated Lines (Photonic Wires)

Figure 3 shows the measured line width (on wafer) as a function of lithographic exposuredose for a variety of designed line widths (on mask)

20 30 40 50 60 70 80901000

100

200

300

400

500

Square hole diameter vs exposure dose

Design diameter:pitch [nm]

200:400

226:450

MeasuredHoleDiameter[nm]

Exposure Dose [mJ/cm2]

250:500

20 30 40 50 600

100

200

300

400

500

600

700

800

Isolated line width vs exposure dose

design iso-line width [nm]

700

600

500

400

300200Measuredline

width[nm]

Exposure dose [mJ/cm2]

Figure 3

Figure 2


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Gap WidthFigure 4 shows the measured gap spacing (on wafer) between two lines with width of 0.3

m as a function of lithographic exposure dose for a variety of designed gap widths (onmask)..

Tip Coupler

For tip coupler, the following figure shows an example:

a = 180 nmb = 200 m

bb

Si wave uide

20 30 40 50 60 70 80 90

0

100

200

300

400

500

600

700

800

900

Gap width vs exposure dose

design gap width [nm]

600 nm550 nm

500 nm450 nm400 nm

300 nm350 nm

200 nm250 nm

MeasuredGapWidth

[nm]

Exposure Dose [mJ/cm2]

a

Figure 4


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3. Mask Files

3.1 File Format

For submission of design layout to IME, the file format to be used should be GDSII. As notall software tools support the full GDSII command set, users should limit structuredefinitions to the following types:

i. BOUNDARYFilled, closed polygons; with a maximum of 200 nodes.

ii. PATHOpen lines with a physical width.

iii. Simple Reference (SREF)Singular reference to a previously defined structure. Transformations on references areallowed as long as the rotation angle is a multiple of 90.

iv. Array Reference (AREF)An array of references to a previously defined structure. Transformations on references areallowed as long as the rotation angle is a multiple of 90.

Here, it is to be noted that the use of BOUNDARY type structures are preferred to PATHtype in order to avoid arbitrary grid snapping in PATH type boundaries. Also, the followingstructure types are NOT supported:

i. NODESuch elements are ignored and will not be fabricated on the mask.

ii. LABELSuch elements are also ignored and will not appear on the mask.

3.2 Hierarchy

The layout should make full use of the GDSII hierarchy scheme such that SREFs andAREFs are used to define repeating structures where possible so as to keep final layout filesize acceptably low. For instance, where a periodic photonic crystal lattice is required, itshould not be composed of copying thousands of individual polygons, but rather createdthrough instances call up of SREFs or AREFs.

The final layout should comprise of only a single top cell in which the other sub-cells ofSREFs and AREFs lower on the hierarchy are referenced.

3.3 Software

GDSII layouts may be created on most layout tools such as Cadence, Silvaco Expert, L-editetc. For partners without such software, layout can be created by IME in-house at a fee.Alternatively, free layout software such as Ruby GDSII Library may be used for writingGDSII data in the Ruby programming language (http://en.wikipedia.org/wiki/Ruby). As thisis a third-party software, its correctness and usage is solely the decision of the user, forwhich IME cannot be responsible for.

For viewing of GDSII files without data manipulation, the free software CleWinmay be used(http://www.phoenixbv.com ).


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3.4 Dark Field/ Light Field

For ease of definition, the default polarity of the masks are in dark field, so that structuresdefined in the layout mask files become transparent on a chrome background, and areetched away after processing. On the other hand, to accommodate layers whereby it ismuch simpler to define the structures as portions that should not be etched away (forexample in waveguides layers for lines features), light field layer definition may be usedinstead of laying out two trenches to define the line.

For layers whereby there are to be both lightand dark fieldfeatures, the different fields areto be laid out on separate GDSII layer numbers so as to enable subsequent logic operationprocessing as shown in the next section. In general, it is highly recommended that eachlayer consist of a single field type (i.e., eitherlightordark field).

3.5 Layer Structure

To facilitate the processing of mask data and also the application of proximity corrections formask data optimization. A table of the different categories for structure types is listed asfollows for layout drawing layer assignment:

LayerNumber

Layer Type StructureCriticalDimension (CD)

Examples

1 to 5 Non criticalLines, trenches,

polygons etc 1 m

Alignment marks, text,logos, fiber grooves etc

6 to 10 TypicalLines, trenches,

polygons etc250 nm CD < 1 m

Broad lines, ridges,polygons etc

11 to 15Lines

170 nm CD < 250 nm Photonic wires, tapers

16 to 20Trenches

180 nm CD < 250 nm Gaps

21 to 25

Critical

Holes, pillars, polygonwidest dimension

190 nm CD < 250 nm Photonic crystal lattice

26 to 30Lines

100 nm CD < 150 nm Waveguides, gratings

31 to 35Trenches

140 nm CD < 190 nm Gratings, gaps

36 to 40

Alternatingphase shifted

Holes Only160 nm CD < 200 nm Photonic crystal

Here, the density of the patterns should also be specified, as a function of pitch, whichshould not be less than 400nm unless they are of the alternating phase shifted type, which

has minimum pitch of 280nm for line space patterns and 300nm for hole-type feature.

Also, for layers with more than one type of structure, the categorisation of layers isdetermined by the smallest feature on that mask. For example, for a mask having bothphotonic crystal structures (with CD of 250nm), together with broad line waveguides, themask is assigned a layer number ranging from 21 to 25 for data processing.

On a final note, further to the description for combining of clear and dark feature on a samemask. The following Figure 5 schematically explains the logical OR operation of a darkfield (photonic crystal layer X) with a clear field (waveguide layer Y) layout for final layoutpatterned structure as given in schematic Z.


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Figure 5: Schematic of logical operation involving combination of both dark and clear fieldOn a same mask layer.

3.6 General Layout Rules for Basis Cells

For mask fabrication at IME, all layout contributions will be fitted onto a basis cellsize of

either 25 32 mm2 or 25 16 mm2. This is to allow for standardised processing flow andoptimised utilisation of mask area. For every mask layer which requires subsequentalignment and process quantification, clear-out areas without interference from other

patterns need to be reserved for both alignment and metrology structures. In general, Nsuch layers would require layout area of N 2500 100 m2 horizontally and N 2100

100 m2 vertically. Further, for every two layers with overlay requirement, clear-out area of

150 80 m2 need to be reserved at each corner of the basis cell.

Dark field -Photonic

crystal drawnas squares

To obtain thisfinal patterned

structure

Clear field -Waveguides

drawn as lines

Etched

pattern

on wafer

Layout

layer

Y

Layout

layer

X

White area =

resist cleared

OR

ime_design rules for silicon photonics prototyping v1_2008(1)

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