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Background: York Minster roof, from http://www.photoeverywhere.co.uk Immunity of FPGA Chips by Direct Injection Tobias Aurand, John F Dawson, Martin P Robinson, Andrew C Marvin, Department of Electronics, University of York, UK Signal generator Directional coupler 2 channel Power meter IC under test mounted on test PCB FPGA physical layout P40 P59 FPGA functional layout 1 2 3 5 4 RF injection 6.8nF P40 P59 From: Spartan-3L Low Power FPGA Family,Product Specification DS313, Xilinx, 2008 The experimental set-up for direct injection immunity tests. In some cases a power amplifier is inserted after the signal generator. The direct injection circuit board for the Xilinx Spartan-3 FPGA. The FPGA has core logic blocks interfaced to the outside world via IO blocks Due to space limitations we put test pads on alternate pins and had to skip over some ground and power pins. Initially interference was injected on to pin 59 only with the terminations on nearby pins varied Here you can see the Immunity of P59 with adjacent pins open (internal pull-down). With purely resistive loads the changes in immunity are much smaller Comparing different capacitive and resistive loads on pad 2 The Immunity of P59 changes as a 100pF capacitive load is placed on nearby pins. The input impedance of P59 changes due to the load on adjacent pins

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Page 1: Immunity of FPGA Chips by Direct Injection

Background: York Minster roof, from http://www.photoeverywhere.co.uk

Immunity of FPGA Chips by Direct InjectionTobias Aurand, John F Dawson, Martin P Robinson, Andrew C Marvin, Department of Electronics, University of York, UK

Signalgenerator

Directional coupler

2 channelPower meter

IC under test mounted

on test PCB

FPGA

physical layout

P40 P59

FPGA

functional layout

1235 4

RF injection

6.8nF

P40 P59

From: Spartan-3L Low Power FPGA Family,Product Specification DS313, Xilinx, 2008

The experimental set-up for direct injection immunity tests.In some cases a power amplifier is inserted after the signal generator.

The direct injection circuit board for the Xilinx Spartan-3 FPGA.

The FPGA has core logic blocks interfaced to the outside world via IO blocks

Due to space limitations we put test pads on alternate pins and had to skip over some ground and power pins. Initially interference was injected on to pin 59 only with the

terminations on nearby pins varied

Here you can see the Immunity of P59 with adjacent pins open

(internal pull-down).

With purely resistive loads the changes in immunity are much smaller

Comparing different capacitive and resistive loads on pad 2

The Immunity of P59 changes as a 100pF capacitive load is placed on nearby pins.The input impedance of P59 changes due to the load on adjacent pins

Page 2: Immunity of FPGA Chips by Direct Injection

Background: York Minster roof, from http://www.photoeverywhere.co.uk

FPGA

physical layout

P59

P57

P5

5

P53

P5

1

2.5 V

Pads for 0603 SMD components

Tracks leading to SMD connectors for injection

Altera - FPGA

physical layout

P81

P79

P77

P75

P73

VC

CIO

P83

P85

P87

Sup

ply

GN

D

VC

CIN

T

Clo

ck in

put

From: Cyclone III low-cost FPGAs, Altera, 2007

Effect of pcb track and connector at pin 40 on pin 59. Power and ground pins

between seem to isolate any interaction.

The immunity levels of pins 40 and 59 are comparable but not exactly equal. The

measurement is repeatable

A capacitor on pad 4 has little effect on the pin 40 immunity. Ground and power pins between pin 40 and the capacitor

seem to provide isolation.

We built a test board with alternate pins grounded to see if the ground

connections would isolate interactions.

Investigating the coupling between pins shows strong coupling between pins, this

appears to be an on-chip effect.

We decided to look at another similar device to see if the same effects were observable.

The Altera Cyclone-3 family has a similar architecture to the Xilinx device

The Altera FPGA was connected with alternate pins grounded as with the 2nd

Xilinx design.

With the Altera FPGA we observed a larger pin-to-pin variation in immunity

The effect of termination of nearby pins on the immunity of pin 75 was found to be significant even with alternate pins

grounded

The effect of termination of nearby pins on the input impedance of pin 75 was

found to be significant even with alternate pins grounded

The effect of capacitive loads on nearby pins is reduced by grounding alternate pins.


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