impact of doping concentration gradient and spacer thickness on device performance of utb-soi cmos
DESCRIPTION
Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS. Hannes Luyken CPR ND. Session 1.1: Transistor architecture and fabrication. - PowerPoint PPT PresentationTRANSCRIPT
Page 1
Hannes LuykenCPR ND
N e v e r s t o p t h i n k i n g .
UL
IS 2
003
Ult
imat
e In
teg
rati
on
of
Sili
con
T. Schulz, C. Pacha, R. J. Luyken, M. Städele, J. Hartwich, L. Dreeskornfeld, E. Landgraf, J. Kretz, W. Rösner, M. Specht, F. Hofmann and L. Risch
Infineon Technologies AG,
Corporate Research Nano Devices,
Otto-Hahn-Ring 6,
D-81730 Munich, Germany
Session 1.1: Transistor architecture and fabrication
Impact of Doping Concentration Gradient and Spacer Thickness on Device Performance of UTB-SOI CMOS
Page 2
Motivation for the ultra thin body (UTB)-SOI device concept
Simulation method
Impact of technology parameters on device performance
- source/drain doping concentration gradient
- sidewall spacer thickness
- silicon thickness
- supply voltages
Conclusions
Outline
Page 3
Motivation for the ultra thin body (UTB)-SOI device concept with undoped channel region
Gate
Bulk
Source Drain
Gate
Source Drain
SOI
buried oxide
elev. elev.
V (V)DS
I (mA/ m)D
0.30.0 0.6 0.9 1.2
0.0
0.4
0.8
1.2
1.4
V =0.9VGS
ION
SOI
bulk
0.2
0.6
1.0
L = 50nmt = 1.1nmN = / cm
= / eV
G
OX
A
MS
-3
1E184.17
1E14 4.41
+60%
Undoped channel region Increase in drive current
New gate materials Vth adjustment
Page 4
green area:
interconnects and wiring and geometrical aspects of gates
blue area:
intrinsic device and substrate material
red area:
coupled device and circuit simulation
Simulation method
Page 5
Device structure and technological parameters
Gate
LG
Source Drain
Silicon Substrate
Buried Oxide
tSicut
0x [nm]
25 50 75 100 125 150
UndopedBody
L spL sp
tbox
UTB-SOI device parameters
Param eter Value
G ate length L [nm ] 50Spacer length L [nm ] variab leFront-oxide th ickness t [nm ] 1 .1S i-body th ickness t [nm ] 5 and 10Buried-oxide th ickness t [nm ] 100Body doping N [cm ] 10Source/dra in doping N [cm ] 10 D oping
G
sp
O X
Si
BO X
b
SD
-3 14
-3 21
(arsen, boron)
conc. grad ient [nm /dec] variab le
No additional source/drain series resistances were chosen
NMOS and PMOS have the same structure apart from the different doping sequence
Page 6
Simulation scheme and circuit structure
2 Inverter
4 MOSFETs
(n1, p1, n2, p2)
Additional R and C
RC-load
C-wiring
Input pulse (1ps)
Delay between
VOUT_1 and VOUT_2
Page 7
Transient and transfer characteristic
I/O
vo
lta
ge
V [
V]
I/O
time [ps]0
VOUT_1V IN V OUT_2
0.20.4
0.60.8
1.0
440 450 460 470 480
tD
input pulsedelay: 1ps
t =0.5(t +t )D D DO
utp
ut
vo
lta
ge
V [
V]
O
0
0.2
0.4
0.6
0.8
0.40.20 0.6 0.8Input voltage V [V]I
W /W =2.46p n
V OUT_1 V OUT_2
Page 8
Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
34
5
7
10
Gate
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[c
m]
-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
Spacer[nm]
As
B
N b
N (x)SD
15
25
10
30
Gate
20
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
3 457
10
Gate
Spacer
Page 9
Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer
Where is the effective / metallurgical channel length ?
Leff as figure of merit vanish
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
34
5
7
10
Gate
Page 10
Impact of technology parameters on inverter delay - source/drain doping gradient @ constant spacer
Where is the effective / metallurgical channel length ?
Leff as figure of merit vanish
Is a relaxed doping gradient of 10 nm / decade sufficient ?
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
34
5
7
10
Gate
0X [nm/decade]
2 4 6 8 10 12In
vert
er d
elay
[p
s]
12
9
8
7
6
5
43
2
1
0
10
11
t = 5nmSi
t = 10nmSi
Spacer 10nm
Page 11
Steep doping profiles suppress short channel effects
LSTP
LOP
HP
I [
A/µ
m]
OF
F
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
X [nm/decade]2 4 6 8 10 120
10 -12
Spacer 10nm
IOFF and ION versus doping gradient @ constant spacer
Page 12
Steep doping profiles suppress short channel effects
Shallow doping profiles flood the channel with dopants
In most cases spacer thickness of 10nm is too thin
LSTP
LOP
HP
I [
A/µ
m]
OF
F
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
X [nm/decade]2 4 6 8 10 120
10 -12
Spacer 10nm
HP
LSTPLOP
I [
µA
/µm
]O
N
1.0V
0.9V
0.8V
X [nm/decade]2 4 6 8 10 12
2800
2400
2000
1600
1200
800
400
00
Spacer 10nm
IOFF and ION versus doping gradient @ constant spacer
Page 13
Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
34
5
7
10
Gate
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[c
m]
-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
Spacer[nm]
As
B
N b
N (x)SD
15
25
10
30
Gate
20
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
3 457
10
Gate
Spacer
Page 14
Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient
What is the optimal spacer thickness ?
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
Spacer[nm]
As
B
N b
N (x)SD
15
25
10
30
Gate
20
Page 15
Impact of technology parameters on inverter delay - sidewall spacer thickness @ constant gradient
What is the optimal spacer thickness ?
Thinner sidewall spacer increase short channel effects
Thicker sidewall spacer increase inverter delay
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
Spacer[nm]
As
B
N b
N (x)SD
15
25
10
30
Gate
20
5spacer thickness [nm]
10 15 20 25 30 35In
vert
er d
elay
[p
s]
12
9
8
7
6
5
43
2
1
0
10
11
t = 5nmSi
t = 10nmSi
5 nm/decade
Page 16
Thin spacer leakage current increase
5spacer thickness [nm]
10 15 20 25 30 35
I [
A/µ
m]
OF
F
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
10 -12
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
LSTP
LOP
HP
5 nm/decade
IOFF and ION vs. spacer thickness @ constant gradient
Page 17
Thin spacer leakage current increase
Thick spacer drive current decrease
Best case for L=50nm LOP device is 20-25nm spacer thickness
5spacer thickness [nm]
10 15 20 25 30 35
I [
A/µ
m]
OF
F
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
10 -12
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
LSTP
LOP
HP
5 nm/decade
LSTP
LOP
HP
5 nm/decade
I [
µA
/µm
]O
N
1400
1200
1000
800
600
400
200
0
1.0V
0.9V
0.8V
t =5nmSi
t =10nmSi
5spacer thickness [nm]
10 15 20 25 30 35
IOFF and ION vs. spacer thickness @ constant gradient
Page 18
Comparison with (bulk) roadmap trend:sidewall spacer thickness correlate with doping
gradient
State of the art: 50nm spacer thickness, 5nm/decade abruptness
2000year of production
2004 2008 2012 2016
Sid
ew
all
sp
ace
r th
ickn
ess
[n
m]
100
10
1
MAX
MIN
100
10
1
Ext
en
sio
n l
ater
al
abru
ptn
ess
[n
m/d
eca
de
]
Page 19
Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
34
5
7
10
Gate
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[c
m]
-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
Spacer[nm]
As
B
N b
N (x)SD
15
25
10
30
Gate
20
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm /decade
As
B
N b
N (x)SD
3 457
10
Gate
Spacer
Page 20
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
3 457
10
Gate
Spacer
Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient
Page 21
Compensation of spacer thickness and doping gradient
New figure of merit: doping concentration @ gate corner
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
3 457
10
Gate
Spacer
0X [nm/decade]
2 4 6 8 10 12In
vert
er d
elay
[p
s]
12
9
8
7
6
5
43
2
1
0
10
11
0.9V
1.0V
0.8V
t = 5nmSi
t = 10nmSi
Impact of technology parameters on inverter delay - combination of spacer thickness and doping gradient
Page 22
HP-device and LOP-device specs achievable
IOFF spec for the LSTP-device demand thicker spacer
LSTP
LOP
HP
I [
A/µ
m]
OF
F
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
X [nm/decade]2 4 6 8 10 120
10 -12
1E19cm @ gate-3
IOFF and ION versus different spacer / doping gradient
Page 23
HP-device and LOP-device specs achievable
IOFF spec for the LSTP-device demand thicker spacer
For the presented doping profiles 10 nm/decade is the better choice
LSTP
LOP
HP
I [
A/µ
m]
OF
F
1.0V0.9V0.8V
t =5nmSi
t =10nmSi
10 -02
10 -03
10 -04
10 -05
10 -06
10 -07
10 -08
10 -09
10 -10
10 -11
X [nm/decade]2 4 6 8 10 120
10 -12
1E19cm @ gate-3
LSTP
LOP
HP
1E19cm @ gate-3
I [
µA
/µm
]O
N
1.0V
0.9V
0.8V
1400
1200
1000
800
600
400
200
x [nm/dec]2 4 6 8 10 120
0
t =5nmSi
t =10nmSi
IOFF and ION versus different spacer / doping gradient
Page 24
Transfer and output characteristicsfor different spacer thickness and doping gradient
0-0.25-0.5 0.25 0.5 1.25 1.5
Gate Source Voltage V [V]GS
10 -15
10 -14
10 -13
10 -12
10 -10
10 -09
10 -08
10 -07
10 -06
10 -05
10 -04
10 -03
10 -02
Dra
in C
urr
ent
I [
A/µ
m]
D
0.75 1.0
0.9V
0.1V
V =DS
nm/decade
10
3
L=50nm=4.71eV
t =1.1nmN =1E14cmt =5nm
M
OX
A
Si
-3
Drain Source Voltage V [V]DS
Dra
in C
urr
ent
I [
µA
/µm
]D
0.750.50.250 1.0 1.25 1.5
1.0V
0.8V
0.9V
0
100
200
400
600
700
1000
300
500
800
900
nm/decade3 1010
3
VGS
Figure of merit: doping concentration 1E19cm-3 @ gate corner
Devices with different doping profiles but same driver performance
Increase of GIDL-current due to steeper doping concentration gradient
Page 25
Doping concentration gradient and spacer thickness can compensate each other as design parameter.
Source/Drain doping concentration at the gate corner is an accurate figure of merit instead of Leff.
With a steeper doping concentration gradient there is no influence on the driver performance but a significant off-current due to the increase of the GIDL-current occurs.
HP- and LOP-devices can meet the roadmap targets but LSTP-devices are much harder to implement.
Conclusions
Page 26
Back up
Page 27
Subthreshold and output characteristics
0-0.3-1.2 -0.6-0.9-1.5 0.3 0.6 0.9 1.2 1.5Gate Source Voltage V [V]GS
10 -15
10 -14
10 -13
10 -12
10 -10
10 -09
10 -08
10 -07
10 -06
10 -05
10 -04
10 -03
10 -02
Dra
in C
urr
ent
I [
A/µ
m]
D
3nm/decade
-0.9V
-0.1V
V =DS
0.9V
0.1V
V =DS
5nm/decade
V =GS
Drain Source Voltage V [V]DS
Dra
in C
urr
ent
I [
µA
/µm
]D
0-0.3-1.2 -0.6-0.9-1.5 0.3 0.6 0.9 1.2 1.5
1.2V
1.0V
0.8V
0.6V
0.4V0
200
400
600
800
1000
1200
1400
-1.2V
-1.0V
-0.8V
-0.6V-0.4V
L=50nm=4.71eV
t =1.1nmN =1E14cmt =5nm
M
OX
b
Si
-3
Page 28
Impact of sidewall spacer thickness in combination with doping gradient
figure of merit: doping concentration @ gate corner = 1E18cm-3
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
3 4 57
10
Gate
Spacer
Page 29
Impact of sidewall spacer thickness in combination with doping gradient
figure of merit: doping concentration @ gate corner = 1E18cm-3
compensation of spacer thickness and doping gradient depends also from the source / drain doping concentration level (here 1E20cm-3)
0X [nm/decade]
2 4 6 8 10 12In
vert
er d
elay
[p
s]
12
9
8
7
6
5
43
2
1
0
10
11
0.9V
1.0V
0.8V
t = 5nmSi
t = 10nmSi
0x [nm]
25 50 75 100 125 150
do
pin
g c
on
cen
trat
ion
[cm
]-3
10 22
10 21
10 20
10 19
10 18
10 17
10 16
10 15
10 14
10 13
10 12
~Xnm/decade
As
B
N b
N (x)SD
3 4 57
10
Gate
Spacer
Page 30
Silicon film thickness replace doping concentration as figure of merit
Bulk:
SOI:
DG:
depOX
OXAFFBth wt
qNVV0
2 A
FSidep Nqw
04
SiOX
OXAFFBth tt
qNVV0
2
22
0
Si
OX
OXAFFBth
ttqNVV
Page 31
nMOS Transistor
Fan-out 4 Inverter
circuit (clock period)
V SS
V DD
n
n
p
V OUT'V IN
4x Inv load
VOUT
intrinsic device (nMOS) 1FO4 stage delay 14=
FO4 stage delay 1clock period 16=
ITRS 2001:node 130nmgate 65nm
1.65 ps610 GHz
23.1 ps 43.6 GHz
369 ps 2.71 GHz
gate delay metric = C V I
Gate DD
D
Gate delay metric (ITRS 2001)
Page 32
device LSTPLOPHP
f [
GH
z]T
10000
1000
100
10
1
year1990 1995 2005 2010 2015 2020 1985
0.12000
1/14
1/16
FO4 Inv
system
Transit frequency (ITRS 2001)