implantation-dominated junction depths of low-temperature and electron-beam-annealed as...

445 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2, FEBRUARY 1987

Briefs

Implantation-Dominated Junction Depths of.Low- Temperature and Electron-Beam-Annealed As

Source-Drain Regions

G. A. J. AMARATUNGA, N. D. KNEE, M. J. HART, AND A. G . R. EVANS

Abstract-The deep penetration of implanted As is reported and its effect on source-drain regions in NMOS devices is examined. When annealing methods to minimize diffusion are used and the initial implant profiles are not modeled accurately to take into account deep penetration, the junction depths predicted by simulation will be shallower than those obtained in practice. This is verified by comparing experimental results with predicted profiles obtained from two process simulators that use different implantation models. It is shown that a Pearson IV distribution can accurately describe the as-implanted profile of As in Si. From measurements of implanted As profiles annealed using furnace and electron-beam methods, it is found that junction depths determined by implantation can be unchanged at low backgrounds, even after relatively high-temperature (lOOO°C) furnace anneals. As a consequence, low-temperature furnace or transient annealing does not yield the expected reduction in junction depth, while resulting in a significant increase in sheet resistivity.

I. INTRODUCTION To achieve small aevice dimensions for VLSI it is necessary to

lessen process times at high temperatures. This minimizes diffusion during the annealing of implanted regions such as source-drains in CMOS, for instance. For conventional furnace annealing of source- drain regions a reduction of process times to seconds is difficult, and lowering of temperature leads to higher sheet resistivities. Transient annealing techniques on the seconds or millisec- onds timescale allow the use of high temperatures with minimum diffusion. Under conditions of low-temperature furnace or transient annealing the profile and the junction depth of source-drain regions are to a large extent determined by the ion penetration that occurs during implantation, and to a lesser extent by dopant atom diffusion during annealing. Therefore accurate modeling of the implant profile must be carried out if junction depths are to be predicted. We have examined As source-drain implantations and show here that a Pearson IV-type statistical distribution [l] can be used to accurately model profiles obtained from the anneal conditions men- tioned above. The use of a distribution such as a Gaussian or jointed Gaussian can lead to significant errors in predicting junction depths. We also show that for furnace annealing of low-energy implants, at medium temperatures (lOOO"C), the choice of initial distribution i s not critical, as the resulting profile is to a large extent determined by diffusion.

Manuscript received November 11, 1985; revised July 7, 1986. G. Amaratunga was with the Department of Electronics and Infom,ation

Engineering, University of Southampton, U.K. He is now with the Engi- neering Department, Cambridge University, Trumpington St., Cambridge, CB2 lPZ, U.K.

N. D. Knee, M. J . Hart, and A. G. R. Evans are with the Department of Electronics and lnformation Engineering, University of Southampton, U.K.

IEEE Log Number 861 1490.

LDGIO(NICm3) 22

I 14

0 5 10 15 20 25 30 35 40 45 50 N M X10-2

Fig. 1. Profiles of (curve a) 5E15 and (curve b) 2E16 atoms/cmz, 75-keV implanted As after 900"C, 15-min anneals. 0 SIMS (u), D SIMS (b), * electrical (a), X electrical (b) , --- SUPREM 111, and - SPS-1D.

14

0 5 10 15 20 25 30 35 40 45 50 N M X 1 0-2

Fig. 2. Profiles of (curve a) 5E15 and (curve b) 2E16 atoms/cm*, 75-kev implanted As after lOOO"C, 20-min anneals. 0 SIMS (a), V SIMS (b), * electrical (a) , X electrical (b) , --- SUPREM 111, and ___ SPS-1D.

11. EXPERIMENTS Two doses of arsenic, 5.OE15 and 2.OE16 ions/cm2, were im-

planted at two energies, 75 and 140 keV, into (100) p-type silicon of different background concentrations, 4.OE14, 4.OE15, and 4.OE16 atoms/cm3. All the implants were done at an 8" tilt at a dose rate to keep the temperature rise below 300°C. The implanted samples were then capped with 1000 A of LTO and annealed at 900°C for 15 min or 1000°C for 20 min, respectively, in an Nz ambient. Samples were also electron-beam annealed using the isothermal mode [2] .

Profiling of the annealed samples was carried out using SIMS. The furnace-annealed samples were also profiled using four-point probe resistivity measurements to obtain the electrically active concentration. Figs. 1 and 2 show the profiles obtained for the 900 and 1000°C furnace anneals.

0018-9383/87/0200-0445$01.00 @ 1987 IEEE


111. MODELING OF As PROFILES

The implantation of As+ into Si was modeled using a Pearson type IV probability density distribution as suggested by Ryssen [l]. For clarity the essential features of this type of distribution are given below. If the As+ ions are implanted into an amorphous tarzet, then, using.two-body collision theory for the implanted and ta :get atoms, a Gaussian distribution can be used to predict the distnbu- tion of the implanted ions at any given energy [ 11.

. . .. . n.

f ( x ) ='- exp { - (x - RJ2/2x$) 1

2?m,

and

C(X) = D u m (1)

where D , is the implanted dose, Rp is defined as the projected range, and

Xd is the standard deviation

xd = p2 = ja --u (x - R,)'f(x) dx. ( 3 )

p1 and p2 are defined as the first and second moments of the disl h- bution. Higher order moments are defined as

pj = la (x - Rp)Y(x) dx i = 3 , 4 , . * . :4) --oI

A key feature of the Gaussian distribution is its symmetry about Rp. However, in practice, distributions of implanted ions (even in amorphous targets) are nat symmetrical about the first moment. The use of two different standard deviations on either side of Rp has been proposed to take into account the observed asymmetly. Reasonable agreement with the experiment has been obtained f'or concentration values over two or three orders of magnitude for '4s in amorphous material (SO,) [3] with this type of jointed Gaussi un distribution. For the formation of source-drain regions As' is implanted into crystalline Si. Even though the tilt of the Si slice should make the target appear amorphous, there is a finite probability for implanted ions to travel in channel of the lattice. This effectively increases ion penetration in a crystalline target compared with a corresponding amorphous target [ 1 J , [4], and leads to an asyrl- metry in the implant profile that cannot be adequately fitted with a jointed Gaussian distribution. A Pearson type IV distribution USIS

two higher order moments, p3 and p4, and is capable of providing a good fit to the observed asymmetry.

Defining the third- and fourth-order moment ratios to be

P = pdx; ( ( 9

respectively, and the following five constants in terms ofxd, 7, and P [I]:

A = lop - 12y2 - 18

a = -xdy(P + 3)/A

bo = -X; (40 - 3yz)/A

bl = a

b2 = -(2P - 3y2 - 6)/A. (7)

The Pearson type IV distribution (C(x)) for the implanted dose D,, is then given as

13tYIUU~UrlLU~LLULIULLllLY~YYYL~LLYLYll"v-~.lLUUY,LIYYI~I~IIULLL;/ 0 5 10 15 20 25 30 35 40 45 50

NM X10-2

Fig. 3. Modeled and measured profile of 2E16 atoms/cmz, 75-keV planted As in Si. X SIMS, - 0 - SUPREM 11.5, --- SUPREM and - SPS-1D.

im- 111,

0 5 10 15 20 25 30 35 40 45 50 P M X I O - ~

Fig. 4. Profiles of (curve a) 5E15 and (curve b) 2E16 atoms/cm2, 75-keV implanted As after 7.5-s electron-beam anneals. * SIMS (a) , o SIMS (b) , and - SPS-1D. (c) 5E15 and ( d ) 2E16 atoms/cm2, 140 kev- implanted As after 7.5-s electron-beam anneals, 0 SIMS (c), SIMS ( d ) , and - SPS-ID.

f * ( ~ ) = [b& - RJ2 + b,(x - R,,) +

where K is a normalizing constant and can be calculated by nu- merical integration

K = l/l0=f "(4. (9)

The first three moments for As in Si have been calculated from collision theory and tabulated as a function of implant energies. An empirical relation between the third- and fourth-order moments proposed in [l] has been used in this work.

P > Pmin = 48 + 397' + 6(y2 + 4)1.5

32 - y2

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 2. FEBRUARY 1987 447

The original suggestion for 0 in the case of As in Si was 0 = Pmin 1141. This is not strictly correct as @ = Pmin defines a Pearson type V distribution [13], which is not suitable for modeling ion implantation. It must be noted that only the Pearson type IV distribution has the mathematical and practical ability to model ion implantation, and the inequality in (10) must be satisfied to obtain such a distribution [ 131. The authors have found that the best fits for the profiles in Figs. 1, 3 , and 4 are obtained with 0 = 1.12 Pmin. These figures show as-implanted low-temperature (900°C), and electron- beam annealed As profiles at the two doses. In all cases the chan- neling that occurs during implantation can be seen after the anneals. The jointed Gaussian profiles used for modeling the same implant from the SUPREM 11.5 and SUPREM 111 [6] simulators are also shown in Fig. 3. The profile modeled by the Pearson IV distribution with the modified fourth-moment ratio is in very good agreement with the experiment.

The modeled profiles include diffusion effects that are calculated numerically using a finite difference scheme. Also shown in Figs. 1 and 2 are the profiIes obtained from the SUPREM 111 process simulator with a jointed Gaussian used to model As' implantation in Si. All the physical conditions included in SUPREM for diffusion: vacancy enhancement, electric field enhancement, and clus- tering are also included in the SPS-1D simulator, which uses a Pearson IV for the implantation [6]. The electron-beam-annealed implants have been modeled numerically using simulated time- temperature profiles, together with rapid diffusion effects caused by defect redistribution [7].

IV. DISCUSSION Figs. 1, 3 , and 4 show clearly that better agreement with the

experimental profiles is obtained by using a Pearson IV distribution for implantation rather than a jointed Gaussian. For'the 900°C anneal negligible shifi from the implanted profiles is caused by diffusion and therefore an accurate implant model is essential to predict junction depths. The junction depths predicted using the jointed Gaussian profile of SUPREM 111 are shallower than those predicted by SPS-ID, which uses a Pearson IV distribution as seen in Table I. It should be noted that the discrepancy in predicted junction depths would be smaller at higher background concentrations. This is shown in Table I where the junction depths at a high background are also tabulated. The SIMS measurements are in good agreement with the Pearson IV profiles for concentrations above 5.OE17. SIMS measurements of the electron-beam-annealed samples (Fig. 4) also show the tailing caused by asymmetry in the implant profiles. The small amount of diffusion taking place during the electron-beam anneals is well modeled by the transient diffusion enhancement in- corporated in SPS-1D.

For the samples that were furnace annealed at 1000°C for 20 min, the modeled profiles obtained from SUPREM III and our simulator SPS-1D are similar (see Fig. 2). Here the diffusion of dopant atoms dominates the profile obtained from both simulators, making the choice of initial implant model of little importance.

These results have some interesting implications for the fabrication of n-channel MOS devices with As source-drain regions:

1) In terms of vertical junction depths there is no advantage in furnace annealing at temperatures below 1000°C. Below this temperature level the junction depths are determined by implantation phenomena and not by diffusion. In fact by lowering anneal temperatures you pay the penalty of higher sheet resistance without significantly reducing the junction depths. For example, it is seen from Fig. 2 that the 5E15 75-keV As implant that was annealed at 1$04"C has achieved almost complete activation and is only 200 A deeper than the 900°C 5-mir: anneal. The sheet resistivities are 33 and 52 Q/O , respectively. If the background concentration is increased to 5E16 n/cm3 for this implant, typical for a g-well CMOS process, the 1000°C anneal would still only be 400 A deeper.

2) There is no major advantage gained by using transient annealing for the lower dose As source-drain implantations. Elec- tron-beam annealing does not cause a significant reduction in junc-

TABLE I JUNCTION DEPTHS PREDICTED AT BACKGROUNDS OF 4E14 A N D 5E16

ATOMS/Cm3 FOR 900°C 15-min ANNEAL FROM SUPREM 111, WHICH USES JOINTED GAUSSIAN, AND SPS-ID, WHICH U S E S

A PEARSON IV

Implantation 1 Dose 1 s~~ 111 lL~arson IV Energy (atoms/cmZ) Gausian SPS-ID

Jointed

75KeV 5E15 B g 4 E 1 4 Bg=5ElG B g 4 E 1 4 Bp=5EIG 1950% 1600x ZSSOi? Zi00.8

2E1G 2050A 17508 3150x 23008 - ~ ~~ -

TABLE I1 SHEET RESISTIVITrES Q/U

(Figures in brackets for the electron-beam-annealed samples are the measured peak temperatures for the isothermal 7.54 anneals (6 s for the 80-keV implant).)

Implant Energy

ions/crn-'

(GV) 5E15

5x10l5

bSC?

2E16 Anneal 2 x 1016

75 j :(:OS@C) 40(1048°C) electron beam 50 900°C 15 m<n

tion depth due to the reasons stated above in 1). Also, as can be seen in Table 11, the electron-beam anneals do not give sheet resistivities as low as the 1000°C 20-min anneals. Even for a 1200°C peak temperature electron-beam anneal of a 5E15 80-keV implant the resultant sheet resistivity is only reduced to 40.8 Q/U . For the 2E16 n/cm2, 75-keV implant it is more realistic to consider the junction de th at a practical background (well) concentration of 5E16 n/cm P . At this background concentration electron-beam annealing will reduce the junction depth to 0.23 pm as opposed to 0.34-0.35 pm for the 1000°C furnace anneal; see Fig. 4. How- ever, when the sheet resistance obtained for the two doses using electron-beam anneals in Table TI are compared, 46 and 41 Q/D, there seems to be little advantage in using rapid thermal annealing for high As doses. Although there are no advantages of electron- beam annealing for these implantations when considered in isola- tion, there can be considerable advantages when they are part of a CMOS process. Here the diffusion of Boron source-drain regions will be greatly reduced 181.

3). For p-well CMOS structures that are low-temperature furnace or transient annealed, the reduction of well depth required for higher packing densities and smaller device dimensions must take into account deep As penetration during implantation. Otherwise, as shown in Figs. 1 and 4, deep junctions may result in a significant lowering of the well punchthrough voltage. The other advantages of having shallow junctions, such as lower latchup susceptibility and higher source-drain punchthrough voltages wiIl also be dimin- ished.

4) For self-aligned poly-Si gate fabrication processes, the poiy- Si gate must be thick enough so as to completely mask the channel region during source-drain implantation. If the implant model of As in poly-Si does not take into account these same deep penetration effects, the gate poly-Si thickness chosen may not adequately mask the channel and hence lea4 to threshold degradation [9].

It should be noted that points 1) and 2) should be reconsidered in the light of possible lateral diffusion of the source-drain profiles, which is of great significance for short-channel NMOS devices. Experimental techniques presently 'available do not allow for the accurate measurements of the lateral profiles needed to investigate lateral ion penetration during implantation. It is also possible to use electron-beam annealing (or RTA in general) and preserve the channeled tail region of the as-implanted profile, whilst getting lower sheet resistivities than obtained with low-temperature fur-


nace annealing. The lowering of the concentration gradien: adja- cent to the junction in this manner will improve punchthrough and junction breakdown characteristics of the source-drains due to the removal of the sharp concentration gradients present at jux t ion after high-temperature furnace annealing.

A main point that can be seen from the results is that, fo: both the implant doses, deep penetration of As is observed. This t,eems to corroborate the results presented in 141, which suggest that it is predominantly the first small fraction of the implanted ions that channel in the Si lattice. As more ions are implanted, the Si ha ice is damaged and becomes more like an amorphous target. The preamorphization of the crystalline Si target using inert, e.g., Ne or Si ions is a possibility to reduce this deep penetration 141, I BO]. However, there is evidence that at low implantation energiex: the profile of implanted As is not changed by preamarphization I? 11, [12]. This is probably due to a small fraction of the implanted dose traveling beyond the amorphized region and rechanneling to ;:ive the observed tails on the profiles. The proportional increase of the tail concentration with dose in Figs. 1 and 4, and the ineffect ve- ness of preamorphization in removing the tail [1 l j , [12j point ; to rechanneling being a major factor in causing deep penetratior of implanted As. In this event it may be necessary to use boron courther doping to reduce As source-drain junction depths.

V. CONCLUSIONS It has been shown that As source-drain junctions resulting from

low temperature and transient anneals are significantly deeper than expected from process simulators such as SUPREM 1 1 . 5 and TI (using default parameters) due to the asymmetry in the implant profile of As in Si. The junction depths and the profiles can be accj- rately predicted using Pearson type IV distributions to model As implantation in Si. Due to the deep penetration of implanted A ;, the junction depths determined by implantation phenomena remain unchanged after anneals with relatively high-temperature time ,products (e.g., 900°C X 15 min). Consequently low-temperature furnace and rapid thermal annealing used to reduce diffusion caa lead to an increase in sheet resistance with no significant reduction in junction depth.

ACKNOWLEDGMENT The authors would like to thank Dr. P. Rosser of Standard Tele-

cxnmunication Labs., U.K., for making available the SUPREM 111 simulator.

REFERENCES

H. Ryssel and K. Hoffman, “Ion implantation,” in Process and De- vice Simulation for MOS-VLSI Circuits. The Hague: Martiuns Niihoff, 1983. M. J. Hart and A. G. R. Evans, “A scanning electron-beam annealer with electrostatic deflection systems,” J . Phys. Earth, vol. 18, pp. 303-306, May 1985. J. Nakata and K. Kajiyama, “Precise profiles for arsenic implanted in Si and SiOz over a wide implantation energy range,” Japan. J . Appl. Phys., vol. 21, pp. 1363-1369, Sept. 1982. J. M. Fairfield and B. L. Crowder, “Ion implantation doping of silicon for shallow junctions,” Trans. Met. Sac AIME, vol. 245, pp. 469-473, Mar. 1969. C. P. Ho, I. D. Plurnmer, S, E. Hansen, and R. W . Dutton, “VLSI process modeling-SUPREM 111,” IEEE Truns. Electron Devices,

R. B. Fair, “Concentration profiles of diffused dopants in Si,” in hpuri& Doping Processes in S i , F. F. Y. Wang, Ed, New York: North Holland, 1981. R. B. Fair, J. J. Wortman, and 3 . Liu, “Modelling rapid thermal diffusion of arsenic and boron in silicon,” J. Electrochem. SOC., vol.

R. A. McMahon, D. G . Hasko, and H. Ahmed, “Electron-beam pro- cessing of MOS devices with shallow junctions,” Solid State Tech- nol., pp. 208-214, June 1985.

V O ~ . ED-30, pp. 1438-1452, NOV. 1983.

131, pp. 2381-2394, Oct. 1984.

191 K. A. Sabine, G. A. J. Amaratunga, and A. G. R. Evans, “Threshold shift of NMOS transistors due to high energy arsenic sourceidrain implantation,” Proc. IEE, pt. I, pp. 163-166, June 1985.

[lo] A. L. Butler and D. J. Foster, “The formation of shallow low-resistance source-drain regions for VLSI CMOS technologies,” ZEEE Trans. Electron Devices, vol. ED-32, pp. 150-155, Feb. 1985.

[ I l l G. Fernholz and F. Schulte, “Methods of steepening ion implanted profiles,” Annual Report, (Institute of Semiconductor Electronics, Aachen Technical University, W. Germany), pp. 68-69, 1984.

[12] T. E. Seidel, D. J. Lishner, C. S. Pai, R. V. K. Noell, D. M. Maher, and D. C. Jacobson, “A review of rapid thermal annealing of B, BF, and As Ions implanted into Si,” Nucl Inst. Meth. Phys. Res., vol.

[13] S. Selberherr, Analysis and Simulation of Semiconductor devices. Vienna: Springer-Verlag, 1984, ch. 3, pp. 50-58.

[14] H. Ryssel, K. Harherger, K. Hoffman, G. Pinke, R. Dimcke, and A. Sachs, “Simulation of Doping Processes,” IEEE Trans. Electron De- vices, vol. ED-27, pp. 1484-1492, Aug. 1980.

B7/8, pp. 251-260, 1985.

Relationship Between Measured and Intrinsic Transconductances of FET’s

S. Y. CHOU AND D. A. ANTONIADIS

Abstract-In exploratory study of FET’s, such as the study of deep- submicrometer-channel FET’s, carrier transport quantities are ex- tracted from the measured transconductance of a FET. The extraction requires that the intrinsic transconductance of the device be calculated from the measured one, which is generally degraded by source and drain parasitic resistances. We have derived an equation that allows the calculation of the intrinsic transcondhctance of a FET from the measured transconductance, under the assumption that source and drain series resistances are independent of bias. The derivation does not assume zero drain conductance, nor does it involve any specific FET model. Therefore, the derived equation works in both saturation and linear regions of a FET, regardless of its channel length. The equation was tested by adding external resistors in series with source or drain of ultra-short-channel MOSFET’s. Within the accuracy of the measurements, experimental results have proved that the equation is correct.

I. INTRODUCTION The measured transconductance of a FET g, is always smaller

than the intrinsic transconductance.gmi because of the effect of source-drain series resistance. In the case of high source-drain series resistance and/or of high intrinsic transconductance, the difference between the g, and gmi can be large. Since the intrinsic transconductance i s directly related to the FET theory and in par- ticular carrier transport properties, it is often required to extract accurately the intrinsic transconductance from the measured one. However, the commonly used equation 111, [2]

Manuscript received May 20, 1986; revised July 22, 1986. This work was supported by the Joint Services Electronics Program.

S. Y . Chou was with the Department of Physics, Massachusetts Institute of Technology, Cambridge, MA 02139. He is now with the Department of Electrical Engineering, Stanford University, Palo Alto, CA 94305.

D. A. Antoniadis is with the Department of Electrical Engineering and

02139. Computer Science, Massachusetts Institute of Technology, Cambridge, MA

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implantation-dominated junction depths of low-temperature and electron-beam-annealed as...

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